CN2805082Y - Package carrying plate for integrated circuit - Google Patents
Package carrying plate for integrated circuit Download PDFInfo
- Publication number
- CN2805082Y CN2805082Y CN 200520012408 CN200520012408U CN2805082Y CN 2805082 Y CN2805082 Y CN 2805082Y CN 200520012408 CN200520012408 CN 200520012408 CN 200520012408 U CN200520012408 U CN 200520012408U CN 2805082 Y CN2805082 Y CN 2805082Y
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- insulating cement
- pins
- carrier plate
- wafer holder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model provides a package carrying plate for an integrated circuit. The carrying plate is rectangular. A plurality of package units are arranged in a matrix mode to form the utility model. Hollow space is respectively formed between pins on the package units and a wafer seat and between the pins. A plurality of layers of insulating glue which is formed in a stacking mode is filled in the hollow space. More than one group of electrical assemblies is positioned in the layers of insulating glue in a built-in mode. Each group of electrical assemblies comprises conducting holes, wherein the number of the conducting holes is the same as the number of the layers of insulating glue. Each conducting hole is respectively arranged in each layer of insulating glue. The adjacent ends of each conducting hole are electrically communicated with a conducting wire. The electrical assemblies are arranged, which leads two far pins on the carrying plate to be directly or indirectly electrically communicated.
Description
Technical field
The utility model is relevant with integrated circuit board, is meant a kind of integrated circuit encapsulating carrier plate especially.
Background technology
Progress along with science and technology, the consumer requires that electronic product is light, thin, short, little to have become trend, so the usefulness of integrated circuit also constantly promotes, thereby for integrated circuit (1C) carrying support plate also constantly the improvement progress greatly, to up-to-date crystalline substance (cip chip) technology of covering, and the utility model is the design that progresses greatly of doing at the encapsulation technology of QFN (quad flat does not have the excurvation pin-type) especially from early stage conductive metal frames.
The semiconductor packages of looking into QFN (quad flat does not have the excurvation pin-type) is existing for many years, the preceding patent that many approvals are arranged, there is the dealer between each pin of support plate (as conductive metal frames), to etch partially the formation hollow space earlier, fill insulation glue and form a smooth table top on this hollow space again, each pin is stable on the support plate, this platform can be established outside the above wafer holder bearing wafer, also can establish plural passive device, or on the support plate unit are, set up a plurality of electronic components, can effectively promote the space availability ratio of support plate.
Said method is clogged in this hollow out position with insulating cement has increased the support plate usable area, but these passive devices can only with adjacent pin cross-over connection, when being necessary to be electrically connected distance two pins far away because of chip design is not enough, countermeasure is not then arranged, this still need improve part for it.
The utility model content
Main purpose of the present utility model is to provide a kind of integrated circuit encapsulating carrier plate, can make the pin electrical communication of two apart from each others.
For achieving the above object, the integrated circuit encapsulating carrier plate that the utility model provides is formed with the matrix-style arrangement by plural encapsulation unit, and wherein respectively this encapsulation unit includes:
Wafer holder more than one, these wafer holder are provided with corresponding wafer;
The plural number pin, be arranged in this wafer holder periphery, between these pins and this wafer holder and these pins be hollow space each other;
Also include:
The insulating cement that plural layer is above piles up and clogs in this hollow space;
One group of above electrical assembly, each is organized electrical assembly and includes the via identical with these insulating cement numbers of plies, and each via distinctly is arranged in each layer insulating cement, and respectively this via abutting end is interconnected so that a lead is electric.
Wherein respectively respectively this via of this electrical assembly is located at respectively in this insulating cement of different layers.
Wherein these vias in the superiors' insulating cement can be established a lead respectively and are electrically connected with this adjacent pin out of the ordinary.
Wherein these vias in the superiors' insulating cement can be established a passive device respectively and are electrically connected with this adjacent pin out of the ordinary.
Wherein these vias in the orlop insulating cement can be established a lead respectively and are electrically connected with adjacent pin out of the ordinary.
Description of drawings
In order to describe structure of the present utility model and characteristics place in detail, lift following four preferred embodiments and conjunction with figs. explanation as after, wherein:
Fig. 1 is the encapsulation unit vertical view of the utility model first preferred embodiment.
Fig. 2 is the encapsulation unit profile of the utility model first preferred embodiment.
Fig. 3 is the encapsulation unit profile of the utility model second preferred embodiment.
Fig. 4 is the encapsulation unit profile of the utility model the 3rd preferred embodiment.
Fig. 5 is the encapsulation unit profile of the utility model the 4th preferred embodiment.
Embodiment
As shown in Figures 1 and 2, a kind of integrated circuit encapsulating carrier plate that the utility model first preferred embodiment is provided, mainly form (not shown) with rectangular arrangement by a plurality of encapsulation units (11), this each encapsulation unit (11) is the quad flat shape, mainly formed by a wafer holder (12a), plural pin (13), an insulating cement (14), one group of electrical assembly (15), wherein:
This wafer holder (12a), utilize the adhesive corresponding wafer of tin cream (16a), and these pins (13), be positioned at outside this wafer holder (12a) and and be arranged in this encapsulation unit (11) periphery according to predetermined way, and between these pins (13) and this wafer holder (12a) and the mutual interval of these pins (13) preset distance is hollow space therebetween;
This insulating cement (14), comprised two layers insulating cement (14a) (14b), pile up and clog, and make these pins (13), this wafer holder (12a) and this insulating cement (14) be combined to form a complete table top in this hollow space.
This electrical assembly (15), include two vias (151a) (151b) and a lead (152), wherein: these vias (151a) (151b), be located at respectively in the ground floor (14a) and the second layer (14b) of these insulating cements (14), the insulation glue-line (14a) that these vias (151a) (151b) connect its place respectively (14b), in addition, utilize a lead (152) of no electrolytic nickel gold material to be layed between these insulating cements (14) ground floors (14a) and the second layer (14b), and connect this two via (151a) (151b), again the via (151a) that (17b) connects this electrical assembly lower floor and upper strata respectively by two leads (17a) (151b) and out of the ordinary adjacent two pins (13a) (13b), two pins (13a) of apart from each other (13b) are electrically connected each other, solve the problem that the some leads (17) between connection pin (13) can't interlock on single plane, and increased the integrated circuit board utilization of space.
The utility model second preferred embodiment as shown in Figure 3, be in this encapsulation unit (11) and none lead (17a) with the first preferred embodiment difference, its bottom of one via (151a) exposes to this insulating barrier (14a), therefore can be used as a pin and is connected with other electric component.
The utility model the 3rd preferred embodiment as shown in Figure 4, itself and the second preferred embodiment difference are to replace a lead (17b) with a passive device (18) in this encapsulation unit (11), are the mode of this electrical assembly (15) of another kind of electrical communication with a pin (13b).
The utility model the 4th preferred embodiment as shown in Figure 5, being in this encapsulation unit (11) that they are different with first preferred embodiment replaces a lead (17b) with a passive device (18), is the mode of this electrical assembly (15) of another kind of electrical communication with a pin (13b).
In addition, the utility model is not limited to the insulating cement two layers of this hollow space fillings, also is not limited to only be provided with one group of electrical assembly in insulating cement, for example, can clog insulating cement more than three layers in this hollow space, the electrical assembly more than two groups also can be set in insulating cement.
The foregoing description is implemented mode of the present utility model for several are provided, and does not limit execution mode of the present utility model and only limits to above-mentioned mentioned mode.
Comprehensive above-listed described, the utility model provides a kind of integrated road support plate of multilayer circuit, utilize filling multilayer insulation glue, and via and route wires be set therein, directly or by the indirect pin that is electrically connected two apart from each others more than a group of passive device, further also increased the current densities of integrated circuit, made integrated circuit have more efficient with encapsulating carrier plate with encapsulating carrier plate.
Claims (5)
1. an integrated circuit encapsulating carrier plate is formed with the matrix-style arrangement by plural encapsulation unit, and wherein respectively this encapsulation unit includes:
Wafer holder more than one, these wafer holder are provided with corresponding wafer;
The plural number pin, be arranged in this wafer holder periphery, between these pins and this wafer holder and these pins be hollow space each other;
It is characterized in that, also include:
The insulating cement that plural layer is above piles up and clogs in this hollow space;
One group of above electrical assembly, each is organized electrical assembly and includes the via identical with these insulating cement numbers of plies, and each via distinctly is arranged in each layer insulating cement, and respectively this via abutting end is interconnected so that a lead is electric.
2. according to the described integrated circuit encapsulating carrier plate of claim 1, it is characterized in that wherein respectively respectively this via of this electrical assembly is located at respectively in this insulating cement of different layers.
3. according to the described integrated circuit encapsulating carrier plate of claim 1, it is characterized in that wherein these vias in the superiors' insulating cement can be established a lead respectively and are electrically connected with this adjacent pin out of the ordinary.
4. according to the described integrated circuit encapsulating carrier plate of claim 1, it is characterized in that wherein these vias in the superiors' insulating cement can be established a passive device respectively and are electrically connected with this adjacent pin out of the ordinary.
5. according to the described integrated circuit encapsulating carrier plate of claim 1, it is characterized in that wherein these vias in the orlop insulating cement can be established a lead respectively and are electrically connected with adjacent pin out of the ordinary.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520012408 CN2805082Y (en) | 2005-04-13 | 2005-04-13 | Package carrying plate for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520012408 CN2805082Y (en) | 2005-04-13 | 2005-04-13 | Package carrying plate for integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2805082Y true CN2805082Y (en) | 2006-08-09 |
Family
ID=36910367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200520012408 Expired - Lifetime CN2805082Y (en) | 2005-04-13 | 2005-04-13 | Package carrying plate for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2805082Y (en) |
-
2005
- 2005-04-13 CN CN 200520012408 patent/CN2805082Y/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20150413 Granted publication date: 20060809 |