CN103650133A - Techniques for wafer-level processing of QFN packages - Google Patents

Techniques for wafer-level processing of QFN packages Download PDF

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Publication number
CN103650133A
CN103650133A CN201280002459.4A CN201280002459A CN103650133A CN 103650133 A CN103650133 A CN 103650133A CN 201280002459 A CN201280002459 A CN 201280002459A CN 103650133 A CN103650133 A CN 103650133A
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post
wafer
integrated circuit
packaging structure
chip
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CN201280002459.4A
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CN103650133B (en
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V·卡恩德卡尔
K·坦比杜赖
A·阿什拉夫扎德
A·科尔卡
H·D·阮
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

Description

The wafer-level process technology of QFN encapsulation
Background technology
For example the flat no-lead encapsulation technology of four limit flat no-lead (QFN) encapsulation technologies, physically with is electrically connected to printed circuit board (PCB) by integrated circuit (IC) chip.Flat no-lead encapsulation technology is typically used lead frame, and this lead frame comprises the integrated circuit (IC) chip (wafer) being mounted thereon.This wafer can be electrically connected to lead frame mutually by line joining technique or flip chip technology (fct).On lead frame, form subsequently packaging structure, with encapsulated integrated circuit chip.
Summary of the invention
Described the technology for the manufacture of wafer-level packaging semiconductor device, it for example has, similar in appearance to using flat no-lead (, the QFN) form factor of the form factor of encapsulation technology device.In one or more execution modes, wafer-level packaging device comprises integrated circuit (IC) chip (for example, wafer), and it has at least one post (for example, copper post) in the integrated circuit (IC) chip of being formed at.Post is configured to provide mutual electrical connection to integrated circuit (IC) chip.The packaging structure that is configured to support this post is formed on the surface of integrated circuit (IC) chip.In one or more execution modes, the second integrated circuit (IC)-components can be mounted to integrated circuit (IC) chip, thus integrated circuit (IC)-components and integrated circuit (IC) chip electric connection.The second integrated circuit (IC)-components is packed by packaging structure at least in part.
Above-mentioned general introduction is provided, and to introduce the selection of the concept of reduced form, it will be further described in describing in detail below.This general introduction is not intended to determine key feature or the essential characteristic of claimed theme, is not intended to the scope of determining claimed theme as auxiliary yet.
Accompanying drawing explanation
Describe detailed explanation with reference to the accompanying drawings.In the different embodiment of specification and accompanying drawing, use identical Reference numeral can represent similar or identical project.
Fig. 1 has been example according to the perspective view of the wafer-level packaging device of illustrative embodiments of the present disclosure.
Fig. 2 A is the partial side view in cross section along the wafer-level packaging device portions shown in Fig. 1 of plane 2A-2A.
Fig. 2 B is the partial side view in cross section along the wafer-level packaging device portions shown in Fig. 1 of plane 2B-2B, and wherein, wafer-level packaging device comprises integrated circuit (IC)-components.
Fig. 3 has been example for the manufacture of the flow chart of the process in the illustrative embodiments of the wafer-level packaging device of for example device shown in Fig. 1 to 2A.
Fig. 4 A to 4I has been example according to the process shown in Fig. 3, for example, in the partial side view in cross section of the manufacture of the wafer-level packaging device of the device shown in Fig. 1 and 2A.
Embodiment
summary
Use the device of the flat no-lead encapsulation technology of QFN encapsulation technology for example by integrated circuit (IC) chip is contained in encapsulation completely, and provide good mechanical protection to the integrated circuit (IC) chip (wafer) being included in device packing.For example, for example, yet (, QFN) packaging production is very expensive, and relatively low pin number (, the pin of QFN is typically along Waffer edge location) is typically provided for flat no-lead.
Wafer-level packaging is the wafer-level package technology that comprises multiple technologies, and thus, before cutting apart, integrated circuit (IC) chip is packed with wafer scale.Wafer-level packaging expansion wafer manufacture process, to comprise that device interconnects and device protection process.Therefore, wafer-level packaging is by allowing to make course of processing pipelining with the integrated wafer manufacture of wafer scale, encapsulation, test and burned process.Compare with flat no-lead (QFN) encapsulation technology, wafer-level packaging realizes conventionally more cheaply, because encapsulation occurs with wafer scale, and flat no-lead encapsulates to be with level (strip level) to carry out.And taking up room of comparable wafer-level packaging device is typically less than taking up room of QFN packaging, because wafer-level packaging can be no better than the size of integrated circuit (IC) chip.
Therefore, described the technology of manufacturing semiconductor device with Wafer level packaging, this semiconductor device has similar in appearance to the form factor of using those devices of flat no-lead (QFN) encapsulation technology.Therefore the mechanical protection being included in similar in appearance to the integrated circuit (IC) chip (wafer) in the device package being provided by flat no-lead (QFN) device can be provided wafer-level packaging device; the intrinsic benefit (for example, low-cost, little package dimension, high pin number etc.) that simultaneously keeps wafer-level packaging.Wafer-level packaging device comprises integrated circuit (IC) chip (for example, wafer), and it has to device provides electric interconnective post.In concrete enforcement, post can be copper post, and it has the solder layer (solder layer) in the exposed ends that is formed at post.The packaging structure that is configured to support this post is formed on the surface of integrated circuit (IC) chip with wafer scale.In an embodiment, packaging structure can be manufactured by epoxy resin or similar substance.In one or more execution modes, the second integrated circuit (IC)-components can be mounted to integrated circuit (IC) chip, so that integrated circuit (IC)-components and integrated circuit (IC) chip electric connection.The second integrated circuit (IC)-components is packed by packaging structure at least partly.Once from wafer separate, device can be mounted to printed circuit board (PCB), and the back of post by the device that is connected with the phase of solder joint of printed circuit board (PCB) provides mutual electrical connection.
illustrative embodiments
Fig. 1 to 2B example according to the semiconductor packing device 100 of illustrative embodiments of the present disclosure.In some embodiments, semiconductor packing device 100 can comprise wafer-level ball integrate circuit packaging.As shown in the figure, device 100 comprises integrated circuit (IC) chip 102, and this integrated circuit (IC) chip 102 forms by having one or more semiconductor substrates 104 that are formed at integrated circuit 106 wherein.In various execution modes, integrated circuit 106 can comprise digital integrated circuit, analog integrated circuit, composite signal integrated circuits, its combination etc.Integrated circuit 106 can form by suitable FEOL process (FEOL) manufacturing technology.
Device 100 further comprises the post 108 extending from the surface 111 of semiconductor substrate 104.In execution mode, post 108 is via the suitable course of processing, the copper post that for example dual stack/deposition process described herein is manufactured.Post 108 can have from about 1 to 1 (1: 1) to the depth-width ratio (aspect ratio) (ratio of the width of post and the height of post) of about 20 to 1 (20: 1) scope.In specific example, depth-width ratio can be in about 5 to 1 (5: 1) to the scope of about 15 to 1 (15: 1).Post 108 is for providing mutual electrical connection the between integrated circuit (IC) chip 102 and printed circuit board (PCB), and printed circuit board (PCB) is configured to accept device 100.As shown in Fig. 2 A and 2B, post 108 comprises the solder layer 110 (for example, from the far-end of substrate 104) on the end 112 that is arranged in exposure, with for example, as being connected between device 100 (, post 108) and the corresponding solder joint being arranged on printed circuit board (PCB).In execution mode, solder layer 110 can be manufactured by lead-free solder composition, for example tin-silver-copper (Sn-Ag-Cu) solder (that is, SAC), Xi-Yin (Sn-Ag) solder, tin-copper (Sn-Cu) solder etc.
In some embodiments, device 100 can comprise second integrated circuit (IC)-components 114 (for example, integrated antenna package device) on the surface 111 that is arranged in (and being mounted to) integrated circuit (IC) chip 102.In an embodiment, the second integrated circuit (IC)-components 114 can with the integrated circuit 106 phase electric connections of integrated circuit (IC) chip 102.For example, as shown in Figure 2 B, integrated circuit (IC)-components 114 comprises solder bump 116, and it allows device 114 to electrically contact mutually with device 100.It is upper that solder bump 116 for example can be positioned the reallocation structure (for example redistribution layer (RDL) 118) of crystal wafer chip dimension device 100, for example, to allow being electrically connected between device 114 and device 100 (, integrated circuit 106 etc.).RDL118 can be formed by electric conducting materials such as polysilicon, aluminium, copper.Therefore, integrated circuit (IC)-components 114 is by there being the ability of systematization encapsulation to expand the additional functionality of device 100.In execution mode, integrated circuit (IC)-components 114 can be digital integrated circuit device, analog integrated circuit device, composite signal integrated circuits device etc.Solder layer 110 described above, solder bump 116 can by for example tin-silver-copper (Sn-Ag-Cu) solder, (that is, SAC), the lead-free solder composition of Xi-Yin (Sn-Ag) solder, tin-copper (Sn-Cu) solder etc. be manufactured.Yet, be contemplated that and can use tin-lead (PbSn) solder compositions.
Device 100 also comprises the packaging structure 120 on the surface 111 that is arranged in integrated circuit (IC) chip 102.As shown in Fig. 2 A and 2B, packaging structure 120 is packed post 108 at least substantially.Therefore, support and the insulation (and providing the support of integrated circuit (IC)-components 114 and insulation when device 100 is used integrated circuit (IC)-components 114) of coupled columns 108 is provided packaging structure 120.Post 108 has the length of the degree of depth that at least substantially extends to packaging structure 120.As shown in Fig. 1 to 2B, solder layer 110 extends beyond the plane that the surface 122 by packaging structure 120 limits, to allow solder layer 110 to be connected to the corresponding solder joint of printed circuit board (PCB).In execution mode, packaging structure 120 can be the polymeric material being deposited on the surface 111 of crystal wafer chip dimension encapsulation device 100, such as epoxy resin etc.
manufacture process example
Fig. 3 shows instantiation procedure 200, and it has the semiconductor device of post, for example device shown in Fig. 1 and 2A 100 with Wafer level packaging manufacture.In the process 200 of example, one or more posts are formed on semiconductor crystal wafer at first.As described here, can form post by dual stack/deposition process.Therefore, wafer is divided into single circuit chip (wafer) before the first photoresist layer be formed at (square frame 202) on semiconductor crystal wafer.Fig. 4 A example a part for wafer 300, when FEOL fabrication technique by suitable, this part comprises semiconductor substrate 302, this semiconductor substrate 302 comprises integrated circuit (IC) chip 304.Integrated circuit (IC) chip 304 comprises one or more integrated circuits 306 that are formed at wherein.Substrate 302 can comprise the reallocation structure on the surface 310 that is formed at substrate 302, for example redistribution layer (RDL) 308.As shown in the figure, dielectric layer 312 can also be formed on the surface 310 of substrate 302.Dielectric layer 312 can be the polymer of BCB (BCB), silicon dioxide (SiO 2) etc.The first laminating step is included in (for example,, on RDL308 and dielectric layer 312) application the first photoresist layer 314 on wafer 300.The first photoresist layer 314 can be the synthetic of photopolymer and polyester film, and it can form pattern and etching by one or more suitable dry film lamination process.
The first photoresist layer is formed pattern and etching subsequently, to form the first etching area (square frame 204).Fig. 4 B example the first photoresist layer 314, it illustrates and is formed pattern and etching, to form the first etching area 316.Etching area 316 at least extends to the solder joint of RDL layer 308 through the first photoresist layer 314.
Subsequently electric conducting material is deposited on to (square frame 206) in the first etching area.Fig. 4 C example be deposited on the electric conducting material 318 in the etching area 316 of wafer 300.In one or more execution modes, can use suitable electroplating process, with deposits conductive material 318 in the etching area 316 at photoresist layer 314.Electric conducting material 318 can comprise electric conducting material or other electric conducting materials such as copper, aluminium.
Subsequently the second photoresist layer is applied on remaining the first photoresist layer (square frame 208) and electric conducting material.Fig. 4 D example be deposited on the second photoresist layer 320 on remaining the first photoresist layer 314 and electric conducting material 318.Once deposition, the second photoresist layer is formed pattern and etching, to form the second etching area (square frame 210).Fig. 4 E example the second photoresist layer 320, wherein, the second photoresist layer 320 has been formed pattern and etching, to form one or more the second etching areas 322, etched region (for example, the first etching area 316) before this second etching area 322 is positioned.The degree of depth that etching area 322 extends the second photoresist layer 320, so that electric conducting material 318 exposes at least partly.
Subsequently electric conducting material is deposited in the second etching area, to complete the formation (square frame 212) of one or more posts.Fig. 4 F example be deposited in etching area 322 to form the electric conducting material 318 of post 324.As shown in the figure, the electric conducting material 318 being deposited in etching area 322 contacts with the electric conducting material 318 being deposited in etching area 316 at least partly.In one or more execution modes, electric conducting material 318 (such as copper etc.) is plated in etching area 322, for example, to form post 324 (copper post).
Once post is formed, remove photoresist layer (square frame 214).Fig. 4 C example by suitable stripping process, remove first and second photoresist layer 314 and 320 (referring to Fig. 4 F).In addition, post 324 can stand suitable seed etching (seed etch) process.As mentioned above, integrated circuit (IC) chip device (shown in Fig. 2 B) can be positioned on substrate 302.Integrated circuit (IC) chip device can encapsulate systematization Capacity extension to integrated circuit (IC) chip 304.
Once formation post, packaging structure is formed on wafer, at least substantially to pack post (square frame 216).Fig. 4 H example be formed at the packaging structure 326 on the surface 310 of wafer 300, to provide support and to insulate to integrated circuit 306 and post 324.In an embodiment, a plurality of polymeric layers (such as epoxy resin etc.) can be deposited on surface 310, to form packaging structure 326.Expectation, epoxide resin material can also be deposited on (for example,, on surface 328) on the back of wafer 300.Once form, packaging structure 326 can stand grinding process, for example, to expose post 324 (, exposing the end away from substrate 302 of post 324).As shown in the figure, packaging structure 326 length of extending column 324 (for example, the degree of depth or height) at least substantially.As shown in Fig. 4 H, in execution mode, the first post 324 passes whole packaging structure 326 at least substantially and (for example extends, at least substantially, extend the height of packaging structure 326, the height of the first post 324 is identical with the height of packaging structure 326), and the second post 324 is only local through packaging structure 326 extensions.For example, the second post 324 can be only extends (half of height that for example, the height of the second post 324 be at least about packaging structure 326) through half of packaging structure 326.It should be understood, however, that and can use other post height according to the requirement of wafer level semiconductor packaging.
Subsequently solder layer is applied to post (square frame 218).For example, solder layer 330 (for example, the bright and clean processing of scolder) for example can be formed on, for example, in the exposed ends 332 of (, being applied to) post 324 (, the end away from wafer 300 of post 324).In execution mode, wafer 300 can stand suitable immersed solder process, with application of solder layer 330 on the copper post lead-in wire exposing.Once complete immersed solder process, can use suitable process, so that single integrated circuit chip 304 is divided into single package.
conclusion
Although described subject content for architectural feature and/or process operation, it should be understood that in subject content defined in the appended claims and must not be limited to above-mentioned specific features or behavior.On the contrary, above-mentioned specific features and behavior are disclosed as the exemplary form implementing the claims.

Claims (20)

1. a process, comprising:
On semiconductor crystal wafer, form at least one post;
On described semiconductor crystal wafer, form packaging structure, described packaging structure is packed described at least one post at least substantially; And
Solder layer is applied to described at least one post.
2. process according to claim 1, wherein, forms at least one post and further comprises:
On described semiconductor crystal wafer, apply the first photoresist layer;
Make described the first photoresist layer form pattern and the first photoresist layer described in etching at least partly, to form the first etching area;
Deposits conductive material in described the first etching area;
On described the first photoresist layer, apply the second photoresist layer;
Make described the second photoresist layer form pattern and the second photoresist layer described in etching at least partly, to form the second etching area, described the second etching area is formed on described the first etching area;
Deposits conductive material in described the second etching area, to form described at least one post; And
At least substantially, remove described the first photoresist layer and described the second photoresist layer.
3. process according to claim 1, wherein, forms wrapper and is further included on described semiconductor crystal wafer and deposits epoxide resin material, and described wrapper is packed described at least one post at least partly.
4. process according to claim 1, wherein, described at least one post comprises copper post.
5. process according to claim 1, wherein, the depth-width ratio of described at least one post is from least about 1 to 1 (1: 1) to the scope of at least about 20 to 1 (20: 1).
6. process according to claim 1, wherein, the depth-width ratio of described at least one post is from least about 5 to 1 (5: 1) to the scope of at least about 15 to 1 (15: 1).
7. process according to claim 1, wherein, applies described solder layer and comprises the part that described solder layer is applied to the exposure of described at least one post.
8. a wafer-level packaging device, comprising:
There is surperficial integrated circuit (IC) chip;
At least one post extending from described surface, described at least one post has the end away from described surface, and described at least one post is configured to provide mutual electrical connection to described integrated circuit (IC) chip;
Solder layer described in being arranged on the end of at least one post; And
Be arranged in described lip-deep packaging structure, described packaging structure surrounds described at least one post at least partly.
9. wafer-level packaging device according to claim 8, wherein, described at least one post comprises copper post.
10. wafer-level packaging device according to claim 8, wherein, described packaging structure comprises epoxide resin material.
11. wafer-level packaging devices according to claim 8, wherein, described at least one post comprises a plurality of posts that extend from the surface of described integrated circuit (IC) chip.
12. wafer-level packaging devices according to claim 11, wherein, the first post in described a plurality of posts extends through described packaging structure, and the second post in described a plurality of post extends through the described packaging structure of part.
13. wafer-level packaging devices according to claim 8, wherein, the depth-width ratio of described at least one post is from least about 1 to 1 (1: 1) to the scope of at least about 20 to 1 (20: 1).
14. wafer-level packaging devices according to claim 8, wherein, the depth-width ratio of described at least one post is from least about 5 to 1 (5: 1) to the scope of at least about 15 to 1 (15: 1).
15. 1 kinds of semiconductor device, comprising:
There is surperficial integrated circuit (IC) chip;
At least one post extending from described surface, described at least one post has the end away from described surface, and described at least one post is configured to provide mutual electrical connection to described integrated circuit (IC) chip;
Solder layer described in being arranged on the end of at least one post;
Be arranged in described lip-deep integrated antenna package device; And
Be arranged in described lip-deep packaging structure, described packaging structure surrounds described at least one post and described integrated antenna package device at least partly.
16. semiconductor device according to claim 15, wherein, described at least one post comprises copper post.
17. semiconductor device according to claim 15, wherein, described packaging structure comprises epoxide resin material.
18. semiconductor device according to claim 15, wherein, described at least one post comprises a plurality of posts that extend from the surface of described integrated circuit (IC) chip.
19. semiconductor device according to claim 15, wherein, the depth-width ratio of described at least one post is from least about 1 to 1 (1: 1) to the scope of at least about 20 to 1 (20: 1).
20. semiconductor device according to claim 15, wherein, the depth-width ratio of described at least one post is from least about 5 to 1 (5: 1) to the scope of at least about 15 to 1 (15: 1).
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