CN116110860A - Stack type packaging structure and forming method thereof - Google Patents

Stack type packaging structure and forming method thereof Download PDF

Info

Publication number
CN116110860A
CN116110860A CN202310089871.4A CN202310089871A CN116110860A CN 116110860 A CN116110860 A CN 116110860A CN 202310089871 A CN202310089871 A CN 202310089871A CN 116110860 A CN116110860 A CN 116110860A
Authority
CN
China
Prior art keywords
chip
plastic
metal
plastic sealing
sealing layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310089871.4A
Other languages
Chinese (zh)
Inventor
冒一卉
于婷
周澄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
Original Assignee
National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Center for Advanced Packaging Co Ltd, Shanghai Xianfang Semiconductor Co Ltd filed Critical National Center for Advanced Packaging Co Ltd
Priority to CN202310089871.4A priority Critical patent/CN116110860A/en
Publication of CN116110860A publication Critical patent/CN116110860A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

The invention relates to a stack type packaging structure, which comprises: a substrate having a substrate window in a right portion thereof; a first chip mounted on a left side portion of the substrate, wherein a right side of a back surface of the first chip has a back metal; a first plastic layer; the first plastic packaging glue through hole is electrically connected with the substrate window and the back metal of the second chip; the second chip is mounted on the first chip in a staggered manner, wherein the right side of the back of the second chip is provided with back metal; a second plastic layer; the second plastic packaging glue through hole is electrically connected with the substrate window and the back metal of the third chip; the third chip is mounted on the second chip in a staggered manner, wherein the right side of the back of the third chip is provided with back metal; a metal pillar disposed on a right-side pin of the front surface of the third chip; a third plastic layer; a third plastic packaging glue through hole; the circuit is electrically connected with the metal column and the third plastic packaging glue through hole; and a conductive lead electrically interconnecting the substrate, the first chip, the second chip, and the third chip.

Description

Stack type packaging structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor packaging technology, and more particularly, to a stacked package structure and a method for forming the stacked package structure.
Background
With the continuous updating and upgrading of electronic products, stack packages are rapidly developing in order to meet the digital signals processed at high speed, large storage capacity and flexible storage architecture. The stacked package method of the chips is to stack a plurality of chips on a substrate, and then connect the chips with the substrate by using a wire bonding process. The existing stack type package generally stacks chips step by step, and has the problems of unstable stack structures such as chip positioning offset, inclination and the like while stacking the chips upwards infinitely.
Disclosure of Invention
In order to solve at least some of the above problems in the prior art, in a first aspect of the present invention, a stacked package structure is provided, including:
a substrate having a substrate window in a right portion thereof;
a first chip mounted on a left side portion of the substrate, wherein a right side of a back surface of the first chip has a back metal;
a first plastic layer located on the right side of the first chip;
the first plastic packaging glue through hole is electrically connected with the substrate window and the back metal of the second chip;
the second chip is mounted on the first chip in a staggered manner, wherein the right side of the back of the second chip is provided with back metal;
a second molding layer located on the right side of the second chip;
the second plastic packaging glue through hole is electrically connected with the substrate window and the back metal of the third chip;
the third chip is mounted on the second chip in a staggered manner, wherein the right side of the back of the third chip is provided with back metal;
a metal pillar disposed on a right-side pin of the front surface of the third chip;
the third plastic layer is positioned on the right side of the third chip and wraps the metal column;
the third plastic sealing layer through hole penetrates through the first plastic sealing layer to the third plastic sealing layer;
the circuit is electrically connected with the metal column and the third plastic packaging glue through hole;
and a conductive lead electrically interconnecting the substrate, the first chip, the second chip, and the third chip.
Further, the back metal is divided into a plurality of metal areas according to the electrical properties of the right side pins of the front side of each chip, and the electrical properties of the metal areas are the same as those of the pins right above the metal areas.
Further, the number of the first plastic package through holes is the same as the number of the metal areas of the back metal of the second chip;
the number of the second plastic package glue through holes is the same as the number of the metal areas of the back metal of the third chip;
the number of the second plastic package through holes is the same as that of the right side pins of the third chip.
Further, the first chip is attached to the left side portion of the substrate through a conductive adhesive;
the second chip is mounted on the first chip in a staggered manner through conductive adhesive, wherein the back metal of the second chip is electrically connected with the right side pin of the first chip and the first plastic package adhesive through hole through conductive adhesive;
the third chip is mounted on the second chip in a staggered manner through conductive adhesive, wherein the back metal of the third chip is electrically connected with the right side pin of the second chip and the second plastic package adhesive through hole through the conductive adhesive;
the first plastic sealing layer is equal to the first chip in height;
the second plastic sealing layer is equal to the second chip in height.
Further, the conductive leads electrically interconnect the left side pins of the first, second, and third chips and electrically interconnect the left side pins of the first chip with the substrate.
In a second aspect of the present invention, the present invention provides a method for forming a stacked package structure, including:
arranging back metal on the back of the first chip, the second chip and the third chip;
a first chip is arranged on the left side of the substrate, a first plastic sealing layer is arranged on the right side of the first chip, and then a first plastic sealing through hole penetrating through the first plastic sealing layer is manufactured, wherein the right side of the substrate is provided with a substrate window;
a second chip is arranged on the first chip in a staggered mode, a second plastic sealing layer is arranged on the right side of the second chip, and then a second plastic sealing through hole penetrating through the first plastic sealing layer and the second plastic sealing layer is manufactured;
and a third chip is arranged on the second chip in a staggered manner, a copper column is arranged on a right-side pin on the front side of the third chip, a third plastic sealing layer is arranged on the right side of the third chip, the third plastic sealing layer wraps the copper column, then a third plastic sealing glue through hole penetrating through the first plastic sealing layer to the third plastic sealing layer is manufactured, and finally a circuit for connecting the copper column and the third plastic sealing glue through hole is arranged.
Further, the back metal is divided into a plurality of metal areas according to the difference of the electrical properties of the right side pins of the front side of each chip, and the electrical properties of the metal areas are the same as those of the pins right above the metal areas.
Further, a first chip is firstly attached to a substrate through conductive adhesive, then a first plastic sealing layer with the same height as the first chip is arranged on the right side of the first chip, holes are drilled in the first plastic sealing layer, metal is filled into the holes to form first plastic sealing adhesive through holes, and pins on the left side of the front side of the first chip are connected with the substrate through wire bonding.
Further, the second chip is firstly attached to the first chip through the conductive adhesive, so that the metal on the back surface of the second chip is located above the first plastic package adhesive through hole and is electrically connected with the first plastic package adhesive through hole through the conductive adhesive, and meanwhile, the pin on the right side of the front surface of the first chip is electrically connected with the metal on the back surface of the second chip through the conductive adhesive;
then, arranging a second plastic sealing layer with the same height as the second chip on the right side of the second chip, drilling holes on the second plastic sealing layer, drilling through the first plastic sealing layer, filling metal to ensure the conductivity of the first plastic sealing layer, and forming a second plastic sealing glue through hole, wherein the second plastic sealing glue through hole is electrically connected with the substrate window;
and connecting the left pin on the front surface of the second chip with the left pin on the front surface of the first chip through wire bonding.
Further, the third chip is mounted on the second chip in a staggered manner through the conductive adhesive, so that the back metal of the third chip is located above the second plastic package adhesive through hole and is electrically connected with the second plastic package adhesive through hole through the conductive adhesive, and meanwhile, the right pin on the front side of the second chip is electrically connected with the back metal of the third chip through the conductive adhesive;
arranging copper columns on the right side pins of the front side of the third chip, and then arranging a third plastic layer on the right side of the third chip, wherein the third plastic layer wraps the copper columns, and the tops of the third plastic layer are flush with the tops of the copper columns;
drilling holes on the third plastic sealing layer, drilling through the first plastic sealing layer and the second plastic sealing layer, filling metal to ensure the conductivity of the first plastic sealing layer and the second plastic sealing layer, and forming a third plastic sealing glue through hole which is electrically connected with the substrate windowing;
etching a circuit on the surface of the third plastic sealing layer, and filling metal to form a circuit, wherein the circuit is connected with the copper column and the third plastic sealing layer through hole;
and connecting the left pin on the front surface of the third chip with the left pin on the front surface of the second chip through wire bonding.
The invention has at least the following beneficial effects: in the stack type packaging structure and the forming method thereof, only one side of a chip is electrically interconnected by wire bonding, and the right side of the chip is provided with a plastic sealing layer for supporting the chip at the upper layer, so that unstable stacked structures such as chip positioning offset, inclination and the like caused by overhigh stacked steps of the chip can be solved; in the packaging structure, back metal is arranged on the right side of the back of each chip and is electrically connected with the right side pin on the front of the chip, the back metal of each chip is electrically connected with the substrate window through the plastic packaging glue through hole, the power supply and the ground network of each chip are intensively processed, so that the chips can effectively dissipate heat, and compared with the traditional method of simply using wire bonding connection, the current carrying capacity of the chips can be effectively improved by utilizing the back metal and the plastic packaging glue through hole; the packaging structure can effectively solve the problem of impedance increase caused by long routing paths of the traditional packaging, and reduces the packaging size.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
FIG. 1 is a schematic diagram of a stacked package structure according to one embodiment of the present invention; and
fig. 2A to 2C are schematic diagrams illustrating a process of forming a stacked package structure according to an embodiment of the present invention.
Detailed Description
It should be noted that the components in the figures may be shown exaggerated for illustrative purposes and are not necessarily to scale.
In the present invention, the embodiments are merely intended to illustrate the scheme of the present invention, and should not be construed as limiting.
In the present invention, the adjectives "a" and "an" do not exclude a scenario of a plurality of elements, unless specifically indicated.
It should also be noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that the components or assemblies may be added as needed for a particular scenario under the teachings of the present invention.
It should also be noted herein that, within the scope of the present invention, the terms "identical", "equal" and the like do not mean that the two values are absolutely equal, but rather allow for some reasonable error, that is, the terms also encompass "substantially identical", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not explicitly or implicitly indicate that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as limiting or implying any relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and not for limiting the order of the steps, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
Fig. 1 shows a schematic diagram of a stacked package structure according to an embodiment of the present invention.
As shown in fig. 1, a stacked package structure includes a substrate 111, a first chip 112, a second chip 113, a third chip 114, a back metal 115, a conductive adhesive 116, a first molding layer 117, a first molding compound through hole 118, a second molding layer 119, a second molding compound through hole 120, a metal post 121, a third molding compound through hole 122, a third molding compound through hole 123, a circuit 124, and a wire bonding 125.
The right portion of the substrate 111 has a substrate window 126.
The right side of the back sides of the first, second and third chips 112, 113 and 114 are provided with a back metal 115, the front side having pins 130. The back metal 115 is divided into a plurality of metal regions according to the electrical properties of the right side pins of each chip front side, and the electrical properties of the metal regions are the same as those of the pins directly above the metal regions. The back metal is electrically connected with the pin on the right side of the front side of the chip.
The first chip 112 is attached to the left side portion of the substrate 111 with a conductive adhesive 116.
The first molding layer 117 is located on the right side of the first chip 112 and is equal in height to the first chip 112.
The first molding compound through hole 118 penetrates through the first molding compound 117 and is electrically connected with the substrate window 126 and the back metal of the second chip 113. The number of the first molding compound through holes 118 is the same as the number of the metal regions of the back metal of the second chip 113.
The second chip 113 is mounted on the first chip 112 in a staggered manner by the conductive adhesive 116. The back metal of the second chip 113 is electrically connected to the right pin of the first chip 112 and the first plastic package through hole 118 through the conductive adhesive 116. The back metal of the second chip 112 is located above the first molding compound through hole 118. The first plastic layer 117 provides support for the second chip 113.
The second molding layer 119 is located at the right side of the second chip 113 and is equal in height to the second chip 113.
The second molding compound through hole 120 penetrates through the first molding compound 117 and the second molding compound 119, and is electrically connected with the substrate window 126 and the back metal 115 of the third chip 114. The number of second molding compound through holes 120 is the same as the number of metal regions of the back side metal of the third chip 114.
The third chip 114 is mounted on the second chip 113 in a staggered manner by the conductive adhesive 116. The back metal 115 of the third chip 114 is electrically connected to the right pin of the second chip 113 and the second plastic package through hole 120 through the conductive adhesive 116. The back metal of the third chip 114 is located above the second molding compound through hole 120. The second plastic layer 119 provides support for the third chip 114.
The metal post 121 is disposed on the right-side pin of the third chip 114.
The third plastic layer 122 is located on the right side of the third chip 114 and wraps around the metal posts 121. The top of the third plastic layer 122 is flush with the top of the metal posts 121.
The third molding compound through hole 123 penetrates the first molding compound 117 to the third molding compound 122. The number of the third molding compound through holes 123 is the same as the number of the right side pins of the third chip 114.
The circuit 124 is electrically connected to the metal 121 pillars and the third molding compound through hole 123, and is located on the surface of the third molding compound 122.
The wire bonds 125 electrically interconnect the substrate 111, the first chip 112, the second chip 113, and the third chip 114 layer by layer. The wire bonds 125 electrically interconnect the left side pins of the first chip 111, the second chip 112, and the third chip 113, and electrically interconnect the left side pins of the first chip 111 with the substrate 111.
In other embodiments of the present invention, when the number of the second chips and the second molding layers is plural, the second molding compound through holes have plural heights. The plurality of second chips are arranged on the first chip by using conductive adhesive through the dislocation layer. The second plastic sealing layers are arranged on the right sides of the second chips, and each second plastic sealing layer is equal to the corresponding second chip in height. The second plastic package through holes with various heights are electrically connected with the substrate window and the back metal of the third chip or the back metal of the second chip.
The back metal 115 and the right side pins of the first chip 112, the second chip 113 and the third chip 114, the conductive adhesive 116, the first plastic package through hole 118, the second plastic package through hole 120, the metal column 121, the third plastic package through hole 123, the circuit 124 and the substrate window 126 form an electric interconnection path, and the power supply and the ground network of the first chip 112, the second chip 113 and the third chip 114 are intensively processed, so that the chips can radiate heat effectively; compared with the traditional method of simply using wire bonding, the method has the advantages that the current carrying capacity of the chip can be effectively improved by utilizing the metal on the back and the plastic package through hole; the electric interconnection path effectively solves the problem of impedance increase caused by long routing paths of the traditional package, and reduces the package size. The chip on the upper layer is supported by the plastic sealing layer on the right side of the chip only through wire bonding electric interconnection, so that the problem of unstable stacking structure caused by overhigh stacking of the chips can be solved.
Fig. 2A to 2C are schematic diagrams illustrating a process of forming a stacked package structure according to an embodiment of the present invention.
In step 1, a back metal 210 is disposed on the back side of each chip, and the back metal 210 is divided into a plurality of regions according to different electrical properties of the pins on the right side of the front side of the chip, and the electrical properties of the regions are the same as those of the pins above the regions. The back side metal 210 is electrically connected to the right side die on the front side of the chip.
In step 2, as shown in fig. 2A, a first chip 212 is disposed on the left side of the substrate 211, a first molding layer 213 is disposed on the right side of the first chip 212, and then a first molding through hole 214 penetrating the first molding layer 213 is fabricated.
First, a first chip 212 is mounted on the left side of a substrate 211 through conductive adhesive 215, then a first plastic sealing layer 213 with the same height as the first chip 212 is arranged on the right side of the first chip 212, holes are drilled on the first plastic sealing layer 213, metal is filled to ensure the conductivity of the first plastic sealing layer 213, a first plastic sealing adhesive through hole 214 is formed, and pins on the left side of the front surface of the first chip 212 are connected with the substrate 211 through a wire bonding 216. The right portion of the substrate 211 has a substrate window 217. The first molding compound through hole 214 is electrically connected to the substrate window 217.
Step 3, as shown in fig. 2B, the second chip 218 is arranged on the first chip 212 in a staggered manner, the second molding layer 219 is arranged on the right side of the second chip 218, and then the second molding through holes 220 penetrating through the first molding layer 213 and the second molding layer 219 are fabricated.
Firstly, the second chip 218 is mounted on the first chip 212 in a staggered manner through the conductive adhesive 215, so that the metal on the back surface of the second chip 218 is positioned above the first plastic package adhesive through hole 214 and is electrically connected with the first plastic package adhesive through hole 214 through the conductive adhesive 215, and meanwhile, the right side pin on the front surface of the first chip 212 is electrically connected with the metal 210 on the back surface of the second chip 218 through the conductive adhesive 215; then, a second plastic sealing layer 219 with the same height as the second chip 218 is arranged on the right side of the second chip 218, holes are drilled on the second plastic sealing layer 219, the first plastic sealing layer 213 is drilled through, metal is filled to ensure the conductivity of the first plastic sealing layer 213, a second plastic sealing glue through hole 220 is formed, and the second plastic sealing glue through hole 220 is electrically connected with a substrate window 217; the left pin on the front side of the second chip 218 is connected to the left pin on the front side of the first chip 212 by wire bonds 216. The first plastic layer 213 provides support for the second chip 212.
Step 4, as shown in fig. 2C, a third chip 221 is arranged on the second chip 218 in a staggered manner, a copper pillar 222 is arranged on a right side pin on the front side of the third chip 221, a third molding layer 223 is arranged on the right side of the third chip 221, the third molding layer 223 wraps the copper pillar 222, then a third molding through hole 224 penetrating through the first molding layer 213 to the third molding layer 223 is manufactured, and finally a circuit 225 connecting the copper pillar 222 and the third molding through hole 224 is arranged.
Firstly, the third chip 221 is mounted on the second chip 218 in a staggered manner through the conductive adhesive 215, so that the back metal of the third chip 221 is ensured to be positioned above the second plastic package adhesive through hole 220 and is electrically connected with the second plastic package adhesive through hole 220 through the conductive adhesive 215, and meanwhile, the right side pin on the front surface of the second chip 218 is electrically connected with the back metal 210 of the third chip 221 through the conductive adhesive 216; arranging copper columns 222 on the right side pins of the front side of the third chip 221, and then arranging a third plastic layer 223 on the right side of the third chip 221, wherein the third plastic layer 223 wraps the copper columns 222, and the tops of the third plastic layer 223 are level with the tops of the copper columns 222; drilling holes in the third plastic sealing layer 223, drilling through the first plastic sealing layer 213 to the third plastic sealing layer 223, and filling metal to ensure the conductivity of the third plastic sealing layer 223 to form a third plastic sealing glue through hole 224; etching a circuit on the surface of the third plastic sealing layer 223, and filling metal to form a circuit 225, wherein the circuit 225 connects the copper column 222 and the third plastic sealing layer through hole 224; the left pin on the front side of the third chip 221 is connected to the left pin on the front side of the second chip 218 through the wire bond 216. The second plastic layer 219 provides support for the third chip 221.
In other embodiments of the present invention, chips may be stacked first, a plastic layer may be disposed, a plastic through hole may be made, and finally, the left pins on the front sides of the first chip 212, the second chip 218 and the third chip 221 may be connected layer by layer through wire bonding.
In other embodiments of the present invention, step 3 may be repeated, disposing a plurality of second chips, a plurality of second molding layers, and a plurality of second molding compound vias.
While certain embodiments of the present invention have been described herein, those skilled in the art will appreciate that these embodiments are shown by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the present teachings without departing from the scope of the invention. The appended claims are intended to define the scope of the invention and to cover such methods and structures within the scope of these claims themselves and their equivalents.

Claims (10)

1. A stacked package structure, comprising:
a substrate having a substrate window in a right portion thereof;
a first chip mounted on a left side portion of the substrate, wherein a right side of a back surface of the first chip has a back metal;
a first plastic layer located on the right side of the first chip;
the first plastic packaging glue through hole is electrically connected with the substrate window and the back metal of the second chip;
the second chip is mounted on the first chip in a staggered manner, wherein the right side of the back of the second chip is provided with back metal;
a second molding layer located on the right side of the second chip;
the second plastic packaging glue through hole is electrically connected with the substrate window and the back metal of the third chip;
the third chip is mounted on the second chip in a staggered manner, wherein the right side of the back of the third chip is provided with back metal;
a metal pillar disposed on a right-side pin of the front surface of the third chip;
the third plastic layer is positioned on the right side of the third chip and wraps the metal column;
the third plastic sealing layer through hole penetrates through the first plastic sealing layer to the third plastic sealing layer;
the circuit is electrically connected with the metal column and the third plastic packaging glue through hole;
and a conductive lead electrically interconnecting the substrate, the first chip, the second chip, and the third chip.
2. The stacked package structure of claim 1, wherein the back side metal is divided into a plurality of metal regions according to an electrical property of a right side pin of the front side of each chip, and the electrical property of the metal regions is the same as an electrical property of a pin directly above the metal regions.
3. The stacked package structure of claim 2, wherein the number of first molding compound vias is the same as the number of metal areas of the backside metal of the second chip;
the number of the second plastic package glue through holes is the same as the number of the metal areas of the back metal of the third chip;
the number of the second plastic package through holes is the same as that of the right side pins of the third chip.
4. The stacked package structure of claim 1, wherein the first chip is attached to a left portion of the substrate by a conductive adhesive;
the second chip is mounted on the first chip in a staggered manner through conductive adhesive, wherein the back metal of the second chip is electrically connected with the right side pin of the first chip and the first plastic package adhesive through hole through conductive adhesive;
the third chip is mounted on the second chip in a staggered manner through conductive adhesive, wherein the back metal of the third chip is electrically connected with the right side pin of the second chip and the second plastic package adhesive through hole through the conductive adhesive;
the first plastic sealing layer is equal to the first chip in height;
the second plastic sealing layer is equal to the second chip in height.
5. The stacked package structure of claim 1, wherein the conductive leads electrically interconnect left side pins of the first, second, and third chips and electrically interconnect left side pins of the first chip with the substrate.
6. The method for forming the stack type packaging structure is characterized by comprising the following steps:
arranging back metal on the back of the first chip, the second chip and the third chip;
a first chip is arranged on the left side of the substrate, a first plastic sealing layer is arranged on the right side of the first chip, and then a first plastic sealing through hole penetrating through the first plastic sealing layer is manufactured, wherein the right side of the substrate is provided with a substrate window;
a second chip is arranged on the first chip in a staggered mode, a second plastic sealing layer is arranged on the right side of the second chip, and then a second plastic sealing through hole penetrating through the first plastic sealing layer and the second plastic sealing layer is manufactured;
and a third chip is arranged on the second chip in a staggered manner, a copper column is arranged on a right-side pin on the front side of the third chip, a third plastic sealing layer is arranged on the right side of the third chip, the third plastic sealing layer wraps the copper column, then a third plastic sealing glue through hole penetrating through the first plastic sealing layer to the third plastic sealing layer is manufactured, and finally a circuit for connecting the copper column and the third plastic sealing glue through hole is arranged.
7. The method of forming a stacked package structure of claim 6, wherein the backside metal is divided into a plurality of metal regions according to different electrical properties of a right side pin of the front side of each chip, and the electrical properties of the metal regions are identical to those of pins directly above the metal regions.
8. The method of forming a stacked package structure according to claim 6, wherein the first chip is first mounted on the substrate by a conductive adhesive, then a first molding layer having the same height as the first chip is disposed on the right side of the first chip, holes are drilled in the first molding layer, and metal is filled into the holes to form first molding adhesive, and pins on the left side of the front side of the first chip are connected to the substrate by wire bonding.
9. The method of forming a stacked package structure according to claim 6, wherein the second chip is mounted on the first chip by conductive adhesive, so as to ensure that a back metal of the second chip is located above the first molding compound through hole and is electrically connected with the first molding compound through hole by the conductive adhesive, and meanwhile, a right pin on the front surface of the first chip is electrically connected with a back metal of the second chip by the conductive adhesive;
then, arranging a second plastic sealing layer with the same height as the second chip on the right side of the second chip, drilling holes on the second plastic sealing layer, drilling through the first plastic sealing layer, filling metal to ensure the conductivity of the first plastic sealing layer, and forming a second plastic sealing glue through hole, wherein the second plastic sealing glue through hole is electrically connected with the substrate window;
and connecting the left pin on the front surface of the second chip with the left pin on the front surface of the first chip through wire bonding.
10. The method for forming a stacked package structure according to claim 6, wherein first, the third chip is mounted on the second chip in a staggered manner by using the conductive adhesive, so that the back metal of the third chip is located above the second plastic package adhesive through hole and is electrically connected with the second plastic package adhesive through hole through the conductive adhesive, and meanwhile, the right pin on the front surface of the second chip is electrically connected with the back metal of the third chip through the conductive adhesive;
arranging copper columns on the right side pins of the front side of the third chip, and then arranging a third plastic layer on the right side of the third chip, wherein the third plastic layer wraps the copper columns, and the tops of the third plastic layer are flush with the tops of the copper columns;
drilling holes on the third plastic sealing layer, drilling through the first plastic sealing layer and the second plastic sealing layer, filling metal to ensure the conductivity of the first plastic sealing layer and the second plastic sealing layer, and forming a third plastic sealing glue through hole which is electrically connected with the substrate windowing;
etching a circuit on the surface of the third plastic sealing layer, and filling metal to form a circuit, wherein the circuit is connected with the copper column and the third plastic sealing layer through hole;
and connecting the left pin on the front surface of the third chip with the left pin on the front surface of the second chip through wire bonding.
CN202310089871.4A 2023-02-09 2023-02-09 Stack type packaging structure and forming method thereof Pending CN116110860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310089871.4A CN116110860A (en) 2023-02-09 2023-02-09 Stack type packaging structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310089871.4A CN116110860A (en) 2023-02-09 2023-02-09 Stack type packaging structure and forming method thereof

Publications (1)

Publication Number Publication Date
CN116110860A true CN116110860A (en) 2023-05-12

Family

ID=86265113

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310089871.4A Pending CN116110860A (en) 2023-02-09 2023-02-09 Stack type packaging structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN116110860A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117391038A (en) * 2023-10-23 2024-01-12 北京市合芯数字科技有限公司 Metal stack space information dividing method of chip layout and chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117391038A (en) * 2023-10-23 2024-01-12 北京市合芯数字科技有限公司 Metal stack space information dividing method of chip layout and chip
CN117391038B (en) * 2023-10-23 2024-05-14 北京市合芯数字科技有限公司 Metal stack space information dividing method of chip layout and chip

Similar Documents

Publication Publication Date Title
US9640518B2 (en) Semiconductor package with package-on-package stacking capability and method of manufacturing the same
KR100363004B1 (en) Prefabricated Semiconductor Chip Carriers
CN101877348B (en) System and method for embedded chip package with chips stacked in an interconnecting laminate
US20180114781A1 (en) Package structure and manufacturing method thereof
KR100885924B1 (en) A semiconductor package having a buried conductive post in sealing resin and manufacturing method thereof
US6951773B2 (en) Chip packaging structure and manufacturing process thereof
US6417027B1 (en) High density stackable and flexible substrate-based devices and systems and methods of fabricating
CN1266764C (en) Semiconductor device and its producing method
US6867486B2 (en) Stack chip module with electrical connection and adhesion of chips through a bump for improved heat release capacity
CN100524717C (en) Chip buried-in modularize structure
US20080290496A1 (en) Wafer level system in package and fabrication method thereof
CN209880656U (en) LED array packaging structure
US7981796B2 (en) Methods for forming packaged products
KR20130038404A (en) Stacked die bga or lga component assembly
CN1166057A (en) Bottom lead semiconductor chip stack package
US10332854B2 (en) Anchoring structure of fine pitch bva
KR100744146B1 (en) Semiconductor package for connecting wiring substrate and chip using flexible connection plate
JP5394603B2 (en) A multi-package module comprising a stacked package comprising a die and a mold body arranged asymmetrically.
JP2004505451A (en) Method for distributed shielding and decoupling of electronic devices with steric interconnections, device thus obtained and method for manufacturing the device
CN115547961A (en) High-density integrated three-dimensional chip packaging structure and manufacturing method thereof
CN116110860A (en) Stack type packaging structure and forming method thereof
TW201409653A (en) Wiring board with embedded device and electromagnetic shielding
US7310239B1 (en) IC packaging interposer having controlled impedance or optical interconnections and an integral heat spreader
JP3731420B2 (en) Manufacturing method of semiconductor device
US7763983B2 (en) Stackable microelectronic device carriers, stacked device carriers and methods of making the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination