CN2727796Y - Low-temperature polysilicon thin-film transistor base plate - Google Patents
Low-temperature polysilicon thin-film transistor base plate Download PDFInfo
- Publication number
- CN2727796Y CN2727796Y CN 200420072104 CN200420072104U CN2727796Y CN 2727796 Y CN2727796 Y CN 2727796Y CN 200420072104 CN200420072104 CN 200420072104 CN 200420072104 U CN200420072104 U CN 200420072104U CN 2727796 Y CN2727796 Y CN 2727796Y
- Authority
- CN
- China
- Prior art keywords
- film transistor
- low
- temperature polysilicon
- polysilicon film
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The utility model relates to a low-temperature polysilicon thin-film transistor base plate which comprises a base plate and a polysilicon thin layer formed on the base plate, and a drive circuit area and a display panel area are formed on the polysilicon thin film. Wherein, the drive circuit area can form a plurality of drive circuits, the display panel area can form a plurality of pixel units, and the drive circuit area and the display panel area are separately arranged.
Description
[technical field]
The utility model is about a kind of thin film transistor base plate, particularly a kind of low-temperature polysilicon film transistor (Low Temperature Poly-Silicon Thin FilmTransistor, LTPS TFT) substrate.
[background technology]
Flat-panel screens replaces cathode-ray tube (CRT) gradually because have frivolous advantage, becomes the main flow of display.But flourish along with Information technology, and the demand of high resolving power and information demonstration high capacity more, the tradition amorphous silicon film transistor drives the usefulness of LCD (a-si TFT LCD) and has not applied demand, so beginning to develop, industry has the more low-temperature polysilicon film transistor technology of excellent properties, it is advantageous that and driving circuit directly can be produced on (System On Glass on the glass substrate, SOG), with the cost of effective reduction integrated drive electronics, in response to the demand in flat-panel screens market.
General low-temperature polysilicon film transistor technology is to utilize thin film deposition (Thin FilmDeposition), yellow light lithography (UV Lithography), etching (Etching) to make thin film transistor (TFT) and image electrode.But in its manufacturing process, the laser annealing processing procedure is a gordian technique wherein.The success or not of this fabrication steps, very big to the properties influence of thin film transistor (TFT).
Please refer to Fig. 1, be a kind of structural representation of prior art low-temperature polysilicon film transistor substrate 200, this low-temperature polysilicon film transistor substrate 200 comprises insulated substrate 220, drive circuit area 210, a plurality of driving circuit 211, display panel areas 230 and a plurality of pixel cell 222.Wherein, drive circuit area 210 links together with display panel areas 230,222 of a plurality of driving circuits 211 and a plurality of pixel cells thereon, and a plurality of driving circuit 211 is followed a plurality of pixel cells 222 and is provided with.Owing to carry out the quasi-molecule laser annealing processing procedure on the insulated substrate 220 and non-once is finished, but repeatedly scanning is finished one by one, thereby the polycrystalline SiTFT characteristic of making and inhomogeneous, simultaneously, the requirement (± 10～100mV) of 210 pairs of tft characteristics uniformity coefficient of drive circuit area, (± 1～2V) is much higher than the requirement of display panel areas 230 internal membrane transistor switch assemblies, and present stage low-temperature polysilicon film transistor substrate 200 situation of generally arranging, driving circuit 211 is followed a plurality of pixel cells 222 and is distributed on the whole base plate, this is very high for the inhomogeneity difficulty of processing procedure, when the uniformity coefficient of quasi-molecule laser annealing processing procedure in somewhere on the insulated substrate 220 is not high, if certain driving circuit 211 bad waste product that cause only, the display panel areas 230 that then is attached thereto no matter also can scrap by the good and the bad, cause yield low, increase cost.
[utility model content]
In order to overcome the problem that low-temperature polysilicon film transistor substrate yield is low in the prior art, production cost is high, the utility model provides a kind of yield higher, lower-cost low-temperature polysilicon film transistor substrate.
The low-temperature polysilicon film transistor substrate that the utility model provides comprises that an insulated substrate and is formed at the polysilicon membrane on this substrate, have two zones of drive circuit area and display panel areas on this polysilicon membrane, wherein, this drive circuit area forms a plurality of driving circuits, this display panel areas forms a plurality of pixel cells, and this drive circuit area and this display panel areas separate setting.
Compared to existing technology, the beneficial effects of the utility model are: because driving circuit is in the requirement of tft characteristics uniformity coefficient, much higher than viewing area internal membrane transistor switch assembly, thereby the drive circuit area of low-temperature polysilicon film transistor substrate of the present utility model and display panel areas are made in zones of different, driving circuit is concentrated in a certain zone, can reduce the process variation factor to inhomogeneity influence degree, to promote low-temperature polysilicon film transistor substrate panel and driving circuit integral manufacturing yield, reduce production cost.The later use flexible circuit board combines viewing area film transistor matrix pin with conductive material with the driving circuit pin, finish panel and make.
[description of drawings]
Fig. 1 is a kind of structural representation of low-temperature polysilicon film transistor substrate of prior art.
Fig. 2 is a low-temperature polysilicon film transistor board structure synoptic diagram of the present utility model.
Fig. 3 is the making process flow diagram of low-temperature polysilicon film transistor substrate of the present utility model
Fig. 4 is the follow-up connection diagram of low-temperature polysilicon film transistor substrate of the present utility model.
[embodiment]
Seeing also Fig. 2, is the structural representation of the utility model low-temperature polysilicon film transistor substrate.This low-temperature polysilicon film transistor substrate 300 comprises an insulated substrate 320, one drive circuit zone 310, a plurality of driving circuit 311, display panel areas 330 and a plurality of pixel cell 322.Wherein, drive circuit area 310 and display panel areas 330 are distributed in the zones of different on the insulated substrate 320, and a plurality of driving circuits 311 are arranged in the drive circuit area 310, a plurality of pixel cells 322 are arranged in the display panel areas 330, and this insulated substrate 320 can be glass substrate or quartz base plate.
Seeing also Fig. 3, is the making process flow diagram of the utility model low-temperature polysilicon film transistor substrate 300.The making of this low-temperature polysilicon film transistor substrate 300 may further comprise the steps: provide an insulated substrate 320 (step 10), surface at this insulated substrate 320, carry out one first plasma reinforced chemical vapour deposition processing procedure (step 20), wherein this insulated substrate 320 can be glass substrate or quartz base plate, make the surface of this insulated substrate 320 form an amorphous silicon layer, carry out an excimer laser annealing process again so that this amorphous silicon layer again crystallization form polysilicon membrane (step 30), the surface of this polysilicon membrane includes the one source pole zone of this low-temperature polysilicon film transistor, one drain region and a channel region; Carry out one second plasma reinforced chemical vapour deposition processing procedure (step 40), on this channel region, to form a silicon oxide layer based on tetraethoxysilane in regular turn.Simultaneously drive circuit area 310 and display panel areas 330 are separated on insulated substrate 320, wherein drive circuit area 310 comprises a plurality of driving circuits 311, display panel areas 330 comprises a plurality of pixel cells 322, driving circuit 311 is concentrated in a certain zone, can reduce the process variation factor to inhomogeneity influence degree, to promote low-temperature polysilicon film transistor substrate 300 and driving circuit 311 integral manufacturing yields, reduce the cost of processing procedure.
Seeing also Fig. 4, is the follow-up connection diagram of the utility model low-temperature polysilicon film transistor substrate 300.The pin of driving circuit 311 utilizes flexible circuit board 430 to combine with conductive material with the film transistor matrix pin of pixel cell 322, finishes panel and makes.
Claims (4)
1. low-temperature polysilicon film transistor substrate, it comprises that an insulated substrate, is formed at drive circuit area and the display panel areas that forms on polysilicon membrane on this insulated substrate and this polysilicon membrane, this drive circuit area forms a plurality of driving circuits, this display panel areas forms a plurality of pixel cells, it is characterized in that: this drive circuit area and this display panel areas separate setting.
2. low-temperature polysilicon film transistor substrate according to claim 1 is characterized in that: this insulated substrate is a glass substrate.
3. low-temperature polysilicon film transistor substrate according to claim 1 is characterized in that: this insulated substrate is a quartz base plate.
4. low-temperature polysilicon film transistor substrate according to claim 1 is characterized in that: the surface of this polysilicon membrane includes one source pole zone, a drain region and a channel region of this low-temperature polysilicon film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420072104 CN2727796Y (en) | 2004-07-24 | 2004-07-24 | Low-temperature polysilicon thin-film transistor base plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420072104 CN2727796Y (en) | 2004-07-24 | 2004-07-24 | Low-temperature polysilicon thin-film transistor base plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2727796Y true CN2727796Y (en) | 2005-09-21 |
Family
ID=35043809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420072104 Expired - Lifetime CN2727796Y (en) | 2004-07-24 | 2004-07-24 | Low-temperature polysilicon thin-film transistor base plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2727796Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100352040C (en) * | 2004-04-17 | 2007-11-28 | 鸿富锦精密工业（深圳）有限公司 | Low temperature polysilicon thin film electric crystal base board and its producing method |
-
2004
- 2004-07-24 CN CN 200420072104 patent/CN2727796Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100352040C (en) * | 2004-04-17 | 2007-11-28 | 鸿富锦精密工业（深圳）有限公司 | Low temperature polysilicon thin film electric crystal base board and its producing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2717237B2 (en) | Insulated gate semiconductor device and method of manufacturing the same | |
| TWI531847B (en) | Liquid crystal display device | |
| CN102983155B (en) | Flexible display apparatus and preparation method thereof | |
| CN203026507U (en) | Flexible display device | |
| CN100399179C (en) | Pixel structure of a liquid crystal panel, method of fabricating the same and driving method thereof | |
| US20170317107A1 (en) | Novel silicon-based backplane structures and methods for display applications | |
| CN101414564B (en) | Method for manufacturing low-temperature polycrystalline silicon film transistor | |
| CN100437978C (en) | Display panel and method of manufacturing thereof | |
| CN2727796Y (en) | Low-temperature polysilicon thin-film transistor base plate | |
| CN100352040C (en) | Low temperature polysilicon thin film electric crystal base board and its producing method | |
| US6475835B1 (en) | Method for forming thin film transistor | |
| US20050230753A1 (en) | LTPS TFT substrate and manufacturing process thereof | |
| CN2727797Y (en) | Low-temperature polysilicon display device | |
| CN100414354C (en) | Low temperature polysilicon display unit and method for fabricating the same | |
| CN106711157B (en) | The production method of LTPS array substrate | |
| CN110838467A (en) | Manufacturing method of low-temperature polycrystalline silicon substrate and low-temperature polycrystalline silicon substrate | |
| US20180090625A1 (en) | Low temperature poly-silicon tft substrate and manufacturing method thereof | |
| KR100556347B1 (en) | Liquid Crystal Display device and method for manufacturing the same | |
| CN108231693B (en) | Array substrate, manufacturing method thereof and display device | |
| JP2003297746A (en) | Tft forming method | |
| US20060238470A1 (en) | LTPS display panel and manufacturing process thereof | |
| CN202905722U (en) | TFT with light doped drain | |
| JP3300335B2 (en) | display | |
| CN116367680A (en) | Display device, display panel and manufacturing method of active layer of display panel | |
| CN113964086A (en) | Preparation method of display panel based on POA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20071128 |
|
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20071128 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |