CN116367680A

CN116367680A - Display device, display panel and manufacturing method of active layer of display panel

Info

Publication number: CN116367680A
Application number: CN202310377397.5A
Authority: CN
Inventors: 田雪雁; 刘政; 李然
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2023-04-10
Filing date: 2023-04-10
Publication date: 2023-06-30

Abstract

The present disclosure discloses a display device, a display panel, and a method of manufacturing an active layer of the display panel, wherein the method of manufacturing includes: providing a substrate, wherein the substrate comprises a display area and a non-display area surrounding the display area, and the non-display area comprises an array grid driving area; forming a second active layer in the array gate driving region by using a solid state laser annealing method or a second excimer laser annealing method, and forming a first active layer in the display region by using at least one of the solid state laser annealing method, the first excimer laser annealing method, and an oxide patterning method; wherein the scanning pitch of the first excimer laser annealing method is smaller than the scanning pitch of the second excimer laser annealing method. The manufacturing method can reduce the manufacturing cost of the display panel.

Description

Display device, display panel and manufacturing method of active layer of display panel

Technical Field

The disclosure relates to the field of display technologies, and in particular, to a display device, a display panel, and a method for manufacturing an active layer of the display panel.

Background

Active Matrix (Active Matrix) displays, i.e., thin film transistor displays, are now in wide use. In the back plane technology of active matrix displays, the technology of manufacturing the active layer of the thin film transistor is one of the key points. Taking AMOLED (Active Matrix Organic Light-patterning Diode) as an example, it has advantages of high image quality, short response time of moving image, low power consumption, wide viewing angle, ultra-light and ultra-thin, etc., and becomes one of the preferred choices of future display technology, in the back plate technology of AMOLED, excimer laser annealing (Excimer Laser Annealing, ELA) is often used to manufacture polysilicon thin film as active layer, but ELA technology is a relatively complex annealing method, and has problems of high cost, including equipment cost, equipment maintenance cost such as cost of replacing parts, etc.

Disclosure of Invention

In view of the above, the present disclosure provides a display device, a display panel, and a method of manufacturing an active layer of a display panel, which can reduce manufacturing costs of the display panel.

In a first aspect, the present disclosure provides, by way of an embodiment, the following technical solutions:

a method of fabricating an active layer of a display panel, comprising:

providing a substrate, wherein the substrate comprises a display area and a non-display area surrounding the display area, and the non-display area comprises an array grid driving area;

forming a second active layer in the array gate driving region by using a solid state laser annealing method or a second excimer laser annealing method, and forming a first active layer in the display region by using at least one of the solid state laser annealing method, the first excimer laser annealing method, and an oxide patterning method;

wherein the scanning pitch of the first excimer laser annealing method is smaller than the scanning pitch of the second excimer laser annealing method.

Optionally, the forming a second active layer in the array gate driving region by using a solid state laser annealing method or a second excimer laser annealing method includes:

and forming a low-temperature polysilicon layer serving as the second active layer in the array gate driving region by adopting the solid-state laser annealing method.

Optionally, the forming a first active layer in the display area by at least one of the solid-state laser annealing method, the first excimer laser annealing method, and the oxide patterning method includes:

and forming an oxide semiconductor layer as the first active layer in the display region by using the oxide patterning method.

and forming a composite layer including low-temperature polysilicon and an oxide semiconductor as the first active layer in the display region using the solid-state laser annealing method and the oxide patterning method.

and forming a composite layer including low-temperature polysilicon and an oxide semiconductor as the first active layer in the display region using the first excimer laser annealing method and the oxide patterning method.

and forming a low-temperature polysilicon layer as the first active layer in the display area by adopting the first excimer laser annealing method.

and forming a low-temperature polysilicon layer serving as the second active layer in the array gate driving region by adopting the second excimer laser annealing method.

Optionally, the scanning interval of the first excimer laser annealing method ranges from 5 μm to 18 μm, and the scanning interval of the second excimer laser annealing method ranges from 22 μm to 35 μm;

the laser frequency of the first excimer laser annealing method and the second excimer laser annealing method ranges from 400Hz to 700Hz.

Optionally, the scanning interval value range of the solid-state laser annealing method is 2-8 μm, and the laser frequency value range is 8000-12000 Hz.

In a second aspect, based on the same inventive concept, the present disclosure provides, through an embodiment, the following technical solutions:

a display panel comprising a substrate and an active layer disposed on the substrate, the active layer being fabricated using the fabrication method as provided in any one of the embodiments of the first aspect.

In a third aspect, based on the same inventive concept, the present disclosure provides, by an embodiment, the following technical solutions:

a display device comprising the display panel provided by the embodiment of the second aspect.

Through one or more technical schemes of the present disclosure, the present disclosure has the following beneficial effects or advantages:

the present disclosure provides a method for manufacturing an active layer of a display panel, by distinguishing a display area and an array gate driving area, manufacturing a first active layer and a second active layer by different methods, particularly, manufacturing a second active layer by a solid-state laser annealing method or a second excimer laser annealing method with a larger scanning interval in the array gate driving area with relatively lower requirement for the uniformity of crystal grains of the active layer, thereby reducing the cost; in the display area with relatively high requirement on the uniformity of the crystal grains of the active layer, one or a combination of a solid-state laser annealing method, an oxide patterning method and a first excimer laser annealing method with smaller scanning interval is adopted to manufacture the first active layer so as to ensure the electrical performance of the active layer of the thin film transistor in the display area.

The foregoing description is merely an overview of the technical solutions of the present disclosure, and may be implemented according to the content of the specification in order to make the technical means of the present disclosure more clearly understood, and in order to make the above and other objects, features and advantages of the present disclosure more clearly understood, the following specific embodiments of the present disclosure are specifically described.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to designate like parts throughout the figures.

In the drawings:

fig. 1 is a flow chart illustrating a method of manufacturing an active layer of a display panel according to an embodiment of the present disclosure;

FIG. 2 illustrates a schematic diagram of a partition layout on a substrate according to an embodiment of the present disclosure;

FIG. 3 shows a schematic diagram of a display device according to an embodiment of the present disclosure;

reference numerals illustrate:

10. a display area; 21. a flexible circuit board pad region; 22. a display driving region; 231. a first sub-GOA region; 232. a second sub-GOA region; 24. and a frame area.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.

The active layer of the thin film transistor in the display panel is commonly used at present as polysilicon and oxide semiconductor such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO). Taking an AMOLED display panel as an example, a Low Temperature Polysilicon (LTPS) film may be prepared as an active layer of a thin film transistor (Thin Film Transistor, TFT). Methods of fabricating the low temperature polysilicon active layer include Excimer Laser Annealing (ELA), solid Phase Crystallization (SPC), metal Induced Crystallization (MIC), and the like. Among them, the fabrication of a polysilicon thin film of a transistor active layer in a back plate by an ELA method is a method widely used at present. ELA is a relatively complex annealing process that is costly in terms of equipment, equipment maintenance and replacement of parts and consumables.

Control of grain size and grain uniformity in polysilicon thin film fabrication has been a focus of research in this field of technology. Because the number and distribution of polysilicon grains covered by the channel region of the low-temperature polysilicon thin film transistor, i.e. the uniformity of the grains, directly affect the electrical performance of the low-temperature polysilicon thin film transistor, and relate to mobility, uniformity of threshold voltage, etc. Therefore, how to control the transformation of amorphous silicon into ideal polysilicon, i.e. the polysilicon thin film has larger grain size and even distribution, is an important research direction.

On the other hand, the active layer of the thin film transistor is prepared by adopting low-temperature polycrystalline oxide LTPO (Low Temperature Poly-crystalline Oxide), which is a combination of LTPS and IGZO schemes in the OLED at present, the lowest refresh rate of the LTPO screen technology can be 1Hz, lower refresh rate can bring lower power consumption, and a large amount of electric quantity is saved by reducing the refresh rate. However, the current manufacturing process of LTPO screen is very costly, so it is necessary to reduce the process cost of each pass, and the cost reduction of the active layer is one of the important research objects.

Studies have shown that currently, when a polysilicon active layer (active) is involved, both the AA region and the GOA region are fabricated using an ELA excimer laser annealing process. Such manufacturing costs are high, and the low gray-scale image quality is poor, and vertical Mura defects (uneven brightness or color display in the same gray-scale or monochrome picture) caused by ELA are difficult to overcome even after correction (Demura). In addition to the combination of LTPS and IGZO protocols: LTPO technology gradually becomes the main stream of the current OLED screen, the technology is based on the basis of 11-12 Mask of LTPS, the process flow is increased to 14-15 MASK, and the whole manufacturing flow has high cost; if the BSM (Bottom Shield Metal, bottom shielding metal) process is adopted, the cost is higher than 15. In order to solve the problem of poor quality of low gray level images, the scanning Pitch (Pitch value) of the ELA process is further reduced, which further aggravates the problems of high cost and low productivity.

In order to effectively reduce the manufacturing cost of the display panel, referring to fig. 1 in the first aspect, in an alternative embodiment, a method for manufacturing an active layer of the display panel is provided, including steps S101 to S103, and the overall concept is as follows:

s101: a substrate is provided, the substrate including a display region and a non-display region surrounding the display region, the non-display region including an array gate driving region.

The substrate may be a TFT substrate or a substrate for manufacturing a display panel, and a transparent glass substrate, a silicon substrate, or the like may be used. The display Area and the non-display Area on the substrate are areas divided based on the layout (layout) of the display panel, wherein the display Area may be referred to as an AA Area (Active Area) or a pixel circuit Area, and the non-display Area is an Area other than the display Area and is disposed around or surrounds the display Area. Fig. 2 shows an example of division of the display region 10 and the non-display region 10 on the substrate in the embodiment of the present disclosure, and the non-display region 10 specifically includes a flexible wiring board Pad region 21 (FPC Pad), a display driving region 22 (IC), an array gate driving region (Gate Driven on Array, GOA, also referred to as a scan driving circuit region), and a frame region 24 (Seal). The array gate driving region includes a first sub-GOA region 231 and a second sub-GOA region 232, and the first sub-GOA region 231 and the second sub-GOA region 232 are respectively located at two sides of the display region 10.

S102: the second active layer is formed in the array gate driving region using a solid state laser annealing method or a second excimer laser annealing method, and the first active layer is formed in the display region 10 using at least one of a solid state laser annealing method, a first excimer laser annealing method, and an oxide patterning method.

The excimer laser annealing method adopts a gaseous laser, emits excimer laser as a heat source, and generates laser beams with uniformly distributed energy after passing through a transmission system and is projected on a glass substrate of an amorphous silicon structure. The polysilicon grains are shown to be smooth in surface under a scanning electron microscope, the shapes of the polysilicon grains are regular quadrangles, and Mura defects are not obvious. In the present disclosure, the scanning pitch of the first excimer laser annealing method is smaller than the scanning pitch of the second excimer laser annealing method. The smaller the scanning interval is, the higher the process precision of excimer laser annealing is, the uniformity of crystal grains of the formed polycrystalline silicon film is better, meanwhile, the elimination or alleviation of Mura defects is facilitated, and the corresponding process cost is higher.

Solid state laser annealing (Solid laser annealing, SLA), known as ultraviolet solid state laser annealing (UVSLA), converts amorphous silicon into polysilicon using a solid state laser, the polysilicon grains show a polygonal shape under a scanning electron microscope, the alignment is less regular than ELA, and relatively obvious Mura defects are observed, but with relatively low process cost.

The oxide patterning method is to deposit an oxide material on a substrate by a semiconductor process, and then obtain an oxide semiconductor active layer through the process flows of coating photoresist, developing, etching, cleaning and the like, wherein the oxide semiconductor can be IGZO or IGZO.

The idea of reducing the cost is to manufacture different areas of the display panel by adopting different technologies, specifically, in an array gate driving area (GOA) with relatively low requirement on the uniformity of crystal grains of the active layer, a solid state laser annealing method with low cost is adopted, or a second excimer laser annealing method with larger scanning interval is adopted to manufacture a second active layer, so that the cost is reduced; in the display region 10 or the operable region (AA) with relatively high requirement on the uniformity of the active layer grains, one or a combination of the solid-state laser annealing method, the oxide patterning method and the first excimer laser annealing method with a smaller scanning pitch is used to manufacture the first active layer, so as to ensure the electrical performance of the active layer of the thin film transistor in the display region 10. Therefore, compared with the prior art of manufacturing the active layer of the whole panel by adopting an excimer laser annealing method, the display effect of the display panel is not reduced or the display effect meets the requirements of display equipment by matching different manufacturing methods such as ELA and SLA, and the production and manufacturing cost is reduced.

The method for manufacturing the active layer is applied to a manufacturing process of a display panel, and the display panel can be an OLED panel such as an Active Matrix Organic Light Emitting Diode (AMOLED) panel, a liquid crystal display panel such as a low temperature polysilicon thin film transistor liquid crystal display panel (LTPS TFT-LCD) or the like.

The above-described embodiments are further described below in conjunction with specific embodiments.

And forming a low-temperature polysilicon layer as a second active layer in the type I and GOA areas by adopting an SLA method. The following specific schemes can be adopted:

scheme 1:

in the first sub GOA region 231 located at one side of the AA region, a first low-temperature polysilicon layer is fabricated using an SLA solid state laser annealing method, and in the second sub GOA region 232 located at the other side of the AA region, a second low-temperature polysilicon layer is fabricated using an SLA solid state laser annealing method, the second low-temperature polysilicon layer serving as an active layer of LTPS TFTs located at the array gate driving region.

In the AA region, an oxide film is formed by an oxide patterning method and serves as an active layer of an oxide TFT of the AA region. Wherein the oxide film may be IGZO or others such as InNdO oxide and the like.

The cost reduction principle of the scheme 1 is as follows: the display panel, especially the OLED display panel, the AA area has higher requirement on the uniformity of the TFT characteristic, but has no particularly high requirement on the mobility of the TFT, so that the oxide TFT formed in the AA area can also meet the performance requirement; in the GOA region, the requirements for TFT characteristic uniformity are low, but the requirements for TFT mobility are high, so that the performance requirements can be met by manufacturing LTPS TFTs in the GOA region.

The scheme 1 is suitable for preparing low-cost LTPO display products, such as LTPO-TFT AMOLED, and can be applied to products with medium-large size and low pixel density (Pixels Per Inch, PPI) requirements of Notebook computers (NB) and the like, so that the purpose of reducing the cost is achieved.

Scheme 2:

In the AA area, a composite film of low-temperature polysilicon and an oxide semiconductor is formed by combining an SLA solid-state laser annealing method with an oxide patterning method and is used as an active layer of an LTPO TFT in the AA area.

The cost reduction principle of the scheme 2 is as follows: the AA area of the display panel has higher requirement on uniformity of TFT characteristics, so LTPO TFT is formed in the AA area to meet the performance requirement; and the requirement on the uniformity of the characteristics of the TFT in the GOA region is low, but the mobility requirement on the TFT is high, so that the LTPS TFT can be manufactured to meet the performance requirement.

The scheme 2 is suitable for manufacturing low-cost LTPO display products, such as LTPO-TFT AMOLED, which can be applied to Notebook computers (NB) and the like, and has low requirements on large-size PPI, but is superior to the display product of the scheme 1, so that the purpose of reducing the cost is achieved.

Scheme 3:

In the AA area, a composite film comprising low-temperature polysilicon and an oxide semiconductor is formed by adopting a first excimer laser annealing method and an oxide patterning method, and the composite film is used as an active layer of an LTPO TFT in the AA area.

The cost reduction principle of the scheme 3 is as follows: the AA region has higher requirements on uniformity and mobility of the TFT characteristics, so that the LTPO TFT is formed by adopting a first excimer laser annealing method with small scanning interval and combining an oxide patterning method, and the requirement on the uniformity of the TFT characteristics in the GOA region is lower, but the requirement on the mobility of the TFT is high, so that the LTPS TFT is formed in the GOA region to meet the performance requirements. Scheme 3 is suitable for manufacturing LTPO products with low cost and high image quality requirements, and the sizes of the display products can be medium and small sizes or medium and large sizes.

Scheme 4:

And forming a low-temperature polysilicon layer in the AA region by adopting a first excimer laser annealing method to serve as an active layer of the LTPO TFT.

The cost reduction principle of the scheme 4 is as follows: the LTPS TFT layer of the GOA region is manufactured by adopting an SLA method with lower cost, so that the requirement of the GOA region on mobility can be met; and the LTPS TFT layer is manufactured in the AA area by adopting a first ELA method with small scanning interval, so that the crystal grain uniformity of the low-temperature polysilicon active layer is better, and the requirement of the AA area on the uniformity of image quality is met. Scheme 4 is suitable for manufacturing display products with higher image quality requirements.

And forming a low-temperature polycrystalline silicon layer serving as a second active layer in the second type GOA region by adopting a second excimer laser annealing method with relatively larger scanning interval. Two specific embodiments may be employed as follows:

scheme 5:

a second excimer laser annealing method with larger scanning interval is adopted to fixedly manufacture a low-temperature polysilicon layer in a first sub GOA region 231 and a second sub GOA region 232 which are positioned at two sides of the AA region; and in the AA area, a first excimer laser annealing method with smaller scanning interval is adopted to form a low-temperature polysilicon layer which is used as an active layer of the LTPS TFT.

The cost reduction principle of the scheme 5 is as follows: aiming at different requirements of a GOA area and an AA area on TFT performance, process parameters of an ELA method are set in a targeted mode, wherein in the GOA area with relatively low requirement on low-temperature polysilicon grain uniformity, an ELA process with a larger scanning distance (Pitch) is adopted for manufacturing, and the process cost is reduced while the driving requirement performance is met; and in an AA area with relatively high requirement on the uniformity of the polycrystalline silicon crystal grains, the manufacturing is performed by adopting an ELA process with a smaller Pitch, so that the requirement on the uniformity of the crystal grains of the low-temperature polycrystalline silicon is ensured.

The scheme 5 is suitable for display products with low cost and high image quality requirements, is particularly suitable for OLED products with medium and large sizes, and can be applied to the protection range of the OLED products in the display products with medium and small sizes.

Scheme 6:

a second excimer laser annealing method with larger scanning interval is adopted to fixedly manufacture a low-temperature polysilicon layer in a first sub GOA region 231 and a second sub GOA region 232 which are positioned at two sides of the AA region;

in the AA area, a first excimer laser annealing method with smaller scanning distance is combined with an oxide patterning method to form a composite film comprising low-temperature polysilicon and an oxide semiconductor, and the composite film is used as an active layer of an LTPO TFT in the AA area.

The cost reduction principle of the scheme 6 is as follows: in a GOA region with relatively low requirement on low-temperature polysilicon grain uniformity, an ELA process with larger scanning interval (Pitch) is adopted for manufacturing, so that the process cost of the GOA region is reduced while the driving requirement performance is met; in the AA region with relatively high requirement on the uniformity of the polysilicon grains, the active layer of the LTPO TFT can be formed by adopting an ELA process with smaller Pitch and an oxide patterning method, so that the process cost of the AA region can be reduced while the requirement on the uniformity of the grains of the low-temperature polysilicon is ensured.

The scheme 6 is suitable for display products with low cost and high image quality requirements, is particularly suitable for medium-and-large-size OLED products, and can be applied to the protection range of the right of the OLED products in medium-and-small-size display products.

In schemes 1 to 6, a low-cost high-image-quality display panel is obtained by adopting different processes, such as a combination of a high-cost small-scanning-pitch ELA process and a low-cost large-scanning-pitch ELA process or SLA process, in different regions and combining the manufacture of fusing low-temperature polycrystalline oxide LTPO into an oxide AA region.

The medium and large size mentioned in the above-mentioned scheme refers to a display product of 7.9 inches or more, such as 7.9 inches, 9.7 inches, 12.9 inches, 15 inches, 19 inches, 21 inches, 25 inches, 22 inches, 55 inches, 65 inches, 77 inches, etc.; medium and small dimensions refer to display products of less than 6.4 inches, such as 1.8 inches, 2.0 inches, 2.1 inches, 2.2 inches, 2.4 inches, 2.6 inches, 2.8 inches, 3.0 inches, 3.2 inches, 3.4 inches, 3.5 inches, 3.6 inches, 3.7 inches, 3.8 inches, 3.9 inches, 4.0 inches, 4.1 inches, 4.2 inches, 4.3 inches, 4.5 inches, 5.0 inches, 5.5 inches, 6.0 inches, 6.4 inches, and the like.

In summary, the method for manufacturing the active layer of the display panel according to the present embodiment is based on different requirements of the GOA area and the AA area in the display panel for TFT performance, and performs differential control on the manufacturing process of the active layer. The AA area has higher requirement on the uniformity of the TFT characteristics and has not very high requirement on the mobility of the TFT, so that a first excimer laser annealing method with smaller scanning interval can be adopted to manufacture an active layer of the LTPS TFT, and a first excimer laser annealing method can be combined with an oxide patterning method to manufacture an active layer of the LTPO TFT, thereby improving the uniformity of crystal grains and reducing or eliminating Mura defects; in addition, for the display panel with low requirement on image quality, the active layer of the oxide TFT can be manufactured by adopting an oxide patterning method only so as to meet the requirement of the AA region on the TFT performance.

In the GOA region, the requirement on TFT characteristic uniformity is low, but the requirement on TFT mobility is high, so that the active layer of LTPS TFT can be manufactured by SLA solid state laser annealing method, and the active layer of LTPS TFT can be manufactured by second excimer laser annealing method with larger scanning interval, so long as the above design requirement is satisfied. Compared with the original ELA method adopting smaller scanning space to manufacture a complete active layer, the method can reduce the process cost while ensuring that the display effect is not reduced.

Further, in the above scheme, when the active layer is formed, key process parameters of the first excimer laser annealing method adopted include:

scan Pitch: the preferable range is from 7 μm to 18. Mu.m, and from 5 μm to 18. Mu.m.

Laser frequency: 400Hz to 700Hz, preferably 500Hz to 600Hz.

Key process parameters of the second excimer laser annealing method include:

scan Pitch: 22-35 μm, preferably 22-30 μm;

laser frequency: 400Hz to 700Hz, preferably 500Hz to 600Hz.

Before the implementation of the scheme, the scanning interval of the conventional ELA process is 19-21 mu m.

For the solid-state laser annealing SLA, key process parameters include:

scanning pitch:2 μm to 8 μm, preferably in the range of 2 μm to 5 μm;

laser frequency: 8000 Hz-12000 Hz, preferably 9kHz,10kHz, etc.

By adopting the technical parameters for control, the performance of the active layers in different areas can be ensured to meet the corresponding requirements while the technical cost is reduced, so that the display effect of the display panel is consistent relative to the scheme of adopting the ELA technology at one time, and the technical effects of reducing the cost and enhancing the efficiency are obtained.

In a second alternative embodiment, based on the same inventive concept, there is provided a display panel comprising a substrate and an active layer disposed on the substrate, the active layer being fabricated using the fabrication method of any one of the embodiments of the first aspect.

The display panel can be an OLED panel such as an AMOLED panel, or an LCD display panel such as an LTPS TFT-LCD.

When the active layer manufacturing method in the foregoing embodiment is used to manufacture the display panel, the manufacturing process of the back plate structure therein is not changed compared with the original process, and only when the active layer is manufactured, different combination processes are used to manufacture the active layer in the AA area and the GOA area.

Taking an AMOLED with LTPS as an active layer as an example, the backlight structure can adopt an 11MASK process, and the flow is as follows:

sequentially carrying out the following steps on a substrate: active mask process of Active layer- & gt first Gate layer Gate 1mask process- & gt second Gate layer Gate2 mask process- & gt edge bending layer EB mask process- & gt first source drain layer SD 1mask process- & gt mask process EBB of buffer layer and etching barrier layer- & gt first planarization layer PLN 1mask process- & gt second source drain layer SD2 mask process- & gt second planarization layer PLN2 mask process- & gt Anode layer Anode mask process- & gt mask process of pixel limiting layer PDL and isolation column layer PS.

If the BSM mask process is added, the process flow is as follows:

sequentially carrying out the following steps on a substrate: the method comprises the steps of a bottom shielding metal BSM mask process, an Active mask process of an Active layer, a Gate 1mask process of a first Gate layer, a Gate2 mask process of a second Gate layer, an edge bending layer EB mask process, a SD 1mask process of a first source drain layer, a mask process EBB of a buffer layer and an etching barrier layer, a PLN 1mask process of a first planarization layer, a SD2 mask process of a second source drain layer, a PLN2 mask process of a second planarization layer, an Anode layer Anode mask process, and a mask process of a pixel limiting layer PDL and a isolation column layer PS.

Taking an AMOLED with LTPO as an active layer as an example, the backlight structure can adopt a 14MASK process, and the process flow is as follows:

sequentially carrying out the following steps on a substrate: active mask process of Active layer, gate 1mask process of first Gate layer, gate2 mask process of second Gate layer, indium gallium zinc oxide IGZO mask process of third Gate layer, gate3 mask process of third Gate layer, ILD-O mask process of first edge bending layer EB1+ interlayer dielectric layer, ILD-L mask process of second edge bending layer EB2+ interlayer dielectric layer, SD 1mask process of first source drain layer, PVX mask process of passivation layer, PLN 1mask process of first planarization layer, SD2 mask process of second source drain layer, PLN2 mask process of second planarization layer, anode mask process of Anode layer, mask process of pixel limiting layer PDL and isolation column layer PS.

If the BSM mask process is added, the process flow is as follows:

sequentially carrying out the following steps on a substrate: the method comprises the steps of a bottom shielding metal BSM mask process, an Active mask process of an Active layer, a Gate 1mask process of a first Gate layer, a Gate2 mask process of a second Gate layer, an indium gallium zinc oxide IGZO mask process, a Gate3 mask process of a third Gate layer, a first edge bending layer EB1+ interlayer dielectric layer ILD-O mask process, a second edge bending layer EB2+ interlayer dielectric layer ILD-L mask process, a first source drain layer SD 1mask process, a passivation layer PVX mask process, a first planarization layer PLN 1mask process, a second source drain layer SD2 mask process, a second planarization layer PLN2 mask process, an Anode layer Anode mask process, and a mask process of a pixel limiting layer PDL and a isolation column layer PS.

It should be noted that, the introduction of the embodiment of the disclosure does not affect the normal process flow, and only the Active part of the Active layer is required to be manufactured in a partitioning manner.

In a third aspect, referring to fig. 3, in another alternative embodiment, a display device is provided, including a display panel provided in the second aspect, based on the same inventive concept. The display device can be a handheld electronic device or a mobile electronic device, such as a mobile phone, a tablet personal computer and a PDA, and can also be a display, a television, an integrated computer, a conference display integrated machine and the like with various sizes.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A method for manufacturing an active layer of a display panel, comprising:

2. The method of manufacturing according to claim 1, wherein forming a second active layer in the array gate driving region using a solid state laser annealing method or a second excimer laser annealing method, comprises:

3. The method of manufacturing according to claim 2, wherein forming the first active layer in the display region using at least one of the solid state laser annealing method, the first excimer laser annealing method, and the oxide patterning method, comprises:

4. The method of manufacturing according to claim 2, wherein forming the first active layer in the display region using at least one of the solid state laser annealing method, the first excimer laser annealing method, and the oxide patterning method, comprises:

5. The method of manufacturing according to claim 2, wherein forming the first active layer in the display region using at least one of the solid state laser annealing method, the first excimer laser annealing method, and the oxide patterning method, comprises:

6. The method of manufacturing according to claim 2, wherein forming the first active layer in the display region using at least one of the solid state laser annealing method, the first excimer laser annealing method, and the oxide patterning method, comprises:

7. The method of manufacturing according to claim 1, wherein forming a second active layer in the array gate driving region using a solid state laser annealing method or a second excimer laser annealing method, comprises:

8. The method of manufacturing according to claim 7, wherein forming the first active layer in the display region using at least one of the solid state laser annealing method, the first excimer laser annealing method, and the oxide patterning method, comprises:

9. The method of manufacturing according to claim 7, wherein forming the first active layer in the display region using at least one of the solid state laser annealing method, the first excimer laser annealing method, and the oxide patterning method, comprises:

10. The method according to any one of claims 1 to 9, wherein the first excimer laser annealing method has a scanning pitch ranging from 5 μm to 18 μm and the second excimer laser annealing method has a scanning pitch ranging from 22 μm to 35 μm;

11. The method according to any one of claims 1 to 9, wherein the scanning pitch of the solid-state laser annealing method is in the range of 2 μm to 8 μm and the laser frequency is in the range of 8000Hz to 12000Hz.

12. A display panel comprising a substrate and an active layer provided on the substrate, the active layer being manufactured by the manufacturing method according to any one of claims 1 to 11.

13. A display device comprising the display panel of claim 12.