CN2611913Y

CN2611913Y - Device for testing chip compatible with chip operation system in integrated circuit card

Info

Publication number: CN2611913Y
Application number: CN 03230576
Authority: CN
Inventors: 陈桂岭; 廖圣宜; 印义中; 印义言
Original assignee: HUAYUAN MICRO ELECTRONIC TECHNOLOGY Co Ltd SHANGHAI
Current assignee: HUAYUAN MICRO ELECTRONIC TECHNOLOGY Co Ltd SHANGHAI
Priority date: 2003-04-22
Filing date: 2003-04-22
Publication date: 2004-04-14
Anticipated expiration: 2013-04-22

Abstract

The utility model relates to a device testing the compatibility of a chip operation system and a chip in an integrated circuit board, which comprises a printed circuit board (1), a card contact (11), the chip (12) in the certified integrated circuit board, a jumper (13), a memorizer (14) and a test pattern port (15) arranged on the printed circuit board (1), wherein the card contact (11) and the test pattern port (15) are connected with the chip (12) in the certified integrated circuit board, a control line (126) of the chip (12) in the certified integrated circuit board is connected with the memorizer (14) through the jumper (13), and a data bus line (128) and an address bus (127) of the chip (12) are connected with the memorizer (14) through the printed circuit board (1). During the course of testing the compatibility of the chip operation system and the chip in the integrated circuit board, the utility model is completely consistent with the integrated circuit board needing to be produced, and the price is low.

Description

The device of testing integrated circuits card chips operating system and chip compatibility

Technical field

The utility model relates to a kind of proving installation, relates in particular to the device of a kind of testing integrated circuits card chips operating system and chip compatibility.

Background technology

Chip in the integrated circuit card is the chip that inside has CPU (microprocessor), and it is to have COS (chip operating system) to support with the maximum difference of chip in the general storage card, could guarantee the operate as normal of application system.Different application systems has different COS standards, made social security (individual) calliper model as Ministry of Labour and Social Security, People's Bank of China has worked out China's finance integrated circuit (IC) calliper model or the like, to the instruction set of COS operating system, clear and definite regulation has all been done in file system, security.Also root is many in the COS manufacturer of the same application system of one side, for example is that the COS that is used for social security card has a plurality of manufacturers produce equally, and identical standard all will be observed by each manufacturer, but the code that each manufacturer writes is diverse; Basic demand for the chip in the integrated circuit card all has corresponding international standard and national standard to do clear and definite regulation on the other hand, but meeting the chip that has CPU that each chip manufacturer produces under the prerequisite of these standards, order set, its register address etc. all may be different fully.The chip that has a CPU have only by with the cooperation of each COS manufacturer and chip maker, design the COS that can on the chip that has CPU of chip manufacturers produce, normally move and meet corresponding code requirement fully, then when chip production, by the method for mask, COS mask forward (FWD) there is the integrated circuit card that just can become among the ROM of chip of CPU truly.The integrated circuit card that has COS that chip manufacturer final production goes out must detect compliant and require just can put goods on the market through the strictness of national coherent detection unit.If detect the place that does not meet standard then must remodify the COS operating system software, produce again, and this will inevitably cause a large amount of wastes on the time and money.

In order to address this problem, current chip designing unit can provide a cover hardware circuit to COS manufacturer, so that COS can transplant smoothly.Usually way is that the chip that has CPU is made the form of a kind of like this emulation of FPGA (field programmable logic array (FPLA) device): the function that replaces realizing having the chip of CPU on the one hand with FPGA, can only a kind of at last emulation on RTL (register transfer level) circuit, therefore chip in the integrated circuit card truly also has difference, and it is compatible fully to protect positive COS and the final chip that has CPU; The price of FPGA is also very expensive on the other hand, and this has also limited to a certain extent is transplanted to the COS of different COS manufacturers on the chip that has CPU.

Summary of the invention

The utility model technical issues that need to address have provided the device of a kind of testing integrated circuits card chips operating system and chip compatibility, are intended to solve the compatibility and the very expensive defective of proving installation price of emulation in the test process.

In order to solve the problems of the technologies described above, the utility model is achieved through the following technical solutions:

The utility model comprises printed circuit board, card contact, the chip in the integrated circuit card of checking, jumper wire device, storer, test pattern port.Described card contact, the chip in the integrated circuit card of checking, jumper wire device, storer and test pattern port are installed on the described printed circuit board.Chip in the integrated circuit card of described card contact and test pattern port and checking is connected, the control line of the chip in the integrated circuit card of described checking is connected with described storer by jumper wire device, the data bus of the chip in the integrated circuit card of described checking is connected with storer by printed circuit board with address bus, and the chip in the integrated circuit card of described test pattern port and checking is connected.

Compared with prior art, the beneficial effects of the utility model are: in testing integrated circuits card chips operating system and the compatible process of chip, consistent with the integrated circuit card that needs to produce, and cheap fully.

Description of drawings

Fig. 1 is a block scheme of the present utility model;

Fig. 2 is the circuit block diagram of the chip in the integrated circuit card of verifying in the utility model;

Fig. 3 is the block diagram of the chip in the integrated circuit card of verifying in the utility model;

Fig. 4 is a fundamental diagram of the present utility model.

Wherein: printed circuit board 1, card reader 2, PC 3, card contact 11, the chip 12 in the integrated circuit card of checking, jumper wire device 13, storer 14, test pattern port one 5, scratch pad memory 121, CPU122, random access memory 123, ISO7816 serial ports 124, input/output port 125, control line 126, address bus 127, data bus 128, test pattern lead-in wire 129, test logic 130.

Embodiment

Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail:

By Fig. 1, Fig. 2, Fig. 3, Fig. 4 as seen: the utility model comprises printed circuit board 1, card contact 11, the chip 12 in the integrated circuit card of checking, jumper wire device 13, storer 14, test pattern port one 5.Described card contact 11, the chip 12 in the integrated circuit card of checking, jumper wire device 13, storer 14 and test pattern port one 5 are installed on the described printed circuit board 1.Chip 12 in the integrated circuit card of described card contact 11 and test pattern port one 5 and checking is connected, the control line 126 of the chip 12 in the integrated circuit card of described checking is connected with described storer 14 by jumper wire device 13, the data bus 128 of the chip 12 in the integrated circuit card of described checking is connected with storer 14 by printed circuit board 1 with address bus 127, described test pattern port one 5 with the checking integrated circuit card in chip 12 be connected.

Chip 12 in the integrated circuit card of described checking comprises scratch pad memory 121, CPU122, random access memory 123.Described scratch pad memory 121, CPU122 and random access memory 123 are connected with card contact 11, and the control line 126 of described scratch pad memory 121, CPU122 and random access memory 123 is connected with jumper wire device 13; The address bus 127 of the data bus 128 of described scratch pad memory 121, CPU122 and random access memory 123 is connected with storer 14 by printed circuit board 1;

Described storer 14 is ROM (read-only memory), or scratch pad memory;

The shape of described printed circuit board 1 is consistent with general integrated circuit card shape;

The shape and the position consistency of card contact in the shape of described card contact 11 and position and the general integrated circuit card.

On printed circuit board 1, printed card contact 11 on the one hand, the width of this printed circuit board 1 and thickness and the size, the position that are printed on the card contact 11 on the printed circuit board 1 all meet the regulation of standard GB/T 16649 " integrated circuit card of identification card contact-carrying ", this printed circuit board 1 just can have correct electrical connection as direct insertion card reader 2 of common integrated circuit card and card reader 2 like this; Chip 12 in the integrated circuit card that a slice tests the checking that COS uses also has been installed, the different ROM (read-only memory) that are used to deposit the COS operating system software in (1) this chip internal manufacturing that are in of the chip in this chip and the common integrated circuit card on this printed circuit board 1; (2) this chip is the address bus 127 of CPU122, data bus 128, and control line 126 all has been connected on the external-connected port of chip.Like this this Chip Packaging and be installed on the printed circuit board 1 after, the address bus 127 of chip, data bus 128, control line 126 all has been connected on the printed circuit board 1.Chip 12 in the integrated circuit card of this checking is except above 2, and its performance parameter is all identical with chip in the integrated circuit card of the final required installation of COS operating system that is verified.

Jumper wire device 13 also has been installed on printed circuit board 1, can be the storer 14 and the test pattern port one 5 of ROM (read-only memory) or scratch pad memory.

The correspondence lead-in wire port of the chip 12 in the integrated circuit card of card contact 11 and checking is connected, and the described corresponding port that goes between is being connected by ISO7816 serial ports 124 and input/output port 125.The control line 126 of the chip 12 in the integrated circuit card of checking links to each other with storer 14 by jumper wire device 13, and the data bus 128 of the chip 12 in the integrated circuit card of checking and address bus 127 are connected with storer 14 by printed circuit board 1.Test pattern port one 5 is connected by the test logic 130 in the chip in the integrated circuit card of test pattern lead-in wire 129 on the printed circuit board 1 and checking.Just formed a complete IC card chip system like this on the printed circuit board 1.When test mode signal is delivered to test logic 130 in the chip 12 integrated circuit card of checking from test pattern port one 5, need the COS operating system software of checking can download in the storer 14.This printed circuit board 1 is inserted into card reader 2 backs just can operate operation as the IC card chip of a common band microprocessor.Card reader 2 links to each other with PC 3.Whether whether PC 3 just can carry out every test by the IC card chip system that 2 pairs of these printed circuit boards of card reader 1 are formed like this, correct with the COS operating system software on the verification system, can operation normally on this IC card chip.If find in operation wrongly, download to test once more in the storer 14 again after then can revising COS software.Till normal fully.Because the chip 12 in the integrated circuit card of checking is except the ROM (read-only memory) that do not have chip internal with address bus 127, data bus 128, outside control line 126 was drawn, other characteristic parameters all and identical by the IC card chip of the required final installation of COS operating system checked and accepted.Therefore the COS operating system of verifying on this printed circuit board 1 can be fabricated onto in the IC card chip fully relievedly.

On the other hand, the IC card chip manufacturing tries flow owing to need plate-making, and the initial stage drops into very big.It is also very big to drop into batch process back output, and the output more than 1,000,000 must be arranged.If a small amount of make then the cost of every chip can be very high.Chip 12 demands in the integrated circuit card of the checking in the utility model only at tens to the hundreds of sheet.Can't accept for its Development and Production cost specially.But because chip manufacturer must try flow earlier when releasing new chip.Generally can adopt the examination flow of putting together of the product of various trial-productions, be called MPW (plan of polycrystalline garden) to reduce experimental manufacturing cost.When adopting the MPW mode to manufacture experimently new chip, make simultaneously the chip in the integrated circuit card of the checking in the utility model 12 then that cost will descend greatly, its price is much cheaper than FPGA.

Claims

1. the device of testing integrated circuits card chips operating system and chip compatibility, it is characterized in that: comprise printed circuit board (1), card contact (11), chip (12) in the integrated circuit card of checking, jumper wire device (13), storer (14) and test pattern port (15), described card contact (11), chip (12) in the integrated circuit card of checking, jumper wire device (13), storer (14) and test pattern port (15) are installed on the described printed circuit board (1), chip (12) in the integrated circuit card of described card contact (11) and test pattern port (15) and checking is connected, the control line (126) of the chip in the integrated circuit card of described checking (12) is connected with described storer (14) by jumper wire device (13), and the data bus (128) of the chip in the integrated circuit card of described checking (12) is connected with storer (14) by printed circuit board (1) with address bus (127).

2. the device of a kind of testing integrated circuits card chips operating system according to claim 1 and chip compatibility, it is characterized in that: the chip in the integrated circuit card of described checking (12) comprises scratch pad memory (121), CPU (122), random access memory (123), described scratch pad memory (121), CPU (122) is connected with card contact (11) with random access memory (123), described scratch pad memory (121), the control line (126) of CPU (122) and random access memory (123) is connected with jumper wire device (13), described scratch pad memory (121), the data bus (128) of CPU (122) and random access memory (123) is connected with storer (14) by printed circuit board (1) with address bus (127).

3. the device of a kind of testing integrated circuits card chips operating system according to claim 1 and chip compatibility, it is characterized in that: described storer (14) is a ROM (read-only memory), or scratch pad memory.

4. the device of a kind of testing integrated circuits card chips operating system according to claim 1 and chip compatibility is characterized in that: the width of described printed circuit board (1) is consistent with general integrated circuit card with thickness.

5. the device of a kind of testing integrated circuits card chips operating system according to claim 1 and chip compatibility is characterized in that: the shape and the position consistency of card contact in the shape of described card contact (11) and position and the general integrated circuit card.