CN101169755A

CN101169755A - Test pin free contact type CPU card test method

Info

Publication number: CN101169755A
Application number: CNA2006101140936A
Authority: CN
Inventors: 张海峰
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2006-10-27
Filing date: 2006-10-27
Publication date: 2008-04-30

Abstract

The invention provides a contact-type method for testing a CPU card of which the program memory is the electrical erasable memory without testing pin. The method carries out erasing function to the program memory by loading an erasing control signal to the program memory, an erasing address and a data string through the IO pin of the IC card. Thus, the function testing program of the chip can be loaded and written into the program memory through an IO string, and the function testing to the chip can be carried out by operating the function testing program in the program memory. In the testing method, the testing pin is shared with the standard pin of the IC card, thus the separate chip testing pin is not added, so as to improve the safety of the chip and reduce the area of the chip.

Description

Test pin free contact type CPU card test method

Technical field

The present invention is mainly used in the contact type CPU card test circuit that various program storages are the electrically-erasable storer.

Background technology

Arrival along with digital society, more and more can use various types of electronic products in the life, IC-card is exactly the electronic product that a kind of and people's daily life are closely related, and also suitable many in its application scenario are such as mass transit card, SIM card, bank card, ID card or the like.Be to guarantee the correct of the function of product and performance by a series of test for the card series products of such production in enormous quantities finally giving before the user uses so.And what at first should guarantee as the deviser of chip is the correctness of chip hardware function.So just needing such means of testing filters out the product that meets our designing requirement and offers the user and use from the chip of factory process.

And will satisfy in the large-scale production the detecting of chip non-defective unit, the circuit that just should have a function to entire chip, performance and reliability to test is finished this testing.And along with the progressively development of industry is not only that requirement can filter out non-defective unit accurately for test job at present, efficient that the more important thing is test wants the cost of height, test low, the security of test circuit wants high, can not allow the disabled user obtain chip hardware and information of software, thereby preventing that the disabled user from attacking chip by these information that steal make the just rights and interests of validated user receive infringement by test circuit.

Summary of the invention

The present invention realizes that for addressing the above problem program storage is the functional test of the contact type CPU card of electrically-erasable storer, adopts following scheme:

With functional test program being sent in the serial input register group by the serial of IO pin, give program storage through the corresponding signal that will satisfy the erasable sequential of program storage after the parallel register group, finish that test procedure is downloaded to function in the program storage.

After the functional test program is downloaded and is finished, again by the test procedure in the CPU working procedure storer, whether the result of comparison program run is correct automatically in the process of operation for test procedure, and with test result by IO pin sending of serial again, monitor the output result of IO by test machine, can judge by this result whether the chip functions test is correct.

The sub-fraction of key signal in the test circuit has been placed on scribe line, after the chip thinning scribing, can destroy this part circuit, so just can guarantee that chip can not enter into test pattern again after dispatching from the factory, the disabled user just can not come the hardware configuration and the software content of detection chip by test circuit.

The present invention has following advantage:

1, finishes test function by the standard pin of IC, area of chip of not only having saved but also the security that has increased chip to chip.

2, the functional test program is downloaded in the program storage move, such test mode is the same with the situation that chip normally moves COS, and such test mode is more near the real work situation of chip.

3, functional test program automatic result of contrastive test in the process of operation, and test result is sent correctness by test machine contrastive test result by the test I pin.

4, save area of chip, improved the security of test circuit.

Description of drawings

Fig. 1 general structure block diagram, the IO of left and right-hand IO are same pins among the figure, are two-way pins of opening leakage, are the standard pin of IC-card.

Fig. 2 puts into the synoptic diagram of scribe line part

Embodiment

Fig. 1 is an overall construction drawing of the present invention, there is shown the annexation of each module.Describe one embodiment of the present of invention in detail below in conjunction with Fig. 1.

One, be that to introduce it be how to be written in the program storage to example with a byte " F5H ":

Under the test pattern of chip, use a privately owned host-host protocol that " F5H " and " F5H " corresponding address in test procedure is sent into and write in the serial input register group (1) by IO pin serial-by-bit, after all relevant bits of " F5H " write operation are all write in (1), test circuit can produce a marking signal, can be with corresponding again being written in the parallel register group (2) of all data in (1) when chip detection is effective to this marking signal.

This moment again with in (2) about " F5H " thus erasable control signal and data and appropriate address send into to finish according to the erasable control timing of program storage " F5H " byte be written to operation in the program storage (3).

Two, the operation of test procedure and comparison:

According to above-mentioned ablation process can with the functional test program successively be written to corresponding address in (3),

Allow chip enter into function testing mode after finishing and chip is normally operated under the mode of operation when all test procedures write, CPU read functions test procedure from (3) is carried out, and compares operation result voluntarily.Produce test result.

Three, sending of test result:

The test result of above-mentioned generation is sent in the serial output register (4), and again test result is sent by two-way pin IO serial.

Introduce each module below respectively:

Serial input register group (1), it mainly is the shift register group that constitutes by d type flip flop, its effect will temporarily store from the order to program storage (3) write operation of IO pin serial-by-bit input exactly, as the input end of parallel register group (2).

Parallel register group (2), it mainly is the registers group that constitutes by d type flip flop, be connected with (1), after in complete being written to of write order (1) that sends by the IO pin, (2) all data in (1) can be duplicated, and to distinguish those are data bit, and those are address bits, those are erasable control signal positions, and the signal that these are corresponding is sent to the corresponding input pin of program storage.

Program storage (3) after the once input that receives (2), is finished once write operation to program storage according to the signal of input.

Serial output register (4) mainly is the shift register group that is made of d type flip flop, and its effect is shifted out the functional test results step-by-step, and by the IO pin output step-by-step of (4) is sent exactly.

Above circuit structure can be finished the chip functions test assignment.

Fig. 2 is a circuit diagram of putting into the scribe line part, and test circuit will reach high security, guarantees that with regard to needing enough measures the disabled user can not attack the hardware and the software of chip by test circuit, thereby steals the validated user data.

As shown in Figure 2, the present invention has adopted and important control signal wire of test circuit part can be put in the scribe line together with a d type flip flop relevant with this signal wire, after chip testing finished reduction scribing, this d type flip flop of putting into scribe line will be crossed out.Clearly provide to test circuit after the user and just can not work again, and also be difficult to this key signal is reconnected by the mode of FIB when chip envelope card.So instant disabled user understands the test circuit structure of chip also can not do any rogue attacks to chip again by test circuit.

Claims

1. test pin free contact type CPU card test method mainly is by the IO pin chip to be sent in the functional test program serial of chip, be written in the program storage by test circuit again, CPU carries out the functional test program that is written in the program storage then, it is characterized in that: the two-way IO pin by IC-card is sent to serial input register group (1) with the serial of functional test program, the data that serial is sent into are temporary in (1), and then be written into parallel register group (2) again, in (2), distinguish to the erasable control signal of program storage and address and data parallel again be sent to program storage (3) thus the functional test program is written in the program storage, test procedure in the operation (3) and the result that will move are written in the serial output register (4), again by two-way IO pin with the sending of the test result serial in (4), monitor output result's correctness by test machine.

2. according to the test circuit of claim 1, it is characterized in that test procedure that serial is sent into parallel deliver to parallel register group (2), thereby can produce satisfy program storage (3) erasable sequential to finish erasable operation to Flash.

3. according to the test circuit of claim 1, it is characterized in that the result of test procedure operation can be sent by two-way IO pin by serial output register (4) again.

4. according to the test circuit of claim 1, it is characterized in that and the control circuit of a key in the test circuit partly can be put in the scribe line, after the chip thinning scribing, just can not enter into the test pattern of chip again.