CN104459519A - Chip safety testing method and device - Google Patents
Chip safety testing method and device Download PDFInfo
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- CN104459519A CN104459519A CN201410742834.XA CN201410742834A CN104459519A CN 104459519 A CN104459519 A CN 104459519A CN 201410742834 A CN201410742834 A CN 201410742834A CN 104459519 A CN104459519 A CN 104459519A
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Abstract
The invention discloses a chip safety testing method and device. The method includes the following steps: when a chip is in a tested mode, judging whether a chip fuse wire is in a physical connection state or not and whether a chip testing sign word is written or not; if the chip fuse wire is in the physical connection state and the chip testing sign word is not written, entering corresponding testing items according to an input command word, and writing the chip testing sign word after all the testing items are completely tested. By means of the chip safety testing method and device, the safety performance of a chip testing mode in the prior art can be improved.
Description
Technical field
The present invention relates to chip testing field, particularly relate to a kind of chip secure method of testing and device.
Background technology
Be in flourish period with the domestic IC industry that movement, fiscard are changed in a large number as background, along with the increase day by day of smart card issuance amount, chip secure sex chromosome mosaicism also seems more and more important.Wherein, the test process after chip dispatches from the factory is the important stage in chip Life cycle, and in this stage, tester has all operations authority to storer.And test needs to load boot boot before terminating, pay the Chip Operating System (Chip Operating System, COS) that user downloads supporting chip operation.Therefore the level of security of test pattern is very high, once victim invades, can do malicious attack, can bring unthinkable harm to storer or boot.At present, common attack means makes a forcible entry into chip test mode for being attacked by intrusive moods such as physical connections, or read by methods such as simple power consumption analysis (SPA), differential power consumption analysis (DPA) and change boot, and then amendment user COS.
For the problems referred to above, prior art adopts following scheme: connect with chip fuse (fuse) and ensure that chip is in test state, enter corresponding test item by one group of password.At the end of test state, draw disconnected fuse, after this chip can not enter test pattern again; Be, before test terminates, a fixing key is write to chip to the protection of boot, be stored in system power failure and do not lose in memory block, do cryptographic storage by algorithm and double secret key boot content.
Although such scheme has certain safe design for test pattern, if assailant connects upper fuse by physics mode carry out intrusive mood attack, and the pattern password of breaking through still can enter test pattern.And for the storage of boot program, traditional safety Design arranges fixed password to all chips, although boot is that ciphertext stores like this, there is certain security, as long as but assailant takes the cost of multiple sample, and certain hour breaks through a chips, is so equivalent to entire block and has all been broken.
Summary of the invention
The invention provides a kind of chip secure method of testing and device, the security of prior art chips test pattern can be improved.
In order to solve the problem, the invention provides a kind of chip secure method of testing, comprising the following steps: when chip is in test pattern, judge whether chip fuse is in physical connection state, and whether chip testing banner word writes; If described chip fuse is in physical connection state, and described chip testing banner word does not write, and the command word according to input enters corresponding test item, after all test items have all been tested, writes described chip testing banner word.
Further, when described chip enters described test pattern, generate key according to the specific initial information that test host computer provides, be encrypted by described double secret key bootstrap boot.
Further, described specific initial information comprises test duration and chip coordinate.
Further, described chip testing banner word is written in the specific region of described chip, and power down is not lost.
Further, be written into if described chip fuse draws disconnected or described chip testing banner word, then terminate described test pattern.
The present invention also provides a kind of chip secure proving installation, comprising: judge module and test module, described judge module, for when chip is in test pattern, judges whether chip fuse is in physical connection state, and whether chip testing banner word writes; Described test module, if be in physical connection state for described chip fuse, and described chip testing banner word does not write, and the command word according to input enters corresponding test item, after all test items have all been tested, writes described chip testing banner word.
Further, chip secure proving installation provided by the invention also comprises encrypting module, described encrypting module, for entering described test pattern when described chip, generate key according to the specific initial information that test host computer provides, be encrypted by described double secret key bootstrap boot.
Further, described specific initial information comprises test duration and chip coordinate.
Further, described chip testing banner word is written in the specific region of described chip, and power down is not lost.
Further, described test module, is written into if draw disconnected or described chip testing banner word for described chip fuse, terminates described test pattern.
The present invention is that chip test mode provides and controls saferly.Except chip fuse (fuse) connection and pattern password, the present invention have also been devised chip testing banner word, flow process ensures test process is irreversible.Namely test phase terminates rear any calculated attack person and can not enter test circuit again.
In addition, for the safety problem of loading boot boot, the specific initial information that present pre-ferred embodiments utilizes test host computer to provide generates different key, by cryptographic algorithm cryptographic storage boot, so, ensure that each chip loads the inconsistency of boot, thus promote boot security.
Accompanying drawing explanation
Figure 1 shows that the process flow diagram of the chip secure method of testing that present pre-ferred embodiments provides;
Figure 2 shows that the structural drawing of the chip communication transmission frame that present pre-ferred embodiments provides;
Figure 3 shows that the schematic diagram of boot secure download in present pre-ferred embodiments.
Embodiment
Present pre-ferred embodiments provides a kind of chip secure method of testing, comprises the following steps: when chip is in test pattern, judges whether chip fuse is in physical connection state, and whether chip testing banner word writes; If described chip fuse is in physical connection state, and described chip testing banner word does not write, and the command word according to input enters corresponding test item, after all test items have all been tested, writes described chip testing banner word.
Present pre-ferred embodiments also provides a kind of chip secure proving installation, comprising: judge module and test module.Described judge module, for when chip is in test pattern, judges whether chip fuse is in physical connection state, and whether chip testing banner word writes; Described test module, if be in physical connection state for described chip fuse, and described chip testing banner word does not write, and the command word according to input enters corresponding test item, after all test items have all been tested, writes described chip testing banner word.The chip secure proving installation that present pre-ferred embodiments provides also comprises encrypting module, for entering described test pattern when described chip, generate key according to the specific initial information that test host computer provides, be encrypted by described double secret key bootstrap boot.
Specifically, Figure 1 shows that the process flow diagram of the chip secure method of testing that present pre-ferred embodiments provides.As shown in Figure 1, first need to be undertaken verifying (as step S01) by I/O port reception synchronous code and password, secondly, judge that chip is current successively and whether be in test pattern (as step S03), whether chip fuse (fuse) is in physical connection state (as step S04), and whether chip testing banner word (Label) writes (as step S05).If chip is current be in test pattern, under fuse is in physical connection state, and chip testing banner word is not when writing, different command word (as step S02) according to receiving enters different test items, and after all test items have all been tested, write chip testing banner word (being such as written as BB), and fuse is drawn disconnected.If chip fuse is drawn disconnected or chip testing banner word and is written into, terminate test pattern.Chip first can check chip testing banner word (Label) when powering on, if finding chip testing banner word is write value, then represent that test completes, chip can not enter test pattern again.So, ensure that chip testing state is irreversible, even if the information such as password are attacked, chip can not enter test pattern again.Wherein, chip testing banner word is written in the specific region of chip, and power down is not lost.
With reference to Fig. 2, the input mode of synchronous code and password is described.In this, synchronous code is 32, and password is 32 bytes.Specifically, chip carries out half duplex communication with test host computer in units of frame, and every frame comprises 8bit valid data and 1bit acknowledgement bit.Host computer is main frame, clocking; Chip is from machine, and the order that reception host computer sends and data, return an acknowledgement bit after often receiving 8bit valid data.Data on I/O port are read in card at the rising edge of each clock (CLK) by chip, and every 10 rising edge clocks complete a frame data transmission, and host computer gathers the acknowledgement bit on I/O port line between the nine to the ten rising edge clock of frame data.The form of expression of acknowledgement bit is that I/O port line is drawn as low level by chip between the 9th and the tenth rising edge clock, and the control of I/O port line will discharge to chip by host computer during this period.Can ensure that the password of often organizing that tester table inputs is all normal input like this.
Figure 3 shows that the schematic diagram of boot secure download in present pre-ferred embodiments.As shown in Figure 3, specifically, when generating key K ey in test mode, utilize the specific initial informations such as test test duration (such as date, Hour Minute Second) of providing of host computer and chip coordinate through fundamental operation as key K ey, this key K ey is downloaded in register Key_reg simultaneously, being encrypted initial boot program by key K ey, is different after ensureing the boot encryption in every wafer again.Wherein, as shown in Figure 3, key K ey such as can be stored together with chip testing banner word (Label).
In this, because specific to every chips, the test duration that test host computer provides and chip coordinate are diverse, even if the key victim formed after simple operation obtains, also the particular value of a chips can only be obtained, and cannot by the key information of exhaustive other chips of acquisition.Even and if encrypted boot program victim detection mode obtains, also can only take the boot program of destroyed current chip, and the boot program of other chips can not be changed, therefore greatly ensure that the security of loading boot.
More than show and describe ultimate principle of the present invention and principal character and advantage of the present invention.The present invention is not restricted to the described embodiments; what describe in above-described embodiment and instructions just illustrates principle of the present invention; without departing from the spirit and scope of the present invention, the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.
Claims (10)
1. a chip secure method of testing, is characterized in that, comprises the following steps:
When chip is in test pattern, judge whether chip fuse is in physical connection state, and whether chip testing banner word writes;
If described chip fuse is in physical connection state, and described chip testing banner word does not write, and the command word according to input enters corresponding test item, after all test items have all been tested, writes described chip testing banner word.
2. chip secure method of testing as claimed in claim 1, is characterized in that, also comprise:
When described chip enters described test pattern, generate key according to the specific initial information that test host computer provides, be encrypted by described double secret key bootstrap boot.
3. chip secure method of testing as claimed in claim 2, is characterized in that: described specific initial information comprises test duration and chip coordinate.
4. chip secure method of testing as claimed in claim 1, is characterized in that: described chip testing banner word is written in the specific region of described chip, and power down is not lost.
5. chip secure method of testing as claimed in claim 1, is characterized in that: be written into if described chip fuse draws disconnected or described chip testing banner word, then terminate described test pattern.
6. a chip secure proving installation, is characterized in that, comprising: judge module and test module,
Described judge module, for when chip is in test pattern, judges whether chip fuse is in physical connection state, and whether chip testing banner word writes;
Described test module, if be in physical connection state for described chip fuse, and described chip testing banner word does not write, and the command word according to input enters corresponding test item, after all test items have all been tested, writes described chip testing banner word.
7. chip secure proving installation as claimed in claim 6, it is characterized in that, also comprise encrypting module, described encrypting module, for entering described test pattern when described chip, generate key according to the specific initial information that test host computer provides, be encrypted by described double secret key bootstrap boot.
8. chip secure proving installation as claimed in claim 7, is characterized in that: described specific initial information comprises test duration and chip coordinate.
9. chip secure proving installation as claimed in claim 6, is characterized in that: described chip testing banner word is written in the specific region of described chip, and power down is not lost.
10. chip secure proving installation as claimed in claim 6, is characterized in that: described test module, is written into, terminates described test pattern if draw disconnected or described chip testing banner word for described chip fuse.
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| CN201410742834.XA CN104459519A (en) | 2014-12-05 | 2014-12-05 | Chip safety testing method and device |
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| CN201410742834.XA CN104459519A (en) | 2014-12-05 | 2014-12-05 | Chip safety testing method and device |
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| CN104931823A (en) * | 2015-06-08 | 2015-09-23 | 小米科技有限责任公司 | Electronic device test method and device |
| CN105045695A (en) * | 2015-08-17 | 2015-11-11 | 大唐微电子技术有限公司 | Method and system for protecting chips in process of entering test mode |
| CN105389224A (en) * | 2014-09-04 | 2016-03-09 | 国家电网公司 | Test protection method and device for safety chips |
| CN106443415A (en) * | 2016-11-03 | 2017-02-22 | 上海华虹集成电路有限责任公司 | Retesting method for integrated chip with storage unit |
| CN107271888A (en) * | 2017-07-31 | 2017-10-20 | 上海华力微电子有限公司 | A kind of method that single test chip realizes multiple IP chip testings |
| CN107783028A (en) * | 2017-10-16 | 2018-03-09 | 苏州国芯科技有限公司 | A kind of chip enters the control method and system of test pattern |
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| CN107783028A (en) * | 2017-10-16 | 2018-03-09 | 苏州国芯科技有限公司 | A kind of chip enters the control method and system of test pattern |
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