CN107271888A - A kind of method that single test chip realizes multiple IP chip testings - Google Patents
A kind of method that single test chip realizes multiple IP chip testings Download PDFInfo
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- CN107271888A CN107271888A CN201710640096.1A CN201710640096A CN107271888A CN 107271888 A CN107271888 A CN 107271888A CN 201710640096 A CN201710640096 A CN 201710640096A CN 107271888 A CN107271888 A CN 107271888A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The present invention proposes a kind of method that single test chip realizes multiple IP chip testings, comprises the following steps：The coordinate of the area and each pin of test chip is fixed according to position in MPW；By test chip, each pin connects different tested IP chips；Test evaluation is carried out to specified IP chips according to default order；After an IP chip testings evaluation is completed, connection is turned off to the pin that current IP chips are connected；Test evaluation is carried out to next IP chips specified according to default order.The present invention proposes a kind of method that single test chip realizes multiple IP chip testings, and flow is with evaluating area and probe card cost in cost and MPW productions in saving IP chip evaluations.
Description
Technical field
The present invention relates to test of semiconductor integrated circuit field, and more particularly to a kind of single test chip realizes multiple IP
The method of chip testing.
Background technology
Constantly lifted with the technology of integrated circuit, minimum design size is also constantly being reduced, unit area chip
On number of devices it is also more and more.Therefore in the IC design development phase, designer is passed through frequently with MPW
Multiple IC design with same process are exactly placed on same disk by (MultiProjectWafer, abbreviation MPW)
Upper flow, after flow, each design kind can obtain tens of chip samples, reality of this quantity for the stage of designing and developing
Test, test enough.Experimental expenses shares flow expense by all participation MPW project by area simultaneously, to reduce exploitation
Cost and development risk on new product, reduce threshold of the medium and small IC design enterprise in starting, reduce single experiment flow
The resource serious waste caused.
Existing IP is evaluated due in order to save design cost, often solidifying the area of test chip and PAD coordinates in MPW
And with this corresponding probe card.But it is due to that IP species is more, product iterations is more, therefore generally requires in a survey
Two or more IP are put into examination chip, flow are saved with evaluating cost.Therefore need to find a kind of method of testing, using single
Test chip realizes multiple IP tests.
The content of the invention
The present invention proposes a kind of method that single test chip realizes multiple IP chip testings, saves during IP chips are evaluated and flows
Piece is with evaluating area and probe card cost in cost and MPW productions.
In order to achieve the above object, the present invention proposes a kind of method that single test chip realizes multiple IP chip testings,
Comprise the following steps：
The coordinate of the area and each pin of test chip is fixed according to position in MPW；
By test chip, each pin connects different tested IP chips；
Test evaluation is carried out to specified IP chips according to default order；
After an IP chip testings evaluation is completed, connection is turned off to the pin that current IP chips are connected；
Test evaluation is carried out to next IP chips specified according to default order.
Further, it is attached between the IP chips and each pin by electrically programmable fuse.
Further, it is after an IP chip testings evaluation is completed, to current IP cores that the pin, which disconnects step,
The electrically programmable fuse of piece connection carries out programming operation.
Further, programming operation is to be released protection circuit by ESD, level is set low on power supply, in IP chips
High level is set in input channel, connection is blown to electrically programmable fuse.
Further, this method is by electricity consumption between the power supply and ground that need second of test evaluation and IP chips afterwards
Programmable fuse is attached.
Further, when the IP chips to second and afterwards carry out test evaluation, increase on the power supply of current IP chips
Pressure, the electrically programmable fuse between power supply and ground is blown, and current IP chips are activated beginning test evaluation.
Further, when carrying out test evaluation to specified IP chips according to default order, the power supply of other IP chips
Connect 0 level.
Multiple IP chips can be used only by the method that single test chip proposed by the present invention realizes multiple IP chip testings
One fixed test chip framework, therefore a probe card specified only is needed, take full advantage of the face in test chip
Product, is put into multiple tested IP chips in a test chip, different IP chips can public multiple I/O ports, and do not have mutually
Interference.The present invention can save IP chips evaluate in flow with evaluate cost and MPW production in area and probe card into
This.
Brief description of the drawings
The single test chip that Fig. 1 show present pre-ferred embodiments realizes the method flows of multiple IP chip testings
Figure.
The test chip structure that Fig. 2 show present pre-ferred embodiments realizes the schematic diagrames of 2 IP chip testings.
Fig. 3 show the TCH test channel and IP chip annexation schematic diagrames of present pre-ferred embodiments.
Embodiment
The embodiment of the present invention is provided below in conjunction with accompanying drawing, but the invention is not restricted to following embodiment.Root
According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is using very simple
The form of change and use non-accurately ratio, be only used for conveniently, lucidly aid in illustrating the embodiment of the present invention purpose.
Fig. 1 is refer to, the single test chip that Fig. 1 show present pre-ferred embodiments realizes multiple IP chip testings
Method flow diagram.The present invention proposes a kind of method that single test chip realizes multiple IP chip testings, comprises the following steps：
Step S100：The coordinate of the area and each pin of test chip is fixed according to position in MPW；
Step S200：By test chip, each pin connects different tested IP chips；
Step S300：Test evaluation is carried out to specified IP chips according to default order；
Step S400：After an IP chip testings evaluation is completed, company is turned off to the pin that current IP chips are connected
Connect；
Step S500：Test evaluation is carried out to next IP chips specified according to default order.
Fig. 2 is refer to again, and the test chip structure that Fig. 2 show present pre-ferred embodiments realizes 2 IP chip testings
Schematic diagram.Fig. 2 shows two IP chips of placement in a test chip of knowing clearly, and the different public identicals of IP chips is visited
Pin PAD.
According to present pre-ferred embodiments, it is attached between the IP chips and each pin by electrically programmable fuse.
EFuse is compared with older laser blown technology, and electron transfer (EM) characteristic can be for the much smaller fuse-wires structure of generation.EM
Fuse can be programmed on chip, whether in the probe of wafer stage or in a package.Using voltage on the piece of I/O circuits
(being usually 2.5V), 10 milliamperes of DC pulses for continuing 200 microseconds are just enough to program single fuse.
It is the electricity connected to current IP chips after an IP chip testings evaluation is completed that the pin, which disconnects step,
Programmable fuse carries out programming operation.Further, programming operation is to be released protection circuit by ESD, is set low on power supply
Level, sets high level in IP chip input channels, connection is blown to electrically programmable fuse.
This method will use electrically programmable fuse between the power supply and ground that need second of test evaluation and IP chips afterwards
It is attached.When IP chips to second and afterwards carry out test evaluation, added high pressure on the power supply of current IP chips, power supply with
Electrically programmable fuse between ground is blown, and current IP chips are activated beginning test evaluation.According to default order to specified
When IP chips carry out test evaluation, the power supply of other IP chips connects 0 level.
Fig. 3 is refer to, Fig. 3 show the TCH test channel and IP chip annexation schematic diagrames of present pre-ferred embodiments.
Fig. 3 shows a TCH test channel and the public connection figure of two IP chips, and first IP1 is tested, complete IP1 test after
Add 0V on IP1 VDD, TCH test channel adds high pressure, and IP2 VDD and IP2 GND OPEN, the first electrically programmable fuse 100 fuses, then
Test operation can be carried out to IP2.
In summary, the method that single test chip proposed by the present invention realizes multiple IP chip testings, to multiple IP cores
Piece can be only with a fixed test chip framework, therefore only needs a probe card specified, and takes full advantage of test
Area in chip, is put into multiple tested IP chips in a test chip, different IP chips can public multiple I/O ports,
And do not interfere with mutually.The present invention can save IP chips evaluate in flow with evaluate cost and MPW production in area with
And probe card cost.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.Skill belonging to of the invention
Has usually intellectual in art field, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Cause
This, the scope of protection of the present invention is defined by those of the claims.
Claims (7)
1. a kind of method that single test chip realizes multiple IP chip testings, it is characterised in that comprise the following steps：
The coordinate of the area and each pin of test chip is fixed according to position in MPW；
By test chip, each pin connects different tested IP chips；
Test evaluation is carried out to specified IP chips according to default order；
After an IP chip testings evaluation is completed, connection is turned off to the pin that current IP chips are connected；
Test evaluation is carried out to next IP chips specified according to default order.
2. the method that single test chip according to claim 1 realizes multiple IP chip testings, it is characterised in that described
It is attached between IP chips and each pin by electrically programmable fuse.
3. the method that single test chip according to claim 2 realizes multiple IP chip testings, it is characterised in that described
It is that after an IP chip testings evaluation is completed, the electrically programmable fuse that current IP chips are connected is carried out that pin, which disconnects step,
Programming is operated.
4. the method that single test chip according to claim 3 realizes multiple IP chip testings, it is characterised in that described
Programming operation is to be released protection circuit by ESD, and level is set low on power supply, high level is set in IP chip input channels,
Connection is blown to electrically programmable fuse.
5. the method that single test chip according to claim 2 realizes multiple IP chip testings, it is characterised in that the party
Method will be attached between the power supply and ground that need second of test evaluation and IP chips afterwards with electrically programmable fuse.
6. the method that single test chip according to claim 5 realizes multiple IP chip testings, it is characterised in that to
When two and IP chips afterwards carry out test evaluation, added high pressure on the power supply of current IP chips, the electricity volume between power supply and ground
Journey fuse is blown, and current IP chips are activated beginning test evaluation.
7. the method that single test chip according to claim 1 realizes multiple IP chip testings, it is characterised in that according to
When default order carries out test evaluation to specified IP chips, the power supply of other IP chips connects 0 level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710640096.1A CN107271888A (en) | 2017-07-31 | 2017-07-31 | A kind of method that single test chip realizes multiple IP chip testings |
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| CN201710640096.1A CN107271888A (en) | 2017-07-31 | 2017-07-31 | A kind of method that single test chip realizes multiple IP chip testings |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108398627A (en) * | 2018-02-06 | 2018-08-14 | 珠海市杰理科技股份有限公司 | Chip pin circuit, chip and chip detecting method |
| CN110967614A (en) * | 2018-09-28 | 2020-04-07 | 长鑫存储技术有限公司 | Chip testing method, chip testing equipment and chip |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030234659A1 (en) * | 2002-06-20 | 2003-12-25 | Promos Technologies | Electrical isolation between pins sharing the same tester channel |
| US20040257106A1 (en) * | 2003-06-23 | 2004-12-23 | Kang Tae Jin | Semiconductor device for reducing the number of probing pad used during wafer test and method for testing the same |
| CN1734761A (en) * | 2004-08-04 | 2006-02-15 | 台湾积体电路制造股份有限公司 | Fuse circuit and electrical fuse circuit with electrostatic discharge (ESD) protection |
| CN101061616A (en) * | 2004-06-03 | 2007-10-24 | 阿尔特拉公司 | Electrostatic discharge protection circuit |
| CN101196546A (en) * | 2006-12-04 | 2008-06-11 | 上海华虹Nec电子有限公司 | Method for different IP products executing burn-in test and test board used for it |
| CN101458296A (en) * | 2007-12-13 | 2009-06-17 | 上海华虹Nec电子有限公司 | Multi-product silicon wafer test method |
| CN101788644A (en) * | 2009-12-30 | 2010-07-28 | 北京龙芯中科技术服务中心有限公司 | Device and method for testing system-on-chip chip with multiple isomorphic IP cores |
| CN102880536A (en) * | 2012-09-07 | 2013-01-16 | 杭州中天微系统有限公司 | JTAG (joint test action group) debug method of multi-core processor |
| CN103579196A (en) * | 2012-07-27 | 2014-02-12 | 英飞凌科技股份有限公司 | Wafers and chips comprising test structures |
| CN104459519A (en) * | 2014-12-05 | 2015-03-25 | 大唐微电子技术有限公司 | Chip safety testing method and device |
| CN106887425A (en) * | 2015-12-16 | 2017-06-23 | 格罗方德半导体公司 | For the ESD-protection structure of electric fuse |
-
2017
- 2017-07-31 CN CN201710640096.1A patent/CN107271888A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030234659A1 (en) * | 2002-06-20 | 2003-12-25 | Promos Technologies | Electrical isolation between pins sharing the same tester channel |
| US20040257106A1 (en) * | 2003-06-23 | 2004-12-23 | Kang Tae Jin | Semiconductor device for reducing the number of probing pad used during wafer test and method for testing the same |
| CN101061616A (en) * | 2004-06-03 | 2007-10-24 | 阿尔特拉公司 | Electrostatic discharge protection circuit |
| CN1734761A (en) * | 2004-08-04 | 2006-02-15 | 台湾积体电路制造股份有限公司 | Fuse circuit and electrical fuse circuit with electrostatic discharge (ESD) protection |
| CN101196546A (en) * | 2006-12-04 | 2008-06-11 | 上海华虹Nec电子有限公司 | Method for different IP products executing burn-in test and test board used for it |
| CN101458296A (en) * | 2007-12-13 | 2009-06-17 | 上海华虹Nec电子有限公司 | Multi-product silicon wafer test method |
| CN101788644A (en) * | 2009-12-30 | 2010-07-28 | 北京龙芯中科技术服务中心有限公司 | Device and method for testing system-on-chip chip with multiple isomorphic IP cores |
| CN103579196A (en) * | 2012-07-27 | 2014-02-12 | 英飞凌科技股份有限公司 | Wafers and chips comprising test structures |
| CN102880536A (en) * | 2012-09-07 | 2013-01-16 | 杭州中天微系统有限公司 | JTAG (joint test action group) debug method of multi-core processor |
| CN104459519A (en) * | 2014-12-05 | 2015-03-25 | 大唐微电子技术有限公司 | Chip safety testing method and device |
| CN106887425A (en) * | 2015-12-16 | 2017-06-23 | 格罗方德半导体公司 | For the ESD-protection structure of electric fuse |
Non-Patent Citations (1)
| Title |
|---|
| 1.3 FPGA器件编程技术: "《Xilinx FPGA设计与实践教程》", 31 January 2012, 西安电子科技大学出版社 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108398627A (en) * | 2018-02-06 | 2018-08-14 | 珠海市杰理科技股份有限公司 | Chip pin circuit, chip and chip detecting method |
| CN110967614A (en) * | 2018-09-28 | 2020-04-07 | 长鑫存储技术有限公司 | Chip testing method, chip testing equipment and chip |
| CN110967614B (en) * | 2018-09-28 | 2021-09-24 | 长鑫存储技术有限公司 | Chip testing method, chip testing equipment and chip |
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