CN2558082Y - 堆栈式芯片尺寸封装结构 - Google Patents

堆栈式芯片尺寸封装结构 Download PDF

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CN2558082Y
CN2558082Y CN02233795.4U CN02233795U CN2558082Y CN 2558082 Y CN2558082 Y CN 2558082Y CN 02233795 U CN02233795 U CN 02233795U CN 2558082 Y CN2558082 Y CN 2558082Y
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chip
package structure
stacking
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彭镱良
吴凯强
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Advanced packaging and testing (Hongkong) Co.,Ltd.
Riyueguang Semiconductor Weihai Co ltd
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LIWEI SCIENCE AND TECHNOLOGY C
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本实用新型是一种堆栈式芯片尺寸封装结构，是于一基板上叠设一下芯片及一上芯片，该上下芯片各设有二排焊垫，且该二芯片上的焊垫是呈平行排列；在该上芯片悬空部分的下方且于该下芯片的侧边设置至少一假芯片，以作为焊垫打线的支撑。该假芯片与该下芯片之间并留设一空隙。故本实用新型是利用假芯片的设计，以解决芯片悬空打线造成的晶粒崩碎问题，因此可灵活调整上芯片的尺寸及方向配置，并可缩短基板上的走线长度，以增强电性功能。

Description

堆栈式芯片尺寸封装结构
技术领域
本实用新型涉及一种集成电路封装，特别是有关一种堆栈式芯片尺寸封装(stacked chip size/scale package，stacked CSP)的芯片堆栈结构。
背景技术
在集成电路封装中，堆栈式芯片尺寸封装或称为多芯片封装(multi-chip package，MCP)的芯片堆栈结构，如图1与图2所示，于一基板10上设置一下芯片12及一上芯片14，各界面间分别以粘着剂16、18粘着在一起，利用金线20自上芯片14与下芯片12上的焊垫22、24(Bonding Pad)连接到基板10上的接点26，该基板10下方则植设有数焊球28。
在传统技术中，下层芯片尺寸皆大于上层芯片尺寸，使得基板的布局受到限制；即使上层芯片尺寸大于下层芯片尺寸，如图3所示，为使基板走线路径最短，上芯片14与下芯片12的焊垫是在同一方向排列，且上芯片14仅在无焊垫的方向其尺寸可大于下面的芯片；但是焊垫30、32、34及36却因悬空而无法打线(Wire Bonding)，此乃因堆栈式芯片封装的芯片厚度都相当薄，因此悬空打线势必将造成晶粒崩碎(Die Crack)。而此问题使得现有芯片的设计无法广泛应用，有时也因基板布局的困难而无法将上芯片调整方向。
发明内容
本实用新型的主要是提供一种堆栈式芯片尺寸封装结构，以解决芯片悬空打线的晶粒崩碎问题。
本实用新型的另一目的，是在提供一种可灵活调整上芯片尺寸及设置方向的多层芯片尺寸封装结构。
本实用新型的再一目的，是在提供一种可缩短基板上的走线长度，以增强电性功能的封装结构。
本实用新型是这样实现的，一种堆栈式芯片尺寸封装结构，其特征在于包括：一下芯片，设置在一基板上；至少一上芯片，设于所述下芯片之上；至少一假芯片，设置在该上芯片悬空部分的下方且位于该下芯片的侧边的所述基板上，且该假芯片的厚度与该下芯片的厚度相当；复数焊垫，整齐排列于该上、下芯片露出的表面。
下面结合附图以具体实施例对本实用新型进行详细说明，以便更容易了解本实用新型的目的、技术内容、特点及其所达成的功效。
附图说明
图1为传统堆栈式芯片尺寸封装结构示意图；
图2为传统堆栈式芯片尺寸封装结构俯视图；
图3为传统芯片悬空打线示意图；
图4为本实用新型的最佳实施例。
附图标号说明：10基板；12下芯片；14上芯片；16粘着剂；18粘着剂；20金线；22焊垫；24焊垫；26接点；28焊球；30焊垫；32焊垫；34焊垫；36焊垫；40堆栈式芯片尺寸封装结构；42假芯片；44假芯片；46间隙。
具体实施方式
本实用新型是在上芯片悬空部分的下方设置一假芯片，作为焊垫打线时的支撑，以解决悬空打线造成的晶粒崩碎问题。
如图4所示，一堆栈式芯片尺寸封装结构40是于基板10上叠设一下芯片12及一上芯片14，各界面间利用粘着剂接合在一起，该粘着剂可为银胶。该上芯片14与该下芯片12各设有复数焊垫22、24，且该上芯片14沿无焊垫22的方向其尺寸是大于该下芯片12，因此该上芯片14相对于该下芯片12，其二侧区域是呈悬空状态。而该焊垫22、24整齐排列于该上芯片14与该下芯片12的两对边，使上芯片14的二排焊垫22是与该下芯片12的二排焊垫24平行。
为克服芯片悬空打线造成晶粒崩碎的问题，因此在该上芯片14的二侧悬空区域下方且位于该下芯片12的二侧的基板10上，各设置一假芯片42及44以作为打线的支撑，该假芯片42、44的厚度等于该下芯片12的厚度，且该假芯片42、44与该下芯片12的总尺寸大于该上芯片14的尺寸。该假芯片42、44与该下芯片12之间并留设一间隙46，作为减少热帐冷缩效应及为银胶溢胶预留空间，以增强封装体的可靠性。
其中，若该假芯片42、44与该下芯片12之间存有尺寸公差，则可藉由非导电胶或粘晶薄膜(Die Attach Film)的流动性与韧性做补偿，因此不会发生上芯片倾斜的问题。本实用新型除可应用于两层芯片的堆栈技术外，更可扩展至三层以上或多芯片组的堆栈封装。
本实用新型利用上述在上芯片悬空部分的下方设置至少一假芯片以作为打线的支撑，可避免悬空打线造成晶粒崩碎的问题。所以，本实用新型不但可彻底解决传统上芯片大于下芯片便无法打线的困扰及不便，并可灵活调整上芯片的尺寸以配合基板布局的需要，更可减少基板上的走线长度，以增强电性功能。
以上所述是藉由实施例说明本实用新型的特点，其目的在使本领域熟练技术人员了解本实用新型的内容并据以实施，而非限定本实用新型的范围。因此，凡其它未脱离本实用新型所揭示的精神所完成的等效修饰或修改，仍应包含在本实用新型的范围中。

Claims (5)

1.一种堆栈式芯片尺寸封装结构，其特征在于包括：
一下芯片，设置在一基板上；
至少一上芯片，设于所述下芯片之上；
至少一假芯片，设置在该上芯片悬空部分的下方且位于该下芯片的侧边的所述基板上，且该假芯片的厚度与该下芯片的厚度相当；以及
复数焊垫，整齐排列于该上、下芯片露出的表面。
2.如权利要求1所述的堆栈式芯片尺寸封装结构，其特征在于所述上芯片的焊垫与该下芯片的焊垫呈同一方向平行排列。
3.如权利要求1所述的堆栈式芯片尺寸封装结构，其特征在于所述假芯片与该下芯片之间设有一空隙。
4.如权利要求1所述的堆栈式芯片尺寸封装结构，其特征在于所述假芯片与该下芯片的总尺寸大于所述上芯片尺寸。
5.如权利要求1所述的堆栈式芯片尺寸封装结构，其特征在于所述上下芯片以一粘着剂接合在一起。
CN02233795.4U 2002-05-23 2002-05-23 堆栈式芯片尺寸封装结构 Expired - Lifetime CN2558082Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7777348B2 (en) 2006-12-27 2010-08-17 Kabushiki Kaisha Toshiba Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7777348B2 (en) 2006-12-27 2010-08-17 Kabushiki Kaisha Toshiba Semiconductor device
CN102214629A (zh) * 2006-12-27 2011-10-12 株式会社东芝 半导体装置和存储卡

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