CN2508397Y - 数组式凸块对凸块的封装结构 - Google Patents

数组式凸块对凸块的封装结构 Download PDF

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CN2508397Y
CN2508397Y CN 01278416 CN01278416U CN2508397Y CN 2508397 Y CN2508397 Y CN 2508397Y CN 01278416 CN01278416 CN 01278416 CN 01278416 U CN01278416 U CN 01278416U CN 2508397 Y CN2508397 Y CN 2508397Y
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integrated circuit
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张庆云
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Wintek Corp
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Wintek Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member

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Abstract

一种数组式凸块对凸块的封闭结构,包括:一集成电路芯片,其底部全断面的任意处以数组型态突伸若干耐高温高压的第一良导凸块,利用第一良导凸块与电路基板连结;一电路基板,其表面相对集成电路芯片的第一良导凸块突伸耐高温高压的第二良导凸块,利用前述集成电路芯片的第一良导凸块布设于芯片全断面任意处,以及电路基板的第二良导凸块的配合设计,可使电子组件体积缩小。

Description

数组式凸块对凸块的封装结构
技术领域
本设计有关于一种超微米的电子连结装置，特别是指一种数组式凸块对凸块的封装结构。
背景技术
请先参阅图1，公知集成电路芯片10所据以插设于电路基板12的插孔13的接脚11，于电路芯片10的下表面以最小间距为60μm环绕集成电路芯片10周缘排列设置；但由于接脚11设置于集成电路芯片10周缘，以及电路基板12的插孔13呈相对接脚11的环状排列的原因，造成集成电路芯片10以及电路基板13的面积无法缩小，使各式电路基板12以及集成电路芯片10在体积、重量方面皆无法达到“轻、薄、短、小”的现代产品需求，也造成材料成本的支出与浪费。
再则，为使集成电路芯片10得以固设于电路基板12，而于电路基板12上开设插孔13的设计，常造成电路基板12的损坏，或因插孔13过多，而疏漏开设一、二个插孔13的话，即造成集成电路芯片10无法插设，如此，除组装者自行钻孔外(造成组装者不便)，即是将电路基板12退回厂商，增加一道退(换)货手续，也是造成使用者的不便。
实用新型内容
本设计的目的在于提供一种数组式凸块对凸块的封闭结构，利用集成电路芯片底部的全部面积并使集成电路芯片的体积微米化，以突破现代电子产品的体积缩小化的瓶颈。
本设计的次一目的在于提供一种数组式凸块对凸块的封闭结构，精简电路基板的制作过程，有效地提高电路基板的精密度。
为实现上述目的，本设计提供的一种数组式凸块对凸块的封闭结构，其包括：
一集成电路芯片，其底部全断面的任意处以数组型态突设数个第一良导凸块；以及
一电路基板，其具有数个联结线路，该联结线路上面覆设一绝缘层，各联结线路分别与一第二良导凸块导通，各第二良导凸块露出于该绝缘覆层表面，并分别与该集成电路芯片上的各第一良导凸块相互接触，以连接该集成电路芯片与该电路基板。
其中该第一良导凸块与该第二良导凸块为一种耐高温高压的金属凸块结构。
其中该集成电路芯片与该电路基板间还夹布有一导电胶层，该导电胶层含有数个导电粒子，而该等导电粒子分别被夹布于该第一良导凸与该第二良导凸块之间。
其中该导电胶层可被加热或照射紫外线而加速固化。
附图说明
请参阅以下有关本设计的一较佳实施例的详细说明及其附图，将可进一步了解本设计的技术内容及其目的功效，有关该实施例的附图为：
图1为已知技术的集成电路芯片与电路基板的组设平面图，
图2为本设计的集成电路芯片平面图，
图3为本设计的电路基板平面图，
图4为图3中A部分的结构放大示意图，
图5为本设计的连结过程示意图；以及
图6为图5的连结完成示意图。
具体实施方式
请参阅图2至图6，本设计主要包括有：一集成电路芯片20；一电路基板30，供集成电路芯片20插设，该电路基板30由绝缘基材31构成，于绝缘基材31设置联结线路32；其中，前述集成电路芯片20的底部，可依集成电路芯片20内部电路设计，而于集成电路芯片20全断面的任意处以“数组型态”突伸若干耐高温高压的第一良导凸块21，该第一良导凸块21让集成电路芯片20内部的电路与任意电子组件构成导通状态；并利用第一良导凸块21供集成电路芯片20与电路基板30连结。
前述电路基板30的联结线路32以微机电(MEMS)制程直接制作于电路基板30的绝缘基材31表面。并自联结线路32表面突伸相对应于该集成电路芯片20上第一良导凸块21的第二良导凸块33，该第二良导凸块33可为一种耐高温高压的金属凸块结构，再于电路基板30的联结线路32上面覆设一绝缘层34，并让第二良导凸块33暴露出绝缘覆层34表面，如此即可由第二良导凸块33与第一良导凸块21相互接触，让电路基板30的联结线路32与集成电路芯片20构成导通状态。
如图5及图6所示，连结该集成电路芯片20与该电路基板30时，先于集成电路芯片20与电路基板30间夹布一层导电胶层40，该导电胶层40含有复数个导电粒子41，其后将集成电路芯片20的第一良导凸块21相对压固于电路基板30的第二良导凸块33上；并对导电胶层40加热或照射紫外线，使之固化，如此即让集成电路芯片20固定于电路基板30上，并让导电胶层40的导电粒子41被夹布于第一良导凸块21与第二良导凸块33的触着面，以提高第一良导凸块21与第二良导凸块33间的良导性能。
再者，该第一良导凸块21与第二良导凸块33的接触面也可涂布任意高熔点的金属或合金材料，可由高温熔融该高熔点金属或合金材料，再配合高压将第一良导凸块21压触于第二良导凸块33表面，由该高熔点金属或合金材料冷却固化，而同时将该第一良导凸块21与该第二良导凸块33相互固结。
又，该电路基板30也可由第二良导凸块33先与一良导接部(与该集成电路芯片20上的第一良导凸块21为等效结构)的接合底座连结，再以接合底座供任意具第一良导凸块21的集成电路芯片20插设，以利电子产品的相关组件升级替换。
本设计与已知的技术相比，具有下列优点：
1)已知技术的集成电路芯片的接脚突设于芯片周缘，而限于高脚数的接脚无处设置，故需将集成电路芯片保持一定面积，如此，除集成电路芯片底部面积平白耗占外，相对电路基板的面积也无法缩小，造成电子产品在体积及面积上无法缩小，而本设计乃将集成电路芯片的接脚化为第一良导凸块而视其内部电路设计，以“数组型态”突设于集成电路芯片底部全断面的预定处，如此，除确实利用集成电路芯片底部的全部面积外，也可使集成电路芯片的体积微米化，以突破现代电子产品体积缩小化的瓶颈。
2)已知技术的电路基板需钻孔以供集成电路芯片插设，而钻孔的过程中，极容易造成电路基板损坏，或是插孔漏钻，皆造成电路基板的品保不易。而本设计除以业界未曾应用的微机电(MEMS)制程，将联结线路直接制作于电路基板上外，还于联结线路预定处配合集成电路芯片的第一良导凸块直接突伸第二良导凸块，利用第二良导凸块供电路基板与任意集成电路芯片的连结，完全不破坏电路基板的结构体，也精密电路基板的制作过程，有效地提高电路基板的品保精密度。

Claims (3)

1、一种数组式凸块对凸块的封闭结构，其包括：
一集成电路芯片，其底部全断面的任意处以数组型态突设数个第一良导凸块；以及
一电路基板，其具有数个联结线路，该联结线路上面覆设一绝缘层，各联结线路分别与一第二良导凸块导通，各第二良导凸块露出于该绝缘覆层表面，并分别与该集成电路芯片上的各第一良导凸块相互接触。
2、如权利要求1所述的数组式凸块对凸块的封闭结构，其特征在于，其中该第一良导凸块与该第二良导凸块为一种耐高温高压的金属凸块结构。
3、如权利要求1所述的数组式凸块对凸块的封闭结构，其特征在于，其中该集成电路芯片与该电路基板间夹布有一良导胶层，该良导胶层含有数个良导粒子，而该等良导粒子分别被夹布于该第一良导凸块与该第二良良导凸块之间。
CN 01278416 2001-12-13 2001-12-13 数组式凸块对凸块的封装结构 Expired - Lifetime CN2508397Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1326432C (zh) * 2002-12-23 2007-07-11 矽统科技股份有限公司 无焊垫设计的高密度电路板及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1326432C (zh) * 2002-12-23 2007-07-11 矽统科技股份有限公司 无焊垫设计的高密度电路板及其制造方法

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