CN2458814Y - Full-bridge phase-shift drive - Google Patents

Abstract

The utility model relates to a full-bridge phase-shift driver, composed of an amplifier, a pulse width modulator, an or logic gate, two D triggers and four and logic gates. The input of the amplifier is connected with given input signals, the amplifier outputs feedback signals, and the output of the amplifier is connected with the input of an error amplifier of the pulse width modulator. The two paths of the output of the pulse width modulator are connected with the input of the or logic gate, the output of the or logic gate is connected with the clock end of the first trigger, and the output of the or logic gate is also connected with the clock end of the second trigger through an inverter. The two triggers are both connected to be the counting state, the four output of the two triggers are respectively connected with the input of one and logic gate, and the four and logic gates output four driving signals. Pulse starting time sequences can be strictly controlled, and the dead time can be precisely controlled.

Description

The full-bridge phase shifting driver

The utility model relates to a kind of full-bridge phase shifting drive circuit.

Extraordinary high-power communication power supply rapid dynamic response speed, adaptive capacity is strong, requires the pulse enable sequential strict to control; Because power output electric current big, power component is big, ask when requiring long dead band, and circuit should not disturbed again.Full-bridge phase shifting chip for driving UC3875, μ L4818 etc. commonly used are difficult for accomplishing.

The purpose of this utility model is to provide a kind of full-bridge phase shifting drive circuit, and its pulse enable sequential can strict be controlled, and its Dead Time can accurately be controlled.

For achieving the above object, the utility model adopts following solution:

A kind of full-bridge phase shifting driver, by amplifier, pulse width modulator or gate, two d type flip flops, four constitute with gate, wherein:

The input of amplifier connects given input signal and output feedback signal, the output of amplifier connects the input of the error amplifier of pulse width modulator, the output of the two-way of pulse width modulator connects or the input of gate, or the output of gate connects the clock end of first trigger, or the output of gate also connects the clock end of second trigger through inverter, two triggers all connect into count status, four outputs of two triggers connect an input with gate respectively, four with four drive signals of gate output.

Advantage of the present utility model: because the frequency of oscillation of PWM and the Dead Time of output signal can accurately be set by its external circuit, its Dead Time can accurately be controlled, so an ingenious pwm chip and the peripheral auxiliary circuits utilized just realized the full-bridge phase shifting function.

Describe in detail below in conjunction with drawings and Examples.

Fig. 1 is a circuit diagram of the present utility model;

Fig. 2 is the circuit waveform figure of Fig. 1;

Fig. 3 is the full-bridge phase shifting circuit.

See also Fig. 1.The utility model by amplifier N3, pulse width modulator N1 (model SG3525AN) or gate, two d type flip flop N2A and N2B, four constitute with gate N3A-N4B, or gate is made of two diode V1 and V2 that become common cathodes to connect.Wherein:

Given input signal and output feedback signal are relatively imported at the inverting input of amplifier N3.Resistance R 1, R2 and capacitor C 1 are set the frequency of oscillation of pulse width modulator N1 and the Dead Time of output signal, and the error amplifier of N1 is connected into the integrating circuit form, and C2 is its integrating capacitor.The output of amplifier N3 connects the input of the error amplifier of pulse width modulator N1; the output of the two-way of pulse width modulator N1 connects or the input of gate; or the output of gate connects the clock end of trigger N2A; also after V3 is anti-phase, connect the clock end of trigger N2B simultaneously; two triggers all connect into count status; their four outputs connect four inputs with gate respectively; two inputs in addition of each and gate all connect protection input signal and dead band setting signal, four with four drive signals of gate output.

Foregoing circuit is contained in the shell.During use, four signal input parts of the present utility model are connect given input, output feedback, protection input, dead band setting signal respectively, with the grid of V1-V4 in the full-bridge phase shifting circuit shown in four outputs difference of the present utility model map interlinking 3.

Operation principle of the present utility model is: utilize the output signal of pulse width modulator to transfer out four road required phase-shift pulse drive signals of full-bridge phase shifting circuit.Describe in detail below in conjunction with Fig. 1, Fig. 2:

In Fig. 2, solid line waveform is an initial waveform, and dotted line waveform is the phase shift waveform.When the error signal of output feedback and given input increases, the PWM waveform duty cycle of N1 output increases, as Fig. 2-I, K, through or the gate addition after, C point waveform is 2 waveform stack result of I, K, D point waveform then for C order anti-phase, the signal that C, D are ordered drives d type flip flop N2A and N2B respectively, and the N2A output waveform is E, F, and the N2B output waveform is G, H, E, F, G, H respectively through with gate N3A-N4B shaping after, obtain full-bridge phase shifting drive signal A, A-, B, B-.A, B high level were total to leader and dashed increase as can be seen from Fig. 2 this moment, and A-, B-high level leader altogether dash increase.

If when the error signal of output feedback and given input reduced, the phase shift process was with above-mentioned opposite.

Claims (1)

1. full-bridge phase shifting driver is characterized in that: it by amplifier, pulse width modulator or gate, two d type flip flops, four constitute with gate, wherein:

The input of amplifier connects given input signal and output feedback signal, the output of amplifier connects the input of the error amplifier of pulse width modulator, the output of the two-way of pulse width modulator connects or the input of gate, or the output of gate connects the clock end of first trigger, or the output of gate also connects the clock end of second trigger through inverter, two triggers all connect into count status, four outputs of two triggers connect an input with gate respectively, four with four drive signals of gate output.

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