CN103399610B - Primary feedback self-compensating sampling circuit - Google Patents
Primary feedback self-compensating sampling circuit Download PDFInfo
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- CN103399610B CN103399610B CN201310367087.1A CN201310367087A CN103399610B CN 103399610 B CN103399610 B CN 103399610B CN 201310367087 A CN201310367087 A CN 201310367087A CN 103399610 B CN103399610 B CN 103399610B
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Abstract
The invention discloses a primary feedback self-compensating sampling circuit which is applied to a primary feedback switching power supply, and comprises a pull-up current source, a pull-down current source, a first charge and discharge subcircuit, a second charge and discharge subcircuit, a clock pair generator and a sampling logic circuit, wherein the pull-up current source comprises a fixed current source and a controlled current source; the controlled current source detects a load of the primary feedback switching power supply, and adjusts a magnitude of output current according to the load; and the output current of the fixed current source and the output current of the controlled current source are summed to serve as output current of the pull-up current source. According to the primary feedback self-compensating sampling circuit, a sampling time point falls in a preset optimal sampling time period all the time, so that a sampling interval with a great sampling error is avoided, and a sampling result can be more accurate and can reflect a load change.
Description
Technical field
The invention belongs to Switching Power Supply design field, relate to the feedback switch power control circuit design of former limit, particularly a kind of former limit feedback auto-compensation sample circuit.
Background technology
The update of the demand powerful along with consumption electronic product and various electronic product, also more and more higher to the requirement of power module.Power module is generally functional module and provides constant voltage or constant electric current, to ensure the work that they are stable.
Anti exciting converter its transformer usual of former limit feedback technique is made up of three windings, is respectively former limit winding, winding is assisted on former limit and secondary limit winding.Among more existing former limit feedback techniques, necessary sampling and outputting voltage, thus control the length of PWM turn-off time.Owing to there is high pressure in former limit winding, and the switch of switching tube can introduce larger noise, need sample circuit can bear high pressure and strong noise interference, in other method, introduce former limit assists winding to go to detect output voltage, auxiliary winding can be powered in the feedback technique of former limit to control chip simultaneously, and key controls feedback error.Traditional former limit feedback can arrange the sampled point of a set time usually, and this sampling instant is generally arranged on the moment that former limit energy has just transferred to time limit, assists winding to sample to obtain output voltage signal in this moment to former limit.Because secondary limit electric current is now larger, larger pressure drop can be produced between coil-end and output terminal, therefore the feedback voltage now sampled and actual output voltage have very big error, and simultaneously due to traditional sampling vibrational power flow fixed sample point, sampled signal can not accurately reflected load change.
Along with the increase of load, the energy that secondary coil shifts to load increases, the required time namely demagnetizes time corresponding prolongation, demagnetization time variations makes original sampling time be arranged on to be not suitable for the time of sampling, such as previously mentioned, do not wish that the sampling time is arranged on the moment that former limit energy has just transferred to time limit, now sampling error is larger.
Summary of the invention
Fixing for overcoming point of existing former limit feedback sampling circuit sampling time, can not reflected load change, thus the technological deficiency causing sampling error large, the invention discloses a kind of former limit feedback auto-compensation sample circuit.
One of the present invention former limit feedback auto-compensation sample circuit, be applied to former limit feedback switch power supply, comprise pull-up current source, pull-down current source, the first discharge and recharge branch road, the second discharge and recharge branch road, clock is to generator and Sample Logic;
Described first discharge and recharge branch road and the second discharge and recharge branch road all comprise following technical characteristic:
Comprise charging capacitor, the charge switch of series connection and discharge switch, described charge switch is connected with pull-up current source, described discharge switch is connected with pull-down current source, and described charge switch is connected charging capacitor with the common port of discharge switch, and this common port is also connected with the input end of Sample Logic;
Described charge switch is connected the clock signal output terminal that generator exports with clock with the control end of discharge switch;
When described clock is operated in charged state to one of them of clock enabling signal two discharge and recharge branch roads that generator exports, another is operated in discharge condition;
Described Sample Logic detects the voltage on the charging capacitor of two discharge and recharge branch roads, and when any one this voltage arrives low level, exporting width is the square-wave signal of D, and D is the sampling time preset;
Described pull-up current source comprises fixed current source and controlled current source, described controlled current source detects the load of former limit feedback switch power supply, and increase with load and increase output current, as the output current in pull-up current source after the output current addition of described fixed current source and controlled current source.
Adopt foregoing circuit structure, sampling time point can be realized and follow load change and the function of movement.
Concrete, described controlled current source comprises operational transconductance amplifier, sampling hold circuit and reference voltage source, two input ends of described operational transconductance amplifier are connected with the output terminal of sampling hold circuit and reference voltage source respectively, the input end of described sampling hold circuit assists winding to be connected in voltage sample mode with the transformer of former limit feedback switch power supply, and the output terminal of described operational transconductance amplifier is as the output terminal of controlled current source.
Further, described transformer is assisted on winding and is in series with divider resistance, and described sampling hold circuit is sampled to the pressure drop on divider resistance.
Further, also comprise sampling amplifier, the output terminal of described sampling hold circuit is connected with the input end of operational transconductance amplifier by sampling amplifier.
Preferably, described clock is demagnetization time signal and inversion signal thereof to the clock pair signals that generator exports.Demagnetization time signal easily obtains in the control circuit of former limit feedback switch power supply, and meeting that demagnetization signal can be proper will be limited in the demagnetization time period in the sampling time, avoid the ringing condition of subsequent feedback end.
Preferably, the output current in described pull-down current source is greater than the output current in fixed current source.
Preferably, described D was 100 nanoseconds nanosecond to 400.
Adopt former limit of the present invention feedback auto-compensation sample circuit, voltage VEA is amplified in the load after sampling and compares with internal reference voltage, produces a linear-charging electric current changed with load, thus detection time point is then moved with load increase.Sampling time is put drop on all the time in the optimum sampling time section that presets, avoid the sampling interval that sampling error is large, make sampled result more accurately and can reflected load change.
Accompanying drawing explanation
Fig. 1 is typical former limit feedback flyback AC/DC circuit FB and pwm signal schematic diagram;
Fig. 2 is a kind of embodiment schematic diagram of former limit of the present invention feedback auto-compensation sample circuit;
Fig. 3 is the signal sequence schematic diagram of each circuit node in Fig. 2;
In figure, Reference numeral name is called: 1-Sample Logic 2-operational transconductance amplifier 3-fixed current source 4-clock is to generator 5-pull-down current source 6-edge triggered flip flop 7-and logical circuit.
Embodiment
Goal of the invention of the present invention is to provide a kind of circuit structure that the sample detecting time can be made to change with load condition change, and this circuit structure is applied particularly in the control of former limit feedback switch power supply.
For achieving the above object, former limit of the present invention feedback auto-compensation sample circuit, comprise pull-up current source, pull-down current source 5, first discharge and recharge branch road, the second discharge and recharge branch road, clock is to generator 4 and Sample Logic 1;
Described first discharge and recharge branch road and the second discharge and recharge branch road all comprise following technical characteristic:
Comprise charging capacitor, the charge switch of series connection and discharge switch, described charge switch is connected with pull-up current source, described discharge switch is connected with pull-down current source, and described charge switch is connected charging capacitor with the common port of discharge switch, and this common port is also connected with the input end of Sample Logic;
Described charge switch is connected the clock signal output terminal that generator exports with clock with the control end of discharge switch;
When described clock is operated in charged state to one of them of clock enabling signal two discharge and recharge branch roads that generator exports, another is operated in discharge condition;
Described Sample Logic 1 detects the voltage on the charging capacitor of two discharge and recharge branch roads, and when any one this voltage arrives low level, exporting width is the square-wave signal of D, and D is the sampling time preset;
Described pull-up current source comprises fixed current source 3 and controlled current source, described controlled current source detects the load of former limit feedback switch power supply, and according to the size of load regulation output current, as the output current in pull-up current source after the output current of described fixed current source and controlled current source is added.
Above-mentioned pull-up current source, pull-down current source, the first discharge and recharge branch road, the second discharge and recharge branch road, the object of clock to generator and Sample Logic produce the sampling time.
As Figure 1-3, in a certain switch periods T1, when pwm signal is low, the power tube controlling former limit feedback switch power supply turns off, first discharge and recharge branch road enters charged state, charge switch PMOS PM1 opens, discharge switch NMOS tube NM1 closes, the charging capacitor C1 of the first discharge and recharge branch road is charged, OUT1 point voltage rises from low level, rise time depends on that the control signal CP1 and CN2 that are exported generator by clock are to the switching time of PM1 and NM1, and in this cycle T 1, the high level that OUT1 point voltage rises is designated as V-PEAK.
While the first charging paths enters charged state, second charging paths enters discharge condition, clock is reverse to signal CP2 and CP1, CN1 and CN2 that generator exports, the charge switch PMOS PM2 of the second discharge and recharge branch road is closed, discharge switch NMOS tube NM2 opens, and the OUT2 point voltage of charging capacitor C2 drops to low level from high level.
Described Sample Logic detects the voltage on the charging capacitor of two discharge and recharge branch roads, when any one this voltage arrives low level, exporting width is the square-wave signal of D, when the OUT2 point voltage in Fig. 2 drops to low level from high level, Sample Logic captures this change procedure from high to low, and exporting width is that the square-wave signal of D is as sampled signal SAMPLER-2.
The next cycle T2 of T1 is discussed, still the pwm signal within the T2 cycle controls the switching tube blocking interval of former limit feedback switch power supply, second discharge and recharge branch road enters charged state, charge switch PMOS PM2 opens, discharge switch NMOS tube NM2 closes, charge to the charging capacitor C2 of the second discharge and recharge branch road, OUT2 point voltage rises from low level, and the rise time depends on that the control signal CP2 and CN1 that are exported generator by clock are to the switching time of PM2 and NM2.
Simultaneously, first charging paths enters discharge condition, clock makes the charge switch PMOS PM1 of the first discharge and recharge branch road close to signal CP1 and the CN2 that generator exports, and discharge switch NMOS tube NM1 opens, and the OUT1 point voltage of charging capacitor C1 drops to low level from high level.
When the OUT1 point voltage in Fig. 2 drops to low level from high level, Sample Logic captures this change procedure from high to low, and exporting width is that the square-wave signal of D is as sampled signal SAMPLER-1.
The signal that Sample Logic finally exports is the superposed signal of SAMPLER-1 and SAMLPER-2 two pulses.
Charge switch and the discharge switch of pull-up current source and pull-down current source and two discharge and recharge branch roads are connected, control charging current and discharge current, in the present invention, pull-up current source comprises fixed current source and controlled current source, described controlled current source detects the load of former limit feedback switch power supply, and according to the size of load regulation output current, as the output current in pull-up current source after the output current of described fixed current source and controlled current source is added.Namely load is heavier, and the output current of controlled current source is larger, and the output current in pull-up current source is increased.
In Fig. 3, the bold portion of each bar curve indicates the sequential chart of each signal in said process, and dotted portion is distinguished as with bold portion: what dotted portion characterized is load condition relative heavier time the sequential chart of each signal.
When load condition is heavier, controlled current source makes pull-up current increase, and the charging current of two discharge and recharge branch roads when charged state increases, and the high value reached after charging becomes large.As shown in Figure 3, OUT1-a, OUT1-b and OUT2-a, OUT2-b represent the curve of voltage OUT1, OUT2 on the charging capacitor under load weight state respectively, due to load down, charging current increases, high level after charging is increased, in discharge process, because discharge current is constant, low level after electric discharge is also constant, and therefore charging capacitor is increased to the time that low level is discharged by high level.
Sample Logic is converted into low level change node to charging capacitor from high level and catches and export sampling pulse SAMPLER-1 and SAMLPER-2, therefore when overtime discharge time of charging capacitor, as shown in Figure 3, the relative solid line of SAMPLER-1 with SAMLPER-2 curve that dotted portion characterizes, the time passes backward.Thus achieve and increase with load, sampling time point is put off backward, in like manner, utilizes foregoing circuit, can obtain reducing with load, sampling time point effect in advance.
The invention provides a kind of specific implementation of controlled current source, described controlled current source comprises operational transconductance amplifier 2, sampling hold circuit and reference voltage source, two input ends of described operational transconductance amplifier are connected with output terminal VEA and VREF of sampling hold circuit and reference voltage source respectively, the input end of described sampling hold circuit assists winding to be connected in voltage sample mode with the transformer of former limit feedback switch power supply, and the output terminal of described operational transconductance amplifier is as the output terminal of controlled current source.
Operational transconductance amplifier compares voltage VEA and the reference voltage V REF of sampling hold circuit output, and output current signal is as the output current of controlled current source, and the voltage difference of operational transconductance amplifier two input ends is larger, and output current is larger.
Above-mentioned voltage sample mode can be assist a series connection divider resistance on winding at transformer, and described sampling hold circuit is sampled to the pressure drop on divider resistance.Be such as an error amplifier by sampling hold circuit, two input ends are connected on divider resistance two ends respectively, and divider resistance both end voltage difference carries out amplifier.
The output voltage of sampling hold circuit is preserved owing to may adopt switching capacity mode, driving force is weak, therefore a sampling amplifier can be connected between the output terminal of sampling hold circuit and the input end of operational transconductance amplifier, the output signal of sampling hold circuit is amplified, not only driving force can be increased, and suitably can adjust signal proportion by sampling hold circuit, the voltage signal that the input end of operational transconductance amplifier is received can make operational transconductance amplifier be operated in preferably state.
The effect of Sample Logic catches the decline process of charging capacitor voltage and exports the sampling pulse of one fixed width, voltage drop process due to charging capacitor is actual to be one and to drop to low level process from high level, therefore Sample Logic can adopt edge triggered flip flop 6 and realize with logical circuit 7, when edge triggered flip flop captures the negative edge of charging capacitor, export a pulse signal, the width of this pulse signal is the width D of sampling pulse signal, the output of two edge triggered flip flops by with logical circuit 7 realize with computing after as sampling pulse signal.The width D of sampling pulse signal is generally taken at 100-400 nanosecond, and the time is short, can not fully sample, and the sampling time is oversize stable not only bad for sampled signal, and can not adapt to high-frequency work state.
The output current be preferably arranged to pull-down current and be greater than fixed current source in pull-up current source is arranged to the size of current in pull-up current source and pull-down current source, because the sampling time must be arranged in the power tube down periods, constantly may increase with load at pull-up current, high level on charging capacitor is constantly increased, when causing the high low level voltage difference of charging capacitor constantly to increase, therefore suitably discharge current is increased, be conducive to accelerating the velocity of discharge, the sampling time was dropped in the power tube down periods.The output current ratio in pull-down current and fixed current source can be arranged between 2-4 times, and scale-up factor is little, be then unfavorable for the change that the embodiment sampling time changes with load, follow low precision.Ratio is too large, and pull-down current is excessive, is changed limited the discharge time of charging capacitor, then adjustable extent diminishes the sampling time, is unfavorable for the accuracy requirement that the sampling time changes with load equally.
The effect of clock to generator is the charge and discharge switch of control two discharge and recharge branch roads, two branch roads are made alternately to be in charging and discharging state, clock preferably directly utilizes demagnetization time signal (TDEMG) and inversion signal thereof to generator to the clock signal produced, demagnetization time signal easily obtains in the control circuit of former limit feedback switch power supply, and demagnetization signal can will be limited in the demagnetization time period by meeting of appropriateness in the sampling time, avoid the ringing condition of follow-up feedback end as shown in Figure 1.
Adopt former limit of the present invention feedback auto-compensation sample circuit, voltage VEA is amplified in the load after sampling and compares with internal reference voltage, produces a linear-charging electric current changed with load, thus detection time point is then moved with load increase.Sampling time is put drop on all the time in the optimum sampling time section that presets, avoid the sampling interval that sampling error is large, make sampled result more accurately and can reflected load change.
Previously described is each preferred embodiment of the present invention, preferred implementation in each preferred embodiment is if not obviously contradictory or premised on a certain preferred implementation, each preferred implementation can stack combinations use arbitrarily, design parameter in described embodiment and embodiment is only the invention proof procedure in order to clear statement inventor, and be not used to limit scope of patent protection of the present invention, scope of patent protection of the present invention is still as the criterion with its claims, the equivalent structure change that every utilization instructions of the present invention and accompanying drawing content are done, in like manner all should be included in protection scope of the present invention.
Claims (7)
1. a former limit feedback auto-compensation sample circuit, be applied to former limit feedback switch power supply, comprise pull-up current source, pull-down current source (5), the first discharge and recharge branch road, the second discharge and recharge branch road, clock is to generator (4) and Sample Logic (1);
Described first discharge and recharge branch road and the second discharge and recharge branch road all comprise following technical characteristic:
Comprise charging capacitor, the charge switch of series connection and discharge switch, described charge switch is connected with pull-up current source, described discharge switch is connected with pull-down current source, and described charge switch is connected charging capacitor with the common port of discharge switch, and this common port is also connected with the input end of Sample Logic;
Described charge switch is connected the clock signal output terminal that generator exports with clock with the control end of discharge switch;
When described clock is operated in charged state to one of them of clock enabling signal two discharge and recharge branch roads that generator exports, another is operated in discharge condition;
Described Sample Logic detects the voltage on the charging capacitor of two discharge and recharge branch roads, and when any one this voltage arrives low level, exporting width is the square-wave signal of D, and D is the sampling time preset;
It is characterized in that, described pull-up current source comprises fixed current source (3) and controlled current source, described controlled current source detects the load of former limit feedback switch power supply, and increase with load and increase output current, as the output current in pull-up current source after the output current addition of described fixed current source (3) and controlled current source.
2. a kind of former limit as claimed in claim 1 feedback auto-compensation sample circuit, it is characterized in that, described controlled current source comprises operational transconductance amplifier (2), sampling hold circuit and reference voltage source, two input ends of described operational transconductance amplifier (2) are connected with the output terminal of sampling hold circuit and reference voltage source respectively, the input end of described sampling hold circuit assists winding to be connected in voltage sample mode with the transformer of former limit feedback switch power supply, and the output terminal of described operational transconductance amplifier is as the output terminal of controlled current source.
3. a kind of former limit as claimed in claim 2 feedback auto-compensation sample circuit, it is characterized in that, described transformer is assisted on winding and is in series with divider resistance, and described sampling hold circuit is sampled to the pressure drop on divider resistance.
4. a kind of former limit as claimed in claim 2 or claim 3 feedback auto-compensation sample circuit, it is characterized in that, also comprise sampling amplifier, the output terminal of described sampling hold circuit is connected with the input end of operational transconductance amplifier by sampling amplifier.
5. a kind of former limit as claimed in claim 1 feedback auto-compensation sample circuit, it is characterized in that, described clock is demagnetization time signal and inversion signal thereof to the clock pair signals that generator (4) exports.
6. a kind of former limit as claimed in claim 1 feedback auto-compensation sample circuit, it is characterized in that, the output current of described pull-down current source (5) is greater than the output current of fixed current source (3).
7. a kind of former limit as claimed in claim 1 feedback auto-compensation sample circuit, it is characterized in that, described D was 100 nanoseconds nanosecond to 400.
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| CN201310367087.1A CN103399610B (en) | 2013-08-22 | 2013-08-22 | Primary feedback self-compensating sampling circuit |
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| CN201310367087.1A CN103399610B (en) | 2013-08-22 | 2013-08-22 | Primary feedback self-compensating sampling circuit |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107370375B (en) * | 2017-07-19 | 2019-08-23 | 深圳芯智汇科技有限公司 | DC-DC conversion circuit current sample, current-sharing control method and circuit |
| CN111669028B (en) * | 2019-03-07 | 2022-06-21 | 比亚迪半导体股份有限公司 | Switching power supply and sampling and holding method and circuit applied to flyback switching power supply |
| CN111596251A (en) * | 2020-07-10 | 2020-08-28 | 陕西航空电气有限责任公司 | Broadband current transformer phase error measuring device and method |
| CN116827128B (en) * | 2023-08-30 | 2023-11-17 | 苏州锴威特半导体股份有限公司 | Sampling circuit of flyback converter with primary side feedback |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101645658B (en) * | 2009-05-27 | 2013-09-18 | 北京中星微电子有限公司 | Flyback power converter and loop control method thereof |
| CN102497107B (en) * | 2011-12-09 | 2015-04-01 | 上海新进半导体制造有限公司 | Switch power supply and controller of switch power supply |
| CN102237812B (en) * | 2010-04-26 | 2013-06-12 | 辉芒微电子（深圳）有限公司 | Primary side feedback (FB) switching power supply controller and switching power supply system |
| CN102685982A (en) * | 2012-04-10 | 2012-09-19 | 苏州聚元微电子有限公司 | Primary side feedback constant current control circuit |
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Address after: 610000 innovation center, No. 4, West core road, hi tech West District, Sichuan, Chengdu C341-343 Patentee after: Chengdu Qi Chen electronic Limited by Share Ltd Address before: 610000 innovation center, No. 4, West core road, hi tech West District, Sichuan, Chengdu C341-343 Patentee before: Chengdu Chip-Rail Microelectronic Co., Ltd. |