CN103399610A - Primary feedback self-compensating sampling circuit - Google Patents
Primary feedback self-compensating sampling circuit Download PDFInfo
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- CN103399610A CN103399610A CN2013103670871A CN201310367087A CN103399610A CN 103399610 A CN103399610 A CN 103399610A CN 2013103670871 A CN2013103670871 A CN 2013103670871A CN 201310367087 A CN201310367087 A CN 201310367087A CN 103399610 A CN103399610 A CN 103399610A
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Abstract
The invention discloses a primary feedback self-compensating sampling circuit which is applied to a primary feedback switching power supply, and comprises a pull-up current source, a pull-down current source, a first charge and discharge subcircuit, a second charge and discharge subcircuit, a clock pair generator and a sampling logic circuit, wherein the pull-up current source comprises a fixed current source and a controlled current source; the controlled current source detects a load of the primary feedback switching power supply, and adjusts a magnitude of output current according to the load; and the output current of the fixed current source and the output current of the controlled current source are summed to serve as output current of the pull-up current source. According to the primary feedback self-compensating sampling circuit, a sampling time point falls in a preset optimal sampling time period all the time, so that a sampling interval with a great sampling error is avoided, and a sampling result can be more accurate and can reflect a load change.
Description
Technical field
The invention belongs to the Switching Power Supply design field, relate to the feedback switch power control circuit design of former limit, particularly the auto-compensation sample circuit is fed back on a kind of former limit.
Background technology
Along with the powerful demand of consumption electronic product and the update of various electronic products, also more and more higher to the requirement of power module.Power module is generally functional module constant voltage or constant electric current is provided, with the work that guarantees that they are stable.
The anti exciting converter of former limit feedback technique its transformer usually is comprised of three windings, is respectively former limit winding, the auxiliary winding in former limit and inferior limit winding.Among more existing former limit feedback techniques, necessary sampling and outputting voltage, thereby the length of control PWM turn-off time.Owing to having high pressure on the winding of former limit, and the switch of switching tube can be introduced larger noise, need sample circuit can bear high pressure and strong noise interference, introduced the auxiliary winding in former limit and removed to detect output voltage in the other method, auxiliary winding can be to the control chip power supply in the feedback technique of former limit simultaneously, and key is to control feedback error.Traditional former limit feedback can arrange the sampled point of a set time usually, and this sampling instant generally is arranged on former limit energy and has just transferred to the moment on time limit, at this, constantly the auxiliary winding in former limit is sampled to obtain output voltage signal.Because inferior limit electric current at this moment is larger, can produce larger pressure drop between coil-end and output terminal, therefore the feedback voltage and the actual output voltage that sample this moment have very large error, and simultaneously because the traditional sampling structure arranges a fixed sample point, sampled signal accurately reflected load changes.
Increase along with load, the energy that secondary coil shifts to load increases, the corresponding prolongation of time of namely demagnetizing of needed time, the variation of demagnetization time makes original sampling time may be arranged on the time that is not suitable for sampling, for example as previously mentioned, do not wish that the sampling time is arranged on former limit energy and just transferred to the moment on time limit, this moment, sampling error was larger.
Summary of the invention
Fixing for overcoming existing former limit feedback sampling circuit sampling time point, can not reflected load change, thereby cause the large technological deficiency of sampling error, the invention discloses a kind of former limit feedback auto-compensation sample circuit.
A kind of former limit of the present invention feedback auto-compensation sample circuit, be applied to former limit feedback switch power supply, comprises the pull-up current source, the pull-down current source, and first discharges and recharges branch road, and second discharges and recharges branch road, and clock is to generator and sampling logical circuit;
Described first discharges and recharges branch road and second discharges and recharges branch road and all comprises following technical characterictic:
The charge switch and the discharge switch that comprise charging capacitor, series connection, described charge switch is connected with the pull-up current source, described discharge switch is connected with the pull-down current source, and described charge switch is connected common port and is connected charging capacitor with discharge switch, and this common port also is connected with the input end of sampling logical circuit;
Described charge switch is connected control end and clock the clock signal output terminal of generator output is connected with discharge switch;
Described clock two of the clock enabling signals of generator output are discharged and recharged branch road one of them while being operated in charged state, another is operated in discharge condition;
Described sampling logical circuit detects the voltage on two charging capacitors that discharge and recharge branch road, and when any one this voltage arrived low level, the output width was the square-wave signal of D, and D is the predefined sampling time;
Described pull-up current source comprises fixed current source and controlled current source, described controlled current source detects the load of former limit feedback switch power supply, and increase output current with load, after the output current addition of described fixed current source and controlled current source as the output current in pull-up current source.
Adopt the foregoing circuit structure, can realize that the sampling time point follows load variations and mobile function.
Concrete, described controlled current source comprises operational transconductance amplifier, sampling hold circuit and reference voltage source, two input ends of described operational transconductance amplifier are connected respectively output terminal and are connected with reference voltage source with sampling hold circuit, the input end of described sampling hold circuit is connected in the voltage sample mode with the auxiliary winding of the transformer of former limit feedback switch power supply, and the output terminal of described operational transconductance amplifier is as the output terminal of controlled current source.
Further, be in series with divider resistance on the auxiliary winding of described transformer, described sampling hold circuit is sampled to the pressure drop on divider resistance.
Further, also comprise sampling amplifier, the output terminal of described sampling hold circuit is connected input end and is connected with operational transconductance amplifier by sampling amplifier.
Preferably, described clock is demagnetization time signal and inversion signal thereof to the clock of generator output to signal.The demagnetization time signal easily obtains in the control circuit of former limit feedback switch power supply, and satisfied being limited in the sampling time in the demagnetization time period that the demagnetization signal can be proper, avoids the ringing condition of subsequent feedback end.
Preferably, the output current in described pull-down current source is greater than the output current in fixed current source.
Preferably, described D was 100 nanoseconds nanosecond to 400.
Adopt former limit of the present invention to feed back the auto-compensation sample circuit, the amplification voltage VEA of the load after sampling and internal reference voltage are compared, produce a linear-charging electric current that changes with load, thereby put detection time, with the load increase, then move.Sampling time point is dropped in predefined optimum sampling time section all the time, avoided the large sampling interval of sampling error, make sampled result more accurate and can reflected load change.
Description of drawings
Fig. 1 is the anti-AC/DC circuit FB of swashing of typical former limit feedback and pwm signal schematic diagram;
Fig. 2 is a kind of embodiment schematic diagram of former limit of the present invention feedback auto-compensation sample circuit;
Fig. 3 is the signal sequence schematic diagram of each circuit node in Fig. 2;
In figure, the Reference numeral name is called: 1-sampling logical circuit 2-operational transconductance amplifier 3-fixed current source 4-clock is to generator 5-pull-down current source 6-edge triggered flip flop 7-and logical circuit.
Embodiment
Goal of the invention of the present invention is to provide a kind of can make the sample detecting time change the circuit structure that changes with load condition, and this circuit structure specifically is applied in the control of former limit feedback switch power supply.
For achieving the above object, former limit of the present invention feedback auto-compensation sample circuit, comprise the pull-up current source, and pull-down current source 5, the first discharges and recharges branch road, and second discharges and recharges branch road, and clock is to generator 4 and sampling logical circuit 1;
Described first discharges and recharges branch road and second discharges and recharges branch road and all comprises following technical characterictic:
The charge switch and the discharge switch that comprise charging capacitor, series connection, described charge switch is connected with the pull-up current source, described discharge switch is connected with the pull-down current source, and described charge switch is connected common port and is connected charging capacitor with discharge switch, and this common port also is connected with the input end of sampling logical circuit;
Described charge switch is connected control end and clock the clock signal output terminal of generator output is connected with discharge switch;
Described clock two of the clock enabling signals of generator output are discharged and recharged branch road one of them while being operated in charged state, another is operated in discharge condition;
The voltage that 1 pair two of described sampling logical circuits discharge and recharge on the charging capacitor of branch road detects, and when any one this voltage arrived low level, the output width was the square-wave signal of D, and D is the predefined sampling time;
Described pull-up current source comprises fixed current source 3 and controlled current source, described controlled current source detects the load of former limit feedback switch power supply, and according to the size of load regulation output current, after the output current addition of described fixed current source and controlled current source as the output current in pull-up current source.
Above-mentioned pull-up current source, pull-down current source, first discharge and recharge branch road, second, and to discharge and recharge branch road, clock be to produce the sampling time to the purpose of generator and sampling logical circuit.
As Figure 1-3, in a certain switch periods T1, when pwm signal is low, the power tube of controlling former limit feedback switch power supply turn-offs, first discharges and recharges branch road enters charged state, charge switch PMOS pipe PM1 opens, discharge switch NMOS pipe NM1 closes, the first charging capacitor C1 that discharges and recharges branch road is charged, the OUT1 point voltage rises from low level, rise time depends on that by clock to the control signal CP1 of generator output and CN2 switching time to PM1 and NM1, in this period T 1, the high level that the OUT1 point voltage rises is designated as V-PEAK.
When the first charging paths enters charged state, the second charging paths enters discharge condition, clock is reverse to the signal CP2 of generator output and CP1, CN1 and CN2, the second charge switch PMOS pipe PM2 that discharges and recharges branch road is closed, discharge switch NMOS pipe NM2 opens, and the OUT2 point voltage of charging capacitor C2 drops to low level from high level.
Described sampling logical circuit detects the voltage on two charging capacitors that discharge and recharge branch road, when any one this voltage arrives low level, the output width is the square-wave signal of D, when the OUT2 point voltage in Fig. 2 drops to low level from high level, the sampling logical circuit captures this change procedure from high to low, and the output width is that the square-wave signal of D is as sampled signal SAMPLER-2.
The next cycle T2 of T1 is discussed, still the pwm signal in the cycle is controlled the switching tube blocking interval of former limit feedback switch power supply at T2, second discharges and recharges branch road enters charged state, charge switch PMOS pipe PM2 opens, discharge switch NMOS pipe NM2 closes, to the second charging capacitor C2 charging that discharges and recharges branch road, the OUT2 point voltage rises from low level, and the rise time was depended on by clock the control signal CP2 of generator output and CN1 switching time to PM2 and NM2.
Simultaneously, the first charging paths enters discharge condition, clock is closed with the charge switch PMOS pipe PM1 that CN2 first discharges and recharges branch road the signal CP1 of generator output, discharge switch NMOS pipe NM1 unlatching, and the OUT1 point voltage of charging capacitor C1 drops to low level from high level.
When the OUT2 point voltage in Fig. 2 dropped to low level from high level, the sampling logical circuit captured this change procedure from high to low, and the output width is that the square-wave signal of D is as sampled signal SAMPLER-2.
The signal of the final output of sampling logical circuit is the superposed signal of SAMPLER-1 and two pulses of SAMLPER-2.
The pull-up current source is connected with discharge switch with two charge switchs that discharge and recharge branch road with the pull-down current source, control charging current and discharge current, in the present invention, the pull-up current source comprises fixed current source and controlled current source, described controlled current source detects the load of former limit feedback switch power supply, and according to the size of load regulation output current, after the output current addition of described fixed current source and controlled current source as the output current in pull-up current source.Be that load is heavier, the output current of controlled current source is larger, and the output current in pull-up current source is increased.
In Fig. 3, the solid line of each curve is partly expressed the sequential chart of each signal in said process, and the difference of dotted portion and solid line part is: dotted portion characterizes is the sequential chart of relative each signal when heavier of load condition.
When load condition was heavier, controlled current source increased pull-up current, and two discharge and recharge the charging current increase of branch road when charged state, and it is large that the high value that reaches after charging becomes.As shown in Figure 3, OUT1-a, OUT1-b and OUT2-a, OUT2-b represent respectively the voltage OUT1 on charging capacitor under load weight state, the curve of OUT2, because load increases the weight of, charging current increases, high level after charging is increased, in discharge process, because discharge current is constant, low level after discharge is also constant, so charging capacitor was increased by the time of high level to the low level discharge.
The sampling logical circuit is converted into low level variation node to charging capacitor from high level and catches and export sampling pulse SAMPLER-1 and SAMLPER-2, therefore work as overtime discharge time of charging capacitor, as shown in Figure 3, the SAMPLER-1 solid line relative to the SAMLPER-2 curve that dotted portion characterizes, the time passes backward.Realized thus increasing with load, the sampling time point is put off backward, in like manner, utilizes foregoing circuit, can obtain reducing with load sampling time point effect in advance.
The invention provides a kind of specific implementation of controlled current source, described controlled current source comprises operational transconductance amplifier 2, sampling hold circuit and reference voltage source, two input ends of described operational transconductance amplifier are connected respectively output terminal VEA and are connected with VREF with reference voltage source with sampling hold circuit, the input end of described sampling hold circuit is connected in the voltage sample mode with the auxiliary winding of the transformer of former limit feedback switch power supply, and the output terminal of described operational transconductance amplifier is as the output terminal of controlled current source.
Operational transconductance amplifier is voltage VEA and the reference voltage V REF of sampling hold circuit output relatively, and output current signal is as the output current of controlled current source, and the voltage difference of two input ends of operational transconductance amplifier is larger, and output current is larger.
Above-mentioned voltage sample mode can be divider resistance of series connection on the auxiliary winding of transformer, and described sampling hold circuit is sampled to the pressure drop on divider resistance.With sampling hold circuit, be for example an error amplifier, two input ends are connected on respectively the divider resistance two ends, the poor amplifier that carries out of divider resistance both end voltage.
The output voltage of sampling hold circuit is owing to may adopting the switching capacity mode to preserve, a little less than driving force, therefore can connect a sampling amplifier between the input end of the output terminal of sampling hold circuit and operational transconductance amplifier, output signal to sampling hold circuit is amplified, not only can increase driving force, and can suitably adjust signal proportion by sampling hold circuit, make the voltage signal that the input end of operational transconductance amplifier receives can make operational transconductance amplifier be operated in better state.
the effect of sampling logical circuit is the decline process of charging capacitor voltage to be caught and exports the sampling pulse of certain width, be one because the voltage drop process of charging capacitor is actual and drop to low level process from high level, therefore the logical circuit of sampling can adopt edge triggered flip flop 6 and with logical circuit 7, realize, when edge triggered flip flop captures the negative edge of charging capacitor, export a pulse signal, the width of this pulse signal is the width D of sampling pulse signal, the output of two edge triggered flip flops by with logical circuit 7 realize with computing after as sampling pulse signal.The width D of sampling pulse signal generally is taken at 100-400 nanosecond, and the time is short can not fully sample, and the sampling time is oversize stable not only bad for sampled signal, and can not adapt to the high-frequency work state.
The size of current in pull-up current source and pull-down current source is arranged and preferably is arranged to the output current of pull-down current greater than fixed current source in the pull-up current source, because the sampling time must be arranged on power tube in the down periods, may constantly increase with load at pull-up current, high level on charging capacitor is constantly increased, cause in the continuous situation about increasing of high-low level voltage difference of charging capacitor, therefore suitably increase discharge current, be conducive to accelerate the velocity of discharge, make the sampling time drop on power tube in the down periods.The output current ratio in pull-down current and fixed current source can be arranged between 2-4 times, and scale-up factor is little, is unfavorable for embodying the variation of sampling time with load variations, follows low precision.Ratio is too large, and pull-down current is excessive, makes to change discharge time of charging capacitor limitedly, and adjustable extent diminishes the sampling time, is unfavorable for equally the accuracy requirement of sampling time with load variations.
Clock is to control two charge and discharge switchs that discharge and recharge branch road to the effect of generator, make two branch roads alternately be in the charging and discharging state, clock preferably directly utilizes demagnetization time signal (TDEMG) and inversion signal thereof to generator to the clock signal that produces, the demagnetization time signal easily obtains in the control circuit of former limit feedback switch power supply, and the demagnetization signal can will be limited in the demagnetization time period by meeting of appropriateness in the sampling time, avoid the ringing condition of follow-up feedback end as shown in Figure 1.
Adopt former limit of the present invention to feed back the auto-compensation sample circuit, the amplification voltage VEA of the load after sampling and internal reference voltage are compared, produce a linear-charging electric current that changes with load, thereby put detection time, with the load increase, then move.Sampling time point is dropped in predefined optimum sampling time section all the time, avoided the large sampling interval of sampling error, make sampled result more accurate and can reflected load change.
previously described is each preferred embodiment of the present invention, preferred implementation in each preferred embodiment is if not obviously contradictory or take a certain preferred implementation as prerequisite, each preferred implementation stack combinations is arbitrarily used, design parameter in described embodiment and embodiment is only the invention proof procedure for clear statement inventor, not in order to limit scope of patent protection of the present invention, scope of patent protection of the present invention still is as the criterion with its claims, the equivalent structure that every utilization instructions of the present invention and accompanying drawing content are done changes, in like manner all should be included in protection scope of the present invention.
Claims (7)
1. a former limit feedback auto-compensation sample circuit, be applied to former limit feedback switch power supply, comprises the pull-up current source, and pull-down current source (5), first discharges and recharges branch road, and second discharges and recharges branch road, and clock is to generator (4) and sampling logical circuit (1);
Described first discharges and recharges branch road and second discharges and recharges branch road and all comprises following technical characterictic:
The charge switch and the discharge switch that comprise charging capacitor, series connection, described charge switch is connected with the pull-up current source, described discharge switch is connected with the pull-down current source, and described charge switch is connected common port and is connected charging capacitor with discharge switch, and this common port also is connected with the input end of sampling logical circuit;
Described charge switch is connected control end and clock the clock signal output terminal of generator output is connected with discharge switch;
Described clock two of the clock enabling signals of generator output are discharged and recharged branch road one of them while being operated in charged state, another is operated in discharge condition;
Described sampling logical circuit detects the voltage on two charging capacitors that discharge and recharge branch road, and when any one this voltage arrived low level, the output width was the square-wave signal of D, and D is the predefined sampling time;
It is characterized in that, described pull-up current source comprises fixed current source (3) and controlled current source, described controlled current source detects the load of former limit feedback switch power supply, and increase output current with load, after the output current addition of described fixed current source (3) and controlled current source as the output current in pull-up current source.
2. the auto-compensation sample circuit is fed back on a kind of former limit as claimed in claim 1, it is characterized in that, described controlled current source comprises operational transconductance amplifier (2), sampling hold circuit and reference voltage source, two input ends of described operational transconductance amplifier (2) are connected respectively output terminal and are connected with reference voltage source with sampling hold circuit, the input end of described sampling hold circuit is connected in the voltage sample mode with the auxiliary winding of the transformer of former limit feedback switch power supply, and the output terminal of described operational transconductance amplifier is as the output terminal of controlled current source.
3. the auto-compensation sample circuit is fed back on a kind of former limit as claimed in claim 2, it is characterized in that, is in series with divider resistance on the auxiliary winding of described transformer, and described sampling hold circuit is sampled to the pressure drop on divider resistance.
4. a kind of former limit feedback auto-compensation sample circuit as claimed in claim 2 or claim 3, is characterized in that, also comprises sampling amplifier, and the output terminal of described sampling hold circuit is connected input end and is connected with operational transconductance amplifier by sampling amplifier.
5. the auto-compensation sample circuit is fed back on a kind of former limit as claimed in claim 1, it is characterized in that, described clock is demagnetization time signal and inversion signal thereof to the clock of generator (4) output to signal.
6. the auto-compensation sample circuit is fed back on a kind of former limit as claimed in claim 1, it is characterized in that, the output current in described pull-down current source (5) is greater than the output current of fixed current source (3).
7. the auto-compensation sample circuit is fed back on a kind of former limit as claimed in claim 1, it is characterized in that, described D was 100 nanoseconds nanosecond to 400.
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| CN201310367087.1A CN103399610B (en) | 2013-08-22 | 2013-08-22 | Primary feedback self-compensating sampling circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107370375A (en) * | 2017-07-19 | 2017-11-21 | 深圳芯智汇科技有限公司 | DC DC translation circuits current sample, current-sharing control method and circuit |
| CN111596251A (en) * | 2020-07-10 | 2020-08-28 | 陕西航空电气有限责任公司 | Broadband current transformer phase error measuring device and method |
| CN111669028A (en) * | 2019-03-07 | 2020-09-15 | 比亚迪股份有限公司 | Switching power supply and sampling and holding method and circuit applied to flyback switching power supply |
| CN116827128A (en) * | 2023-08-30 | 2023-09-29 | 苏州锴威特半导体股份有限公司 | Sampling circuit of flyback converter with primary side feedback |
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| CN102497107A (en) * | 2011-12-09 | 2012-06-13 | 上海新进半导体制造有限公司 | Switch power supply and control circuit of switch power supply |
| CN102685982A (en) * | 2012-04-10 | 2012-09-19 | 苏州聚元微电子有限公司 | Primary side feedback constant current control circuit |
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| US20100302822A1 (en) * | 2009-05-27 | 2010-12-02 | Vimicro Corporation | Flyback Power converters |
| CN102237812A (en) * | 2010-04-26 | 2011-11-09 | 辉芒微电子（深圳）有限公司 | Primary side feedback (FB) switching power supply controller and switching power supply system |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107370375A (en) * | 2017-07-19 | 2017-11-21 | 深圳芯智汇科技有限公司 | DC DC translation circuits current sample, current-sharing control method and circuit |
| CN107370375B (en) * | 2017-07-19 | 2019-08-23 | 深圳芯智汇科技有限公司 | DC-DC conversion circuit current sample, current-sharing control method and circuit |
| CN111669028A (en) * | 2019-03-07 | 2020-09-15 | 比亚迪股份有限公司 | Switching power supply and sampling and holding method and circuit applied to flyback switching power supply |
| CN111596251A (en) * | 2020-07-10 | 2020-08-28 | 陕西航空电气有限责任公司 | Broadband current transformer phase error measuring device and method |
| CN116827128A (en) * | 2023-08-30 | 2023-09-29 | 苏州锴威特半导体股份有限公司 | Sampling circuit of flyback converter with primary side feedback |
| CN116827128B (en) * | 2023-08-30 | 2023-11-17 | 苏州锴威特半导体股份有限公司 | Sampling circuit of flyback converter with primary side feedback |
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Address after: 610000 innovation center, No. 4, West core road, hi tech West District, Sichuan, Chengdu C341-343 Patentee after: Chengdu Qi Chen electronic Limited by Share Ltd Address before: 610000 innovation center, No. 4, West core road, hi tech West District, Sichuan, Chengdu C341-343 Patentee before: Chengdu Chip-Rail Microelectronic Co., Ltd. |