TWI826090B - Power converter and control method thereof - Google Patents

Abstract

A power converter includes first to fourth switches, a flying capacitor, an inductor, an output capacitor and a control circuit. The first to fourth switches are coupled in cascode and in sequence. The first switch is further used to receive an input voltage, and the fourth switch is further coupled to a ground terminal. The flying capacitor is coupled across the second switch and the third switch, the inductor is coupled to the second switch, the third switch and the output capacitor. The output capacitor is used to output an output voltage. In a non-regulated mode, the control circuit is used to switch the first to fourth switches according to a resonant frequency. In a regulated mode, the control circuit is used to switch the first to fourth switches according to a regulated frequency exceeding the resonant frequency. When the flying capacitor is coupled to the inductor, the flying capacitor and the inductor can form a resonant circuit having the resonant frequency.

Description

Power converter and control method thereof

The present invention relates to electric energy conversion, in particular to a power converter and its control method.

The resonant switched-capacitor converter (RSCC) is a power converter that produces no or only a small amount of power consumption when transmitting power. It is commonly used in mobile electronic devices such as mobile phones and notebook computers. Used to provide power.

Resonant switched capacitor converters convert input voltage to output voltage with a fixed conversion ratio. When the input voltage is too large, the resonant switched capacitor converter still produces an excessive output voltage with a fixed conversion ratio, causing damage to the electronic device. When the input voltage is insufficient, the output voltage generated by the resonant switched capacitor converter with a fixed conversion ratio will be insufficient, resulting in low circuit efficiency.

An embodiment of the present invention provides a power converter, which includes a first switch, a second switch, a third switch, a fourth switch, a flying capacitor, an inductor, an output capacitor and a control circuit. The first switch includes a control terminal, a first terminal for receiving the input voltage, and a second terminal. The second switch includes a control terminal and a first terminal coupled to the second terminal and the second terminal of the first switch. The third switch includes a control terminal and a first terminal coupled to the second terminal and the second terminal of the second switch. The fourth switch includes a control terminal, a first terminal coupled to the second terminal of the third switch, and a second terminal coupled to the ground terminal. The flying capacitor includes a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to the second terminal of the third switch. The inductor includes a first terminal coupled to the second terminal of the second switch and the second terminal. The output capacitor includes a first terminal coupled to the second terminal of the inductor, used to output the output voltage, and the second terminal is coupled to the ground terminal. The control circuit is coupled to the first end of the first switch, the control end of the first switch, the control end of the second switch, the control end of the third switch and the control end of the fourth switch. In the non-adjustment mode, the control circuit is used to switch the first switch, the second switch, the third switch and the fourth switch according to the resonant frequency, and in the adjustment mode, the control circuit is used to switch the first switch according to the adjustment frequency exceeding the resonant frequency. switch, second switch, third switch and fourth switch. When the flying capacitor is coupled to the inductor, the flying capacitor and the inductor form a resonant circuit with a resonant frequency.

An embodiment of the present invention further provides a control method for a power converter. The power converter includes a first switch, a second switch, a third switch, a fourth switch, a flying capacitor, an inductor, an output capacitor and a control circuit. The first switch includes a control terminal, a first terminal for receiving the input voltage, and a second terminal. The second switch includes a control terminal and a first terminal coupled to the second terminal and the second terminal of the first switch. The third switch includes a control terminal and a first terminal coupled to the second terminal and the second terminal of the second switch. The fourth switch includes a control terminal, a first terminal coupled to the second terminal of the third switch, and a second terminal coupled to the ground terminal. The flying capacitor includes a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to the second terminal of the third switch. The inductor includes a first terminal coupled to the second terminal of the second switch and the second terminal. The output capacitor includes a first terminal coupled to the second terminal of the inductor for outputting the output voltage, and a second terminal coupled to the ground terminal. The control circuit is coupled to the first end of the first switch, the control end of the first switch, the control end of the second switch, the control end of the third switch and the control end of the fourth switch. The control method includes: in the non-regulation mode, the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to the resonant frequency; and in the regulation mode, the control circuit switches the first switch according to the regulation frequency exceeding the resonant frequency. , the second switch, the third switch and the fourth switch. When the flying capacitor is coupled to the inductor, the flying capacitor and the inductor form a resonant circuit with a resonant frequency. When the flying capacitor is coupled to the inductor, the flying capacitor and the inductor form a resonant circuit with a resonant frequency.

1: Power converter

10,20,30,40,120: switch

50:Flying Capacitor

60:Inductor

70: Output capacitor

800:Control circuit

801: Signal generation circuit

803: Status detection circuit

804: Closed loop circuit

805,806,807,808: Phase circuit

80 to 83: Buffer

84,85,86,88,89,263,315,318,415:OR gate

111:Transistor

112:Current source

113 and 152: Capacitor

150: Error amplifier

155,210,220: Comparator

250:Zero Cross Detector

260,320,343,420,443: flip-flop

96 to 98,261,267,311,313,411: reverser

223,265,330,345,430,445: Pulse generator

300:Start circuit

90 to 95,225,310,312,316,317,321,322,341,410,412,421,422,441: and gate

110,325,425: NOR gate

342,442:Non-and gate

200:Control method

S202 and S204: steps

CLP: closed loop signal

COMP: error amplification signal

IL: inductor current

Imax: maximum value

Imin: minimum value

MODE: mode signal

P1,P2,PA,PB: phase signal

Ph1, Ph2: stage

Pz1 to Pz3, Pfb1, Pfb2: pulse wave

RAMP: ramp signal

S1 to S4: switch signal

SDM: degaussing signal

Son: starting signal

SP: cutoff signal

SZ: zero cross signal

t1 to r9: time

T1 to T4: time period

TG1, TG2, TGA, TGB: trigger signal

V-: negative voltage

Vcc: supply voltage

Vin: input voltage

VH: high voltage

VL: low voltage

Vo: output voltage

VR: reference voltage

VT: degaussing reference voltage

Vx: switching voltage

GND: ground voltage

ZM: control signal

Figure 1 is a schematic circuit diagram of a power converter in an embodiment of the present invention.

Figure 2 is a flow chart of the control method of the power converter in Figure 1.

Figure 3 is a waveform diagram of the power converter in Figure 1 in non-regulated mode.

Figure 4 is a waveform diagram of the power converter in Figure 1 under two-stage operation.

Figure 5 is a waveform diagram of the power converter in Figure 1 operating in a single stage.

Figures 6A, 6B, 6C, and 6D are current schematic diagrams of the power converter in Figure 1 during four periods of single-stage operation.

Figure 7 is a schematic diagram of the signal generating circuit of the control circuit in Figure 1.

Figure 8 is a schematic diagram of the feedback circuit of the control circuit in Figure 1.

Figure 9 is a waveform diagram of the feedback circuit in Figure 8.

Figure 10 is a schematic diagram of the state detection circuit and closed loop circuit of the control circuit in Figure 1.

Figure 11 is a schematic diagram of the initial circuit and phase circuit of the control circuit in Figure 1.

Figure 12 is a schematic diagram of other phase circuits of the control circuit in Figure 1.

Figure 1 is a schematic circuit diagram of a power converter 1 in one embodiment of the present invention. The power converter 1 can step down the input voltage Vin to generate an output voltage Vo to the load. Both the input voltage Vin and the output voltage Vo can be DC voltages, and the output voltage Vo can be less than or equal to the input voltage Vin. The power converter 1 can operate in a non-regulated mode or a regulated mode. In either the non-regulating mode or the regulating mode, the power converter 1 can operate in discontinuous conduction mode (DCM) but not in continuous conduction mode (CCM).

When the input voltage Vin is between the low voltage threshold and the high voltage threshold, the power converter 1 can operate in the non-regulated mode, and the high voltage threshold can be greater than the low voltage threshold. When operating in the non-regulated mode, the power converter 1 can be regarded as a voltage divider, and the output voltage Vo can be a divided voltage of the input voltage Vin. In some embodiments, the output voltage Vo may be equal to half of the input voltage Vin in the non-regulated mode. When the input voltage Vin is less than the low voltage threshold or exceeds the high voltage threshold, the power converter 1 can operate in a regulation mode to maintain the output voltage Vo within a reasonable range without being too high or too low. The regulation mode can be implemented as single-phase operation or two-phase operation. When the input voltage Vin is less than the low voltage threshold, the power converter 1 can perform a single-stage operation to adjust the output voltage Vo to be less than or equal to the input voltage Vin. When operating in a single stage, the power converter 1 can be regarded as a buck converter. When the input voltage Vin exceeds the high voltage threshold, the power converter 1 can perform a two-stage operation to adjust the output voltage Vo to be less than or equal to the output voltage upper limit. In some embodiments, the output voltage upper limit value may be equal to half of the high voltage threshold value. For example, if the high voltage threshold is 40V, the low voltage threshold is 20V, and the output voltage upper limit is 20V, then when the input voltage Vin is equal to 30V, the output voltage Vo generated by the power converter 1 can be 15V; when When the input voltage Vin is equal to 10V, the power converter 1 can adjust the output voltage Vo to 10V; when the input voltage Vin is equal to 60V, the power converter 1 can adjust the output voltage Vo to 20V to avoid damage to the load and enhance system efficiency.

The power converter 1 may include switches 10 , 20 , 30 , 40 , a flying capacitor 50 , an inductor 60 , an output capacitor 70 and a control circuit 800 . The switch 10 includes a control terminal for receiving the switch signal S1, a first terminal and a second terminal. The switch 20 includes a control terminal for receiving the switch signal S2 and a first terminal coupled to the second terminal and the second terminal of the switch 10 . The switch 30 includes a control terminal for receiving the switch signal S3 and a first terminal coupled to the second terminal and the second terminal of the switch 20 . The switch 40 includes a control terminal for receiving the switch signal S4, a first terminal coupled to the second terminal of the switch 30, and a second terminal coupled to the ground terminal. Flying capacitor 50 includes a first terminal coupled to the second terminal of the switch 10 and a second terminal coupled to the second terminal of the switch 30 . The inductor 60 includes a first terminal coupled to the second terminal of the switch 20 and a second terminal. The output capacitor 70 includes a first terminal coupled to a second terminal of the inductor 60 and a second terminal coupled to the ground. The control circuit 800 may be coupled to the control end of the switch 10 , the control end of the switch 20 , the control end of the switch 30 and the control end of the switch 40 .

The first terminal of the switch 10 can receive the input voltage Vin, and the first terminal of the output capacitor 70 can output the output voltage Vo. The ground terminal can provide ground voltage GND, such as 0V. The second terminal of the switch 20 can provide the switching voltage Vx. The current flowing through the inductor 60 may be called the inductor current IL. When the inductor current IL flows from the first end of the inductor 60 to the second end of the inductor 60 , the inductor current IL is a positive current; and when the inductor current IL flows from the second end of the inductor 60 to the first end of the inductor 60 , the inductor current IL is negative current.

The control circuit 800 can receive the input voltage Vin and/or the output voltage Vo to generate switching signals S1 to S4, and then switch the switches 10, 20, 30 and 40 to set the power converter 1 in the non-regulating mode or the regulating mode. Figure 2 is a flow chart of the control method 200 of the power converter 1, which is applicable to the control circuit 800. The control method 200 includes steps S202 and S204, for allowing the control circuit 800 to control the power converter 1 to operate in a non-regulated mode or a regulated mode. Any reasonable technical changes or step adjustments fall within the scope disclosed by the present invention. Steps S202 and S204 are explained as follows: Step S202: In the non-adjustment mode, the control circuit 800 switches the switches 10, 20, 30 and 40 according to the resonant frequency; Step S204: In the adjustment mode, the control circuit 800 switches the switches 10, 20, 30 and 40 according to the resonant frequency. Switches 10, 20, 30 and 40.

In step S202, the power converter 1 operates in the non-regulating mode, and the control circuit 800 can switch Switches 10, 20, 30 and 40 are changed to couple the flying capacitor 50 to the output capacitor 70 through the inductor 60, so that the flying capacitor 50 and the output capacitor 70 form a voltage divider, and the output voltage Vo is generated according to the input voltage Vin, and at the same time the flying capacitor 50 and inductor 60 form a resonant circuit. The resonant circuit can generate a resonant frequency. The control circuit 800 switches the switches 10, 20, 30 and 40 according to the resonant frequency when the inductor current is 0 to generate a divided voltage of the input voltage Vin as the output voltage Vo, thereby achieving zero-current switching. switching, ZCS). The switching signals S1 and S3 can be the same, so that the switches 10 and 30 can be switched synchronously according to the resonant frequency, and the switching signals S2 and S4 can be the same, so that the switches 20 and 40 can be switched synchronously according to the resonant frequency. Roughly speaking, the power converter 1 can operate in the first stage Ph1 and the second stage Ph2 in turn, as shown in Figure 3. In the first phase Ph1, switches 10 and 30 are on and switches 20 and 40 are off. In the second phase Ph2, switches 20 and 40 are on and switches 10 and 30 are off.

Figure 3 is a waveform diagram of the power converter 1 in the non-regulated mode, in which the horizontal axis is time and the vertical axis is voltage or current. The following describes the operation of the power converter 1 in the non-regulated mode with reference to Figure 1 and Figure 3 at the same time. In the non-regulating mode, the control circuit 800 can use the phase signal P1 to generate the switching signals S1 and S3, use the phase signal P2 to generate the switching signals S2 and S4, generate the zero-crossing signal SZ according to the inductor current IL, and switch the phase according to the zero-crossing signal SZ. Signals P1 and P2. The zero-crossing signal SZ can be generated when the inductor current IL is detected to be 0A. The phase signal P1 and the switching signals S1 and S3 can be the same, and the phase signal P2 and the switching signals S2 and S4 can be the same. The generation method of the zero-crossing signal SZ and the phase signals P1 and P2 will be explained in subsequent paragraphs.

At time t1, the inductor current IL reaches 0A, triggering the pulse wave Pz1 on the zero-crossing signal SZ. At the same time, the pulse wave Pz1 triggers the phase signal P2 to switch from the high voltage VH to the low voltage VL, and the phase signal P1 is maintained at the low voltage VL. The low voltage VL may be the ground voltage GND. At time t2, the pulse wave Pz1 triggers the phase signal P1 to switch from the low voltage VL to the high voltage VH, the phase signal P2 is maintained at the low voltage VL, and the pulse wave Pz1 on the zero-crossing signal SZ ends. The pulse wave Pz1 may have a predetermined width, for example, the predetermined width is equal to (t2-t1).

Between time t2 and time t3, the phase signal P1 is maintained at the high voltage VH, the phase signal P2 is maintained at the low voltage VL, the inductor current IL oscillates at the resonant frequency, and the zero-crossing signal SZ is maintained at the low voltage VL. The switching signals S1 and S3 (=phase signal P1) can be high voltage VH, switches 10 and 30 are turned on, and the switching signals S2 and S4 (=phase signal P2) can be low voltage VL, switches 20 and 40 are turned off, so that the flying capacitor The first terminal of the capacitor 50 receives the input voltage Vin via the switch 10 , and the second terminal of the flying capacitor 50 is coupled to the first terminal of the inductor 60 via the switch 30 . Therefore, the input voltage Vin charges the flying capacitor 50 and the output capacitor 70 through the inductor 60 and performs magnetizing and demagnetizing on the inductor 60. At this time, the flying capacitor 50 and the output capacitor 70 can form a voltage divider to generate an output voltage. Vo, and the flying capacitor 50 and the inductor 60 can form a resonant circuit so that the inductor current IL oscillates at the resonant frequency. In some embodiments, the capacitance values of the flying capacitor 50 and the output capacitor 70 can be equal, so the cross voltages of the flying capacitor 50 and the output capacitor 70 are equal, and the switching voltage Vx and the output voltage Vo are both equal to half of the input voltage Vin.

At time t3, the inductor current IL reaches 0A, triggering the pulse wave Pz2 on the zero-crossing signal SZ. At the same time, the pulse wave Pz2 triggers the phase signal P1 to switch from the high voltage VH to the low voltage VL, and the phase signal P2 is maintained at the low voltage VL. At time t4, the pulse wave Pz2 triggers the phase signal P2 to switch from the low voltage VL to the high voltage VH, the phase signal P1 remains at the low voltage VL, and the pulse wave Pz2 on the zero-crossing signal SZ ends. The pulse wave Pz2 may have the same predetermined width as the pulse wave Pz1, for example, the predetermined width (t4-t3) of the pulse wave Pz2 is equal to the predetermined width (t2-t1) of the pulse wave Pz1. The period between time t1 and t3 is called the first phase Ph1.

Between time t4 and time t5, the phase signal P1 is maintained at the low voltage VL, the phase signal P2 is maintained at the high voltage VH, the inductor current IL oscillates at the resonant frequency, and the zero-crossing signal SZ is maintained at the low voltage VL. The switching signals S1 and S3 (= phase signal P1) can be low voltage VL, and the switches 10 and 30 are turned off, and the switching signals S2 and S4 can be high voltage VH, and the switches 20 and 40 are turned on, so that the first terminal of the flying capacitor 50 passes through switch 20 is coupled to the first terminal of the inductor 60 , and the second terminal of the flying capacitor 50 is coupled to the ground via the switch 40 . The flying capacitor 50 can be used as a voltage source to charge the output capacitor 70 and excite the inductor 60. Therefore, the cross voltage of the flying capacitor 50 can be equal to the output voltage Vo. If the cross voltage of the flying capacitor 50 is equal to half of the input voltage Vin, the output voltage Vo is also equal to half of the input voltage Vin. At the same time, the flying capacitor 50 and the inductor 60 can form a resonant circuit so that the inductor current IL oscillates at the resonant frequency.

At time t5, the inductor current IL reaches 0A, triggering the pulse wave Pz3 on the zero-crossing signal SZ. At the same time, the pulse wave Pz3 triggers the phase signal P2 to switch from the high voltage VH to the low voltage VL, and the phase signal P1 is maintained at the low voltage VL. At time t6, the pulse wave Pz3 triggers the phase signal P1 to switch from the low voltage VL to the high voltage VH, the phase signal P2 remains at the low voltage VL, and the pulse wave Pz3 on the zero-crossing signal SZ ends. The pulse wave Pz3 may have the same predetermined width as the pulse wave Pz1, for example, the predetermined width (t6-t5) of the pulse wave Pz1 is equal to the predetermined width (t2-t1) of the pulse wave Pz1. The period between time t3 and t5 is called the second phase Ph2.

Afterwards, if the control circuit 800 continues to determine that the power converter 1 can operate in the non-regulated mode, the power converter 1 will continue to switch the switches 10, 20, 30 and 40 according to the resonant frequency to repeat the waveforms from time t2 to t6, thereby changing the output Voltage Vo is output to the load.

In step S204, the power converter 1 operates in the regulation mode. During the two-stage operation, the switching signals S1 to S4 can be different, and the power converter 1 can operate in the first stage Ph1 and the second stage Ph2 in turn, as shown in Figure 4. The details of Figure 4 will be discussed in subsequent paragraphs. instruction. When operating in a single stage, the switching signals S1 and S2 can be the same, so that the switches 10 and 20 can be switched synchronously, and the switching signals S3 and S4 can be the same, so that the switches 30 and 40 can be switched synchronously, and the power converter 1 can repeat the first operation. Phase Ph1 operation is shown in Figure 5. The details of Figure 5 will be explained in subsequent paragraphs.

Figure 4 is a waveform diagram of the power converter 1 under two-stage operation, in which the horizontal axis is time and the vertical axis is voltage or current. The operation mode of the power converter 1 in the two-stage operation is explained below with reference to both Figure 1 and Figure 4 . The control circuit 800 can generate the switching signal S1 according to the phase signal P1, generate the switching signal S2 according to the phase signal P2, generate the switching signal S3 according to the phase signals P1, PA and PB, and generate the switching signal S4 according to the phase signals P1, PA and PB, thereby Adjust the output voltage Vo to be less than or equal to the upper limit of the output voltage. In the first phase Ph1, the phase signal P2 is maintained at the low voltage VL; and in the second phase Ph2, the phase signal P1 is maintained at the low voltage VL. The switching signal S1 can be equal to the phase signal P1, the switching signal S2 can be equal to the phase signal P2, the switching signal S3 can be equal to the OR operation result of the phase signals P1, PA and PB, and the switching signal S4 can be equal to the phase signals P2, PA and The OR operation result of PB and the generation method of the phase signals P1, P2, PA and PB will be explained in the subsequent paragraphs.

At time t1, the inductor current IL reaches 0A, the trigger phase signal PB switches from the high voltage VH to the low voltage VL and the trigger phase signal P1 switches from the low voltage VL to the high voltage VH. The phase signals PA and P2 remain at the low voltage VL, causing the switch Signal S1 switches from low voltage VL to high voltage VH, switching signal S2 remains at low voltage VL, switching signal S3 remains at high voltage VH, and switching signal S4 switches from high voltage VH to low voltage VL. Therefore, when inductor current IL reaches 0A When the switch 40 is turned off, ZCS is achieved and switching loss is reduced.

Between time t1 and time t2, the switching signals S1 and S3 are maintained at the high voltage VH, and the switching signals S2 and S4 are maintained at the low voltage VL, causing the switches 10 and 30 to be turned on, and the switches 20 and 40 to be turned off. The terminal receives the input voltage Vin through the switch 10 , and the second terminal of the flying capacitor 50 is coupled to the first terminal of the inductor 60 through the switch 30 . Therefore, the input voltage Vin charges the flying capacitor 50 and the output capacitor 70 and excites the inductor 60. At this time, the flying capacitor 50 and the inductor 60 can form a resonant circuit so that the inductor current IL starts to rise.

At time t2, the input voltage Vin exceeds the input voltage threshold, the trigger phase signal P1 switches from the high voltage VH to the low voltage VL and the trigger phase signal PA switches from the low voltage VL to the high voltage VH. The phase signals P2 and PB remain at the low voltage VL. , causing the switching signal S1 to switch from the high voltage VH to the low voltage VL, the switching signal S2 to maintain the low voltage VL, the switching signal S3 to maintain the high voltage VH, and the switching signal S4 to switch from the low voltage VL to the high voltage VH, so the control circuit 800 When the inductor 60 is excited, the switch 10 can be turned off before the inductor current IL of the inductor 60 reaches 0, thereby reducing the conduction time of the switch 10 .

Between time t2 and time t3, the switching signals S1 and S2 are maintained at the low voltage VL, and the switching signals S3 and S4 are maintained at the high voltage VH, causing the switches 10 and 20 to be turned off, the switches 30 and 40 to be turned on, and the first end of the inductor 60 It is coupled to the ground via switches 30 and 40, so the inductor 60 will be demagnetized, and the inductor current IL will be pulled down to 0A before it reaches the peak value. Since the inductor 60 is coupled to the ground, the decreasing speed of the inductor current IL will be much faster than the decreasing speed of the inductor current IL due to resonance in Figure 3, and the time required for the inductor 60 to be magnetized and demagnetized is shown in Figure 4. (=t3-t1) will be less than the time for one excitation and demagnetization of the inductor 60 in Figure 3 (=t3-t1), so the control circuit 800 will switch switches 10, 20, 30 and 40 according to the adjustment frequency that exceeds the resonant frequency. . The period between time t1 and t3 is called the first phase Ph1.

At time t3, the inductor current IL reaches 0A, the trigger phase signal PA switches from the high voltage VH to the low voltage VL and the trigger phase signal P2 switches from the low voltage VL to the high voltage VH. The phase signals PB and P1 remain at the low voltage VL, causing the switch The signal S1 is maintained at the low voltage VL, the switching signal S2 switches from the low voltage VL to the high voltage VH, the switching signal S3 switches from the high voltage VH to the low voltage VL, and the switching signal S4 is maintained at the high voltage VH. Therefore, when the inductor current IL reaches 0A When the switch 30 is turned off, ZCS is achieved and switching loss is reduced.

Between time t3 and time t4, the switching signals S2 and S4 are maintained at the high voltage VH, and the switching signals S1 and S3 are maintained at the low voltage VL, causing the switches 20 and 40 to be turned on, and the switches 10 and 30 to be turned off. The terminal is coupled to the first terminal of the inductor 60 via the switch 20 , and the second terminal of the flying capacitor 50 is coupled to the ground terminal via the switch 40 . The flying capacitor 50 can be used as a voltage source to charge the output capacitor 70 and excite the inductor 60. The flying capacitor 50 and the inductor 60 can form a resonant circuit to cause the inductor current IL to start to rise.

At time t4, the input voltage Vin exceeds the input voltage threshold, the trigger phase signal P2 switches from the high voltage VH to the low voltage VL and the trigger phase signal PB switches from the low voltage VL to the high voltage VH. The phase signals P1 and PA remain at the low voltage VL. , causing the switching signal S1 to maintain at the low voltage VL, the switching signal S2 to switch from the high voltage VH to the low voltage VL, the switching signal S3 to switch from the low voltage VL to the high voltage VH, and the switching signal S4 to maintain the high voltage VH, so the control circuit 800 When the inductor 60 is excited, the switch 20 can be turned off before the inductor current IL of the inductor 60 reaches 0, thereby reducing the conduction time of the switch 20 and switching the switch 20 at an adjustment frequency exceeding the resonant frequency.

Between time t4 and time t5, the switching signals S1 and S2 are maintained at the low voltage VL, and the switching signals S3 and S4 are maintained at the high voltage VH, causing the switches 10 and 20 to be turned off, the switches 30 and 40 to be turned on, and the first end of the inductor 60 It is coupled to the ground via switches 30 and 40, so the inductor 60 will be demagnetized, and the inductor current IL will be pulled down to 0A before it reaches the peak value. The period between time t3 and t5 is called the second phase Ph2. Since the inductor 60 is coupled to the ground, the decreasing speed of the inductor current IL will be much faster than the decreasing speed of the inductor current IL due to resonance in Figure 3, and the time required for the inductor 60 to be magnetized and demagnetized is shown in Figure 4. (=t5-t3) will be less than the time for one excitation and demagnetization of the inductor 60 in Figure 3 (=t5-t3), so the control circuit 800 will switch switches 10, 20, 30 and 40 according to the adjustment frequency that exceeds the resonant frequency. .

After that, if the control circuit 800 continues to determine that the power converter 1 can operate in the two-stage operation, operation, the power converter 1 will continue to operate in the first stage Ph1 and the second stage Ph2 in turn. The operation mode of the power converter 1 from time t5 to time t9 is similar to that from time t1 to time t5. The explanation can be found in the previous paragraphs and will not be repeated here.

Compared with the embodiment in Figure 2, the control circuit 80 in the embodiment in Figure 3 can reduce the ON time of the switch 10 or the switch 20, and increase the simultaneous ON time of the switch 30 and the switch 40, so as to exceed The resonant frequency is adjusted by switching the frequency switches 10, 20, 30 and 40, thereby adjusting the output voltage Vo to be equal to or less than the output voltage critical value. In some embodiments, when the output voltage Vo exceeds the output voltage threshold, the control circuit 800 can turn off the switch 10 or the switch 20 before the inductor current IL of the inductor 60 reaches 0 when energizing the inductor 60 . Then, after turning off the switch 10 or the switch 20, the control circuit 800 can turn on the switch 30 and the switch 40 to demagnetize the inductor 60. When demagnetizing the inductor 60, the control circuit 800 can detect when the inductor current IL of the inductor 60 reaches 0. Turn off switch 30 or switch 40. In some embodiments, when the power converter 1 is in a light load state, the control circuit 800 may additionally increase the OFF time of the switches 10 and 20, as well as the switches 30 and 40.

In some embodiments, when the power converter 1 is in a light load state, the control circuit 800 can increase the dead-time delay between the phase signals P1 and PA, PA and P2, P2 and PB, PB and P1. ), thereby increasing the off time (OFF time) of switches 10 and 20, switches 30 and 40, thereby achieving the purpose of power saving. When there is a space-time delay between the phase signals P1 and PA, PA and P2, P2 and PB, PB and P1, each pulse wave of the switching signals S3 and S4 in Figure 4 can be replaced by 3 sub-pulse waves. For example, the starting time of the first sub-pulse wave of the switching signal S3 can be later than the starting time of the original pulse wave of the switching signal S3 in Figure 4, and the end time of the third sub-pulse wave of the switching signal S3 can be later than that in Figure 4 At the end time of the original pulse wave of the switching signal S3, the pulse width of each sub-pulse wave is smaller than the pulse width of the original pulse wave of the switching signal S3 in Figure 4, and there may be a time interval between two adjacent sub-pulse waves. Similarly, The starting time of the first sub-pulse wave of the switching signal S4 can be later than the starting time of the original pulse wave of the switching signal S4 in Figure 4, and the end time of the third sub-pulse wave of the switching signal S4 can be later than that of the switch in Figure 4. The end time of the original pulse wave of the signal S4 and the pulse width of each sub-pulse wave are smaller than the pulse width of the original pulse wave of the switching signal S4 in Figure 4, and there may be a time interval between two adjacent sub-pulse waves.

Figure 5 is a waveform diagram of the power converter 1 operating in a single stage, in which the horizontal axis is time and the vertical axis is voltage or current. Figures 6A, 6B, 6C, and 6D are current schematic diagrams of the power converter 1 during the single-stage operation from T1 to T4. The following describes the operation mode of the power converter 1 in a single stage with reference to Figure 5, Figure 6A, Figure 6B, Figure 6C, and Figure 6D. The control circuit 800 can generate the switching signals S1 and S2 according to the phase signal P1. , and generate switching signals S3 and S4 according to the phase signal PA, thereby adjusting the output voltage Vo to be less than or equal to the input voltage Vin. The control circuit 800 can switch the switches 10 , 20 , 30 and/or 40 when the inductor current IL flows from the second terminal of the inductor 60 to the first terminal of the inductor 60 . The switching signals S1 and S2 may be equal to the phase signal P1, and the switching signals S3 and S4 may be equal to the phase signal PA. The generation methods of the phase signals P1 and PA will be described in subsequent paragraphs.

At time t1, the inductor current IL is between the minimum value Imin and 0A, and the switching voltage Vx is equal to the input voltage Vin. The phase signal P1 switches from the low voltage VL to the high voltage VH, and the phase signal PA is maintained at the low voltage VL. The minimum value Imin is a negative current approaching 0A, for example, Imin=-0.1A. Therefore, the switching signals S1 and S2 are switched from the low voltage VL to the high voltage VH, and the switching signals S3 and S4 are maintained at the low voltage VL, causing the switches 10 and 20 to be turned on, and the switches 30 and 40 to be turned off. Since the inductor current IL is between the minimum value Imin and 0A and the switching voltage Vx is equal to the input voltage Vin, the switches 10 and 20 can achieve ZCS and zero-voltage switching (ZVS), reducing switching losses. Between time t1 and t2, the switching signals S1 and S2 are maintained at the high voltage VH, the switching signals S3 and S4 are maintained at the low voltage VL, the switching voltage Vx is maintained at the input voltage Vin, and the inductor current IL continues to rise, as shown in Figure 6A shown. Time t1 to t2 can Called period T1. Referring to FIG. 6A , during the period T1 , the switching voltage Vx is equal to the input voltage Vin, and the inductor current IL flows from the first end of the switch 10 through the switch 10 , the switch 20 and the inductor 60 in order to charge the output capacitor 70 .

At time t2, the output voltage Vo reaches the preset value of the output voltage, the phase signal P1 switches from the high voltage VH to the low voltage VL, and the phase signal PA switches from the low voltage VL to the high voltage VH, the inductor current IL reaches the maximum value Imax, and switches Voltage Vx switches to negative voltage V-. The maximum value Imax is a positive current well beyond 0A, for example Imax=3A. The negative voltage V- is a negative voltage close to 0V, for example, V-=-10mV. Therefore, the switching signals S1 and S2 are switched from the high voltage VH to the low voltage VL, and the switching signals S3 and S4 are switched from the low voltage VL to the high voltage VH, causing the switches 10 and 20 to be turned off, and the switches 30 and 40 to be turned on. Between time t2 and t3, the switching signals S1 and S2 are maintained at the low voltage VL, the switching signals S3 and S4 are maintained at the high voltage VH, the switching voltage Vx is maintained at the negative voltage V-, and the inductor current IL decreases from the maximum value Imax, The time t2 to t3 may be called period T2. Referring to Figure 6B, during period T2, the switching voltage Vx is a negative voltage V-, and the inductor current IL flows from the ground terminal through the switch 40, the switch 30 and the inductor 60 in order to degauss the inductor 60, and the switching voltage Vx is maintained at a negative voltage. V-.

At time t3, the inductor current IL reaches 0A, the switching voltage Vx switches to 0V, the phase signal P1 is maintained at the low voltage VL, and the phase signal PA is maintained at the high voltage VH. Therefore, the switching signals S1 and S2 are maintained at the low voltage VL, and the switching signals S3 and S4 are maintained at the high voltage VH. Between time t3 and t4, the switching signals S1 and S2 are maintained at the low voltage VL, and the switching signals S3 and S4 are maintained at the high voltage VH, so that the switches 10 and 20 remain off, the switches 30 and 40 remain on, and the inductor current IL changes from 0A decreases, and the switching voltage Vx is maintained at 0V, as shown in Figure 6C. Time t3 to t4 may be called period T3. Referring to Figure 6C, during period T3, the switching voltage Vx is 0V, the inductor 60 has been completely demagnetized, and the inductor current IL flows through the inductor 60, switch 30 and switch 40 in order to reduce the inductor current IL to a negative value. The length of the period T3 may be positively related to the magnitude of the inductor current IL. If the length of the period T3 is longer, the magnitude of the inductor current IL will be larger.

At time t4, the phase signal P1 remains at the low voltage VL, and the phase signal PA switches from the high voltage VH to the low voltage VL, the inductor current IL reaches the minimum value Imin, and the switching voltage Vx switches to the input voltage Vin. Therefore, the switching signals S1 and S2 are maintained at the low voltage VL, and the switching signals S3 and S4 are switched from the high voltage VH to the low voltage VL, causing the switches 10 and 20 to be turned off, and the switches 30 and 40 to be turned off. Between time t4 and t5, the switching signals S1 and S2 are maintained at the low voltage VL, the switching signals S3 and S4 are maintained at the low voltage VL, the inductor current IL rises from the minimum value Imin, and the switching voltage Vx is maintained at the input voltage Vin, time The period t4 to t5 may be called period T4. Referring to Figure 6D, during period T4, the switching voltage Vx is equal to the input voltage Vin. Since the switches 30 and 40 are turned off, the inductor current IL flows through the inductor 60, the body diode of the switch 20 and the switch 10 in sequence. body diode to the first terminal of switch 10. The period between time t1 and t4 is called the first phase Ph1.

Afterwards, if the control circuit 800 continues to determine that the power converter 1 can operate in a single stage, the power converter 1 will continue to repeatedly execute the first stage Ph1.

In the embodiment of FIG. 4 , the control circuit 800 turns off the switches 30 and 40 only after the inductor current IL reaches 0A, thereby achieving ZCS and ZVS at the same time. In other embodiments, the control circuit 800 can also turn off the switches 30 and 40 when the inductor current IL reaches 0 during single-stage operation, thereby achieving ZCS. In other embodiments, the control circuit 800 can also turn off the switches 10, 20, 30 and 40 before the inductor current IL reaches 0 during single-stage operation, thereby increasing the average inductor current IL and shortening the period of the first stage Ph1. Increase the regulation frequency and increase circuit efficiency.

Although the embodiments in Figures 2 and 3 only illustrate the implementation of turning off the switches 10, 20, 30 and/or 40 when the inductor current IL reaches 0 in the non-regulating mode and the two-stage operation respectively, those skilled in the art may also According to the principle of generating negative inductor current IL in the embodiment of FIG. 4, the control circuit 800 turns off the switches 10, 20, 30 and/or 40 after the inductor current IL reaches 0A, so that the non-regulating mode and the two-stage operation can be performed at the same time. Achieve ZCS and ZVS and reduce switching losses. In addition, in some embodiments, the control circuit 800 can also turn off the switches 10, 20, 30 and/or 40 before the inductor current IL reaches 0 during the non-regulating mode and/or two-stage operation, thereby increasing the average inductor current IL. , shorten the period of Ph1 in the first stage, increase the adjustment frequency, and increase circuit efficiency.

In addition, the control circuit 80 can reduce the ON time of the switch 10 or the switch 20, and increase the simultaneous ON time of the switch 30 and the switch 40, thereby switching the switches 10, 20, 30 and 40 according to the adjustment frequency exceeding the resonant frequency. The output voltage Vo is then adjusted to be equal to or less than the output voltage critical value. In some embodiments, when the output voltage Vo exceeds the output voltage threshold, the control circuit 800 can turn off the switch 10 or the switch 20 before the inductor current IL of the inductor 60 reaches 0 when energizing the inductor 60 . Then, after turning off the switch 10 or the switch 20, the control circuit 800 can turn on the switch 30 and the switch 40 to demagnetize the inductor 60. When demagnetizing the inductor 60, the control circuit 800 can detect when the inductor current IL of the inductor 60 reaches 0. Turn off switch 30 or switch 40. In some embodiments, when the power converter 1 is in a light load state, the control circuit 800 may additionally increase the OFF time of the switches 10 and 20, as well as the switches 30 and 40.

Figure 7 is a schematic diagram of a portion of the control circuit 800. The control circuit 800 may include a signal generating circuit 801. The signal generating circuit 801 can generate switching signals S1 to S4 according to the phase signals P1, P2, PA and PB and the mode signal MODE. The signal generating circuit 801 may include buffers 80 to 83, OR gates 84, 85, 86, 88 and 89, AND gates 90 to 95, and inverters 96 to 98. The mode signal MODE can be enabled during single-stage operation, and can be disabled during non-adjusting mode and two-stage operation. The mode signal MODE can be used to disable switch signals S2 and S4.

The buffer 80 includes an input terminal for receiving the phase signal P1 and an output terminal for outputting the switching signal S1. The phase signal P1 can generate the switching signal S1 after passing through the buffer 80. Therefore, the switching signal S1 can be a signal after a gate delay of the phase signal P1.

The inverter 96 includes an input terminal for receiving the mode signal MODE and an output terminal. The AND gate 90 includes a first input terminal for receiving the phase signal P2, a second input terminal coupled to the output terminal of the inverter 96, and an output terminal. The AND gate 91 includes a first input terminal for receiving the mode signal MODE, a second input terminal for receiving the phase signal P1, and an output terminal. The OR gate 84 includes a first input terminal coupled to the output terminal of the AND gate 90 and a second input terminal coupled to the output terminal of the AND gate 91 and the output terminal. The buffer 81 includes an input terminal coupled to the output terminal of the OR gate 84 and an output terminal for outputting the switching signal S2. When the mode signal MODE is enabled, the switch signal S2 may be a delayed signal of the phase signal P1. When the mode signal MODE is disabled, the switching signal S2 may be a signal obtained by the phase signal P2 after a gate delay.

The OR gate 88 includes a first input terminal for receiving the phase signal P1, a second input terminal for receiving the phase signal PA, a third input terminal for receiving the phase signal PB, and an output terminal. The inverter 97 includes an input terminal for receiving the mode signal MODE and an output terminal. The AND gate 92 includes a first input terminal coupled to the output terminal of the OR gate 88 , a second input terminal coupled to the output terminal of the inverter 97 , and an output terminal. The AND gate 93 includes a first input terminal for receiving the mode signal MODE, a second input terminal for receiving the phase signal PA, and an output terminal. The OR gate 85 includes a first input terminal coupled to the output terminal of the AND gate 92 and a second input terminal coupled to the output terminal of the AND gate 93 and the output terminal. The buffer 82 includes an input terminal coupled to the output terminal of the OR gate 85 and an output terminal for outputting the switching signal S3. When the mode signal MODE is enabled, the switch signal S3 may be a delayed signal of the phase signal PA. When the mode signal MODE is disabled, the switching signal S3 may be a signal obtained by ORing the phase signals P1, PA and PB after a gate delay.

The OR gate 89 includes a first input terminal for receiving the phase signal P2, a second input terminal for receiving the phase signal PA, a third input terminal for receiving the phase signal PB, and an output terminal. The inverter 98 includes an input terminal for receiving the mode signal MODE and an output terminal. The AND gate 94 includes a first input terminal coupled to the output terminal of the OR gate 89 , a second input terminal coupled to the output terminal of the inverter 98 , and an output terminal. The AND gate 95 includes a first input terminal for receiving the mode signal MODE, a second input terminal for receiving the phase signal PA, and an output terminal. The OR gate 86 includes a first input terminal coupled to the output terminal of the AND gate 94 and a second input terminal coupled to the output terminal of the AND gate 95 and the output terminal. The buffer 83 includes an input terminal coupled to the output terminal of the OR gate 86 and an output terminal for outputting the switching signal S4. The switching signal S4 may be a delayed signal of the phase signal PA. When the mode signal MODE is disabled, the switch signal S4 may be a signal obtained by ORing the phase signals P2, PA and PB after a gate delay.

Figure 8 is a schematic diagram of other parts of the control circuit 800. The control circuit 800 may further include a feedback circuit 802 . The feedback circuit 802 can generate the feedback signal SFB to adjust the output voltage Vo. The feedback signal SFB can indicate that the input voltage Vin exceeds the input voltage threshold or the output voltage Vo exceeds the output voltage upper limit, and can be used to reset the phase signals P1 and/or P2 to the low voltage VL early, thereby reducing the number of switches 10 and/or 20 on time and increase the adjustment frequency. The feedback circuit 802 may include a NOR gate 110, a current source 112, a transistor 111, capacitors 113 and 152, resistors 114, 115, 116, 117 and 151, a switch 120, an error amplifier 150 and a comparator 155.

The NOR gate 110 includes a first input terminal for receiving the phase signal P1, a second input terminal for receiving the phase signal P2, and an output terminal for outputting the result of the OR operation of the phase signals P1 and P2. The current source 112 includes a first terminal coupled to the power supply terminal for receiving the power supply voltage Vcc, and a second terminal. The transistor 111 includes a control terminal coupled to the output terminal of the NOR gate 110 for receiving the operation result of the NOR gate 110, a first terminal coupled to the second terminal of the current source 112, and a second terminal coupled to the output terminal of the NOR gate 110. Connected to ground. Capacitor 113 It includes a first terminal coupled to the first terminal of the transistor 111 and a second terminal coupled to the ground terminal. The NOR gate 110, the current source 112, the transistor 111 and the capacitor 113 can form a ramp circuit. When the phase signal P1 or the phase signal P2 is the high voltage VH, the ramp circuit can generate a gradually rising ramp signal RAMP. When the phase signal P1 and/or the phase signal P2 are both low voltage VL, the ramp circuit can reset the ramp signal RAMP to the ground voltage GND.

The resistor 114 includes a first terminal for receiving the output voltage Vo and a second terminal. The resistor 115 includes a first terminal coupled to a second terminal of the resistor 114 and a second terminal coupled to the ground. The resistor 116 includes a first terminal for receiving the reference voltage VR and a second terminal. The reference voltage VR can be set to 2V or other suitable values. In some embodiments, the power converter 1 may use the same reference voltage VR, such as 2V, for single-stage operation and two-stage operation. In some embodiments, the power converter 1 can use different reference voltages VR for single-stage operation and two-stage operation. For example, the reference voltage VR for single-stage operation can be 1.6V, and the reference voltage VR for two-stage operation can be 2V. . The resistor 117 includes a first terminal coupled to the second terminal of the resistor 116 and a second terminal. The switch 120 includes a control terminal for receiving the closed-loop signal CLP, a first terminal coupled to the second terminal of the resistor 117, and a second terminal coupled to the ground terminal. The resistors 114 and 115 can form a voltage divider to generate a divided voltage according to the output voltage Vo. For example, the resistance value of the resistor 114 can be 9k ohms, and the resistance value of the resistor 115 can be 1k ohms, so that the voltage divider produces a voltage dividing ratio of 10:1. If the output voltage Vo is 20V, then the first voltage of the resistor 115 The terminal can generate 2V as a divided voltage of the output voltage Vo. The error amplifier 150 includes an inverting input terminal coupled to the second terminal of the resistor 114, a forward input terminal coupled to the second terminal of the resistor 116, and an output terminal. The resistor 151 includes a first terminal coupled to the output terminal of the error amplifier 150 and a second terminal. The capacitor 152 includes a first terminal coupled to a second terminal of the resistor 114 and a second terminal coupled to the ground. When the closed loop signal CLP is the low voltage VL, the switch 120 can be turned off, and the error amplifier 150 can compare the divided voltage of the output voltage Vo with the reference voltage VR to generate the error amplification signal COMP. The error amplification signal COMP can be a stable voltage level and is related to the output voltage Vo. If the divided voltage of the output voltage Vo exceeds The reference voltage VR, the error amplification signal COMP will decrease; if the divided voltage of the output voltage Vo is less than the reference voltage VR, the error amplification signal COMP will increase. For example, if the reference voltage VR is 2V and the divided voltage of the output voltage Vo is 2V, the error amplifier 150 can set the error amplification signal COMP to 3V; if the reference voltage VR is 2V and the divided voltage of the output voltage Vo is 2.2V, then The error amplifier 150 can set the error amplification signal COMP to 2.8V; if the reference voltage VR is 2V and the divided voltage of the output voltage Vo is 1.8V, the error amplifier 150 can set the error amplification signal COMP to 3.2V.

The closed loop signal CLP can represent the operating mode of the power converter 1 . If the closed-loop signal CLP is the low voltage VL, the power converter 1 will operate in the non-regulating mode; if the closed-loop signal CLP is the high voltage VH, the power converter 1 will operate in the regulating mode. When the closed loop signal CLP is the high voltage VH, the switch 120 can be turned on, and the resistors 116 and 117 can form a voltage divider to generate a divided voltage according to the reference voltage VR. The error amplifier 150 can compare the divided voltage of the output voltage Vo and the divided voltage of the reference voltage VR to generate an amplified error amplification signal COMP. For example, the resistance value of the resistor 116 can be 1k ohm, and the resistance value of the resistor 117 can be 9k ohm, so that the voltage divider can produce a voltage dividing ratio of 10:9. If the reference voltage VR is 2V, then the resistance of the resistor 117 is One end can generate 1.8V as a divided voltage of the reference voltage VR, and the error amplifier 150 can reduce the level of the error amplification signal COMP when the divided voltage of the output voltage Vo exceeds 1.8V, and when the divided voltage of the output voltage Vo is less than 1.8V When raising the level of the error amplification signal COMP. The closed loop signal CLP can provide hysteresis control on the reference voltage VR. The resistor 151 and the capacitor 152 can form a low-pass filter for filtering the error amplification signal COMP. In some embodiments, the resistor 151 and the capacitor 152 can also be omitted and the error amplification signal COMP is directly input to the comparator 155 .

The comparator 155 includes a positive input terminal coupled to the first terminal of the capacitor 113, a reverse input terminal, a first terminal of the resistor 151, and an output terminal for outputting the feedback signal SFB. The comparator 155 can compare the ramp signal RAMP and the error amplification signal COMP. When the ramp signal RAMP is less than the error amplification signal When COMP occurs, the comparator 155 can set the feedback signal SFB to the low voltage VL. Once the ramp signal RAMP reaches the error amplification signal COMP, the comparator 155 can insert a positive pulse wave with a predetermined width in the feedback signal SFB.

According to the previous paragraph, if the divided voltage of the output voltage Vo exceeds the reference voltage VR, the error amplification signal COMP will decrease, allowing the ramp signal RAMP to reach the error amplification signal COMP faster, thereby generating the feedback signal SFB faster. In addition, when the closed-loop signal CLP is a high voltage VH, the error amplification signal COMP will further decrease, allowing the ramp signal RAMP to reach the error amplification signal COMP faster, thereby generating the feedback signal SFB faster and more stably, thereby increasing the feedback signal SFB reliability.

Figure 9 is a waveform diagram of the feedback circuit 802, in which the horizontal axis is time and the vertical axis is voltage. The operation of the feedback circuit 802 is explained below with reference to Figure 8.

Between time t1 and t2, the phase signal P1 is a high voltage VH, and the trigger ramp signal RAMP begins to rise. At the same time, the phase signal P2 and the feedback signal SFB are maintained at a low voltage VL. At time t2, the ramp signal RAMP and the error amplification signal COMP are equal, triggering the pulse wave Pfb1 on the feedback signal SFB. The pulse wave Pfb1 triggers the phase signal P1 to be switched to the low voltage VL, and because the phase signals P1 and P2 are both low voltages VL, so the ramp signal RAMP is reset to the low voltage VL. At time t3, the pulse wave Pfb1 ends, and the phase signals P1 and P2 and the ramp signal RAMP are maintained at the low voltage VL. Between time t3 and t4, the phase signals P1 and P2, the ramp signal RAMP and the feedback signal SFB are all maintained at the low voltage VL. During single-stage operation, if the input voltage Vin is too low, for example, the reference voltage VR is 2V and the input voltage Vin is equal to 10V, the ramp signal RAMP will continue to be smaller than the error amplification signal COMP, so the comparator 155 will not generate the feedback signal SFB. pulse wave.

Between time t4 and t5, the phase signal P2 is at the high voltage VH, and the trigger ramp signal RAMP begins to rise. At the same time, the phase signal P1 and the feedback signal SFB are maintained at the low voltage VL. At time t5, the ramp signal RAMP and the error amplification signal COMP are equal, triggering the pulse wave Pfb2 on the feedback signal SFB. The pulse wave Pfb2 triggers the phase signal P2 to be switched to the low voltage VL, and because the phase signals P1 and P2 are both low voltages VL, so the ramp signal RAMP is reset to the low voltage VL. At time t6, the pulse wave Pfb2 ends, and the phase signals P1 and P2 and the ramp signal RAMP are maintained at the low voltage VL.

The feedback circuit 802 may repeat the waveform from time t1 to t2 to generate the feedback signal SFB.

Figure 10 is a schematic diagram of other parts of the control circuit 800. The control circuit 800 may further include a status detection circuit 803 and a closed loop circuit 804. The state detection circuit 803 can generate a zero-crossing signal SZ and a cut-off signal SP. The zero-crossing signal SZ can indicate that the voltage across the inductor 60 passes 0V, and the cut-off signal SP can be used to cut off the switches 30 and 40 . The closed-loop circuit 804 can generate a closed-loop signal CLP, and the closed-loop signal CLP can represent the operating mode of the power converter 1 . When the closed-loop signal CLP is a high voltage VH, it indicates that the power converter 1 is operating in the regulating mode, and when the closed-loop signal CLP is a low voltage VL, it indicates that the power converter 1 is operating in a non-regulating mode.

The state detection circuit 803 may include comparators 210 and 220, a zero-crossing detector (ZCD) 250, a pulse generator 223, and an AND gate 225. The comparator 210 includes a forward input terminal for receiving the switching voltage Vx, a reverse input terminal for receiving the output voltage Vo, and an output terminal for outputting a comparison result of the switching voltage Vx and the output voltage Vo. The switching voltage Vx is the voltage at the first terminal of the inductor 60 , and the output voltage Vo is the voltage at the second terminal of the inductor 60 . When it is detected that the switching voltage Vx exceeds the output voltage Vo, the comparator 210 can output the high voltage VH as the comparison result; when it is detected that the switching voltage Vx is less than the output voltage Vo, the comparator 210 can output the low voltage VL as the comparison result. Zero Cross Detector 250 Pack It includes an input terminal coupled to the output terminal of the comparator 210 for receiving the comparison result of the switching voltage Vx and the output voltage Vo, and an output terminal for outputting the zero-crossing signal SZ. When detecting that the two consecutive comparison results of the comparator 210 switch from the high voltage VH to the low voltage VL or from the low voltage VL to the high voltage VH, the zero-crossing detector 250 can generate a pulse with a predetermined width on the zero-crossing signal SZ. wave; when detecting that the two consecutive comparison results of the comparator 210 are both high voltage VH or both low voltage VL, the zero-crossing detector 250 can set the zero-crossing signal SZ to the low voltage VL.

The comparator 220 includes a forward input terminal for receiving the switching voltage Vx, a reverse input terminal for receiving the degaussing reference voltage VT, and an output terminal for outputting a comparison result of the switching voltage Vx and the degaussing reference voltage VT as a degaussing signal. SDM. The degaussing reference voltage VT can be set to 0V. The switching voltage Vx may be equal to the voltage across switches 30 and 40 . If the inductor 60 is completely demagnetized, the switching voltage Vx will reach a peak value. When the switching voltage Vx exceeds the degaussing reference voltage VT, the comparator 220 can set the degaussing signal SDM to a high voltage VH; when the switching voltage Vx is less than the degaussing reference voltage VT, the comparator 220 can set the degaussing signal SDM to a low voltage VL. The pulse generator 223 includes an enable terminal for receiving the control signal ZM, an input terminal for receiving the degaussing signal SDM, and an output terminal. The AND gate 225 includes a first input terminal for receiving the degaussing signal SDM, a second input terminal coupled to the output terminal of the pulse generator 223, and an output terminal for outputting the cut-off signal SP. The control signal ZM can be used to control the ZVS operation of the power converter 1 . The control signal ZM can be enabled during single-stage operation and disabled during non-regulated mode and two-stage operation.

When the control signal ZM is disabled, the cut-off signal SP can be the signal of the degaussing signal SDM after a gate delay. When the control signal ZM is enabled, the pulse wave generator 223 can generate a negative pulse wave in the cut-off signal SP after receiving the degaussing signal SDM and passing through the first predetermined delay. The cut-off signal SP can be the signal after the first predetermined delay. . The length of the first predetermined delay is equal to the length of period T3 in Figure 5.

The closed loop circuit 804 may include inverters 261 and 267, a flip-flop 260, a pulse generator 265 and an OR gate 263. The inverter 261 includes an input terminal for receiving the zero-cross signal SZ and an output terminal for outputting an inverse signal of the zero-cross signal SZ. The OR gate 263 includes a first input terminal for receiving the phase signal P1, a second input terminal for receiving the phase signal P2, and an output terminal for outputting an OR operation result of the phase signals P1 and P2. The pulse generator 265 includes an input terminal for receiving the result of the OR operation of the output phase signals P1 and P2, and an output terminal for outputting the first pulse signal. The inverter 267 includes an input terminal for receiving the first pulse signal and an output terminal for outputting the first reset signal. The flip-flop 260 includes a data input terminal for receiving the reverse signal of the zero-crossing signal SZ, a clock terminal for receiving the feedback signal SFB, a reset terminal for receiving the first reset signal, and an output terminal for To output the closed loop signal CLP. The closed-loop signal CLP can be triggered by the feedback signal SFB and reset by the rising edge of the phase signal P1 or P2.

Figures 11 and 12 are schematic diagrams of other parts of the control circuit 800. FIG. 11 shows that the control circuit 800 may further include a start circuit 300 and phase circuits 805 and 806. FIG. 12 shows that the control circuit 800 may further include phase circuits 807 and 808. The starting circuit 300 can generate the starting signal Son, the phase circuit 805 can generate the phase signal P1 and the trigger signal TG1, the phase circuit 806 can generate the phase signal PA and the trigger signal TGA, and the phase circuit 807 can generate the phase signal P2 and the trigger signal TG2. And the phase circuit 808 can generate the phase signal PB and the trigger signal TGB. When the closed loop signal CLP is low voltage VL (non-regulated mode), the phase circuits 805 and 807 will be enabled and the phase circuits 806 and 808 will be disabled. When the closed loop signal CLP is high voltage VH (regulation mode), the phase circuits 805 to 808 are all enabled.

The phase circuit 805 may include AND gates 321 and 322, a NOR gate 325, a flip-flop 320 and a pulse generator 330. The AND gate 321 includes a first input terminal for receiving the phase signal P1, a second input terminal for receiving the zero-crossing signal SZ, and an output terminal for outputting the sum of the phase signal P1 and the zero-crossing signal SZ. The result of the operation. The AND gate 322 includes a first input terminal for receiving the phase signal P1, a second input terminal for receiving the feedback signal SFB, and an output terminal for outputting the result of the AND operation of the phase signal P1 and the feedback signal SFB. The NOR gate 325 includes a first input terminal coupled to the output terminal of the AND gate 321 for receiving the operation result of the AND gate 321, and a second input terminal coupled to the output terminal of the AND gate 322 for receiving the AND gate. The operation result and output terminal of 322 are used to output the operation result of the NOR operation. The flip-flop 320 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal for receiving the start signal Son, and a reset terminal coupled to the output terminal of the NOR gate 325 for receiving the NOR gate. The operation result and output terminal of 325 are used to output the phase signal P1, and the reverse output terminal is used to output the reverse signal of the phase signal P1. The pulse generator 330 includes an input terminal for receiving the reverse signal of the phase signal P1 and an output terminal for outputting the trigger signal TG1.

The phase circuit 806 may include an AND gate 341 and a NAND gate 342, a flip-flop 343 and a pulse generator 345. The AND gate 341 includes a first input terminal for receiving the closed-loop signal CLP, a second input terminal for receiving the trigger signal TG1, and an output terminal for outputting the result of the AND operation of the closed-loop signal CLP and the trigger signal TG1. . The NAND gate 342 includes a first input terminal for receiving the cut-off signal SP, a second input terminal for receiving the phase signal PA, and an output terminal for outputting the result of the NAND operation of the cut-off signal SP and the phase signal PA. . The flip-flop 343 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal, coupled to the output terminal of the AND gate 341, for receiving the operation result of the AND gate 341, and a reset terminal coupled to the NAND gate. The output terminal of 342 is used to receive the operation result of the NAND gate 342, the output terminal is used to output the phase signal PA, and the reverse output terminal is used to output the reverse signal of the phase signal PA. The pulse generator 345 includes an input terminal for receiving the reverse signal of the phase signal PA, and an output terminal for outputting the trigger signal TGA.

The flip-flop 320 can be triggered by the start signal Son to set the phase signal P1 to the high voltage VH, and can reset the phase signal P1 by the zero-crossing signal SZ and/or the feedback signal SFB. Pulse Generator 330 A space-time delay can be generated for the trigger signal TG1. The longer the space-time delay of the trigger signal TG1 is, the longer the start time of the phase signal P2/PA is delayed, increasing the space-time delay between the end of the phase signal P1 and the start of the phase signal P2/PA.

When the closed loop signal CLP is the low voltage VL, the phase circuit 806 will be disabled. When the closed-loop signal CLP is the high voltage VH, the phase circuit 806 is enabled, the flip-flop 343 can be triggered by the trigger signal TG1 to generate the phase signal PA, and can be reset by the cut-off signal SP. The pulse generator 345 may be used to generate a space-time delay (second predetermined delay) of the trigger signal TGA. The longer the space-time delay of the trigger signal TGA is, the more the start time of the phase signal P2 is delayed, increasing the space-time delay between the end of the phase signal PA and the start of the phase signal P2. The length of the second predetermined delay is equal to the length of period T4 in FIG. 5 .

The starting circuit 300 may include inverters 311 and 313, AND gates 310, 312, 316 and 317, or OR gates 315 and 318. The inverter 311 includes an input terminal for receiving the closed-loop signal CLP and an output terminal for outputting an inverse signal of the closed-loop signal CLP. The AND gate 310 includes a first input terminal for receiving the trigger signal TGB, a second input terminal for receiving the closed loop signal CLP, and an output terminal. The AND gate 312 includes a first input terminal for receiving the reverse signal of the closed loop signal CLP, a second input terminal for receiving the trigger signal TG2, and an output terminal. The OR gate 315 includes a first input terminal coupled to the output terminal of the AND gate 310 and a second input terminal coupled to the output terminal of the AND gate 312 and the output terminal. The inverter 313 includes an input terminal for receiving the mode signal MODE and an output terminal for outputting an inverse signal of the mode signal MODE. The AND gate 316 includes a first input terminal coupled to the output terminal of the OR gate 315, a second input terminal for receiving the reverse signal of the mode signal MODE, and an output terminal. The AND gate 317 includes a first input terminal for receiving the mode signal MODE, a second input terminal for receiving the trigger signal TGA, and an output terminal. The OR gate 318 includes a first input terminal coupled to the output terminal of the AND gate 316, a second input terminal coupled to the output terminal of the AND gate 317, and an output terminal for outputting the start signal Son.

When the mode signal MODE is enabled, the power converter 1 can perform a single-stage operation, and the starting signal Son can be a signal after a gate delay of the trigger signal TGA. When the mode signal MODE is disabled and the closed loop signal CLP is enabled, the power converter 1 can perform a two-stage operation, and the starting signal Son can be a signal after a gate delay of the trigger signal TGB. When the mode signal MODE is disabled and the closed loop signal CLP is disabled, the power converter 1 can operate in the non-regulated mode, and the starting signal Son can be the signal of the trigger signal TG2 after a gate delay.

The phase circuit 807 may include AND gates 410, 412, 421 and 422, an OR gate 415, a NOR gate 425, a flip-flop 420, a pulse generator 430 and an inverter 411. The AND gate 410 includes a first input terminal for receiving the trigger signal TGA, a second input terminal for receiving the closed loop signal CLP, and an output terminal for outputting the result of the AND operation of the trigger signal TGA and the closed loop signal CLP. . The inverter 411 includes an input terminal for receiving the closed-loop signal CLP and an output terminal for outputting an inverse signal of the closed-loop signal CLP. The AND gate 412 includes a first input terminal coupled to the output terminal of the inverter 411 for receiving the reverse signal of the closed loop signal CLP, a second input terminal for receiving the trigger signal TG1, and an output terminal for receiving the reverse signal of the closed loop signal CLP. Outputs the result of the AND operation of the reverse signal of the closed-loop signal CLP and the trigger signal TG1.

The OR gate 415 includes a first input terminal coupled to the output terminal of the AND gate 410 for receiving the operation result of the AND gate 410 and a second input terminal coupled to the output terminal of the AND gate 412 for receiving the AND gate 412 The operation result, and the output terminal are used to output the operation result of the OR operation. The AND gate 421 includes a first input terminal for receiving the phase signal P2, a second input terminal for receiving the zero-crossing signal SZ, and an output terminal for outputting the operation result of the AND operation of the phase signal P2 and the zero-crossing signal SZ. . The AND gate 422 includes a first input terminal for receiving the phase signal P2, a second input terminal for receiving the feedback signal SFB, and an output terminal for outputting the result of the AND operation of the phase signal P2 and the feedback signal SFB. NOR gate 425 contains the first input The second input terminal is used to receive the operation result of the AND gate 421, the second input terminal is used to receive the operation result of the AND gate 422, and the output terminal is used to output the operation result of the NOR operation.

The flip-flop 420 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal coupled to the output terminal of the OR gate 415 for receiving the operation result of the OR gate 415, and a reset terminal for receiving the NOR gate. The operation result and output terminal of 425 are used to output the phase signal P2, and the reverse output terminal is used to output the reverse signal of the phase signal P2. The pulse generator 430 includes an input terminal for receiving the reverse signal of the phase signal P2 and an output terminal for outputting the trigger signal TG2.

The phase circuit 808 may include an AND gate 441, a NAND gate 442, a flip-flop 443 and a pulse generator 445. The AND gate 441 includes a first input terminal for receiving the closed-loop signal CLP, a second input terminal for receiving the trigger signal TG2, and an output terminal for outputting the result of the AND operation of the closed-loop signal CLP and the trigger signal TG2. . The NAND gate 442 includes a first input terminal for receiving the cut-off signal SP, a second input terminal for receiving the phase signal PB, and an output terminal for outputting the result of the NAND operation of the cut-off signal SP and the phase signal PB. . The flip-flop 443 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal for receiving the operation result of the AND gate 441, a reset terminal for receiving the operation result of the NAND gate 442, and an output terminal for receiving the operation result of the AND gate 441. The phase signal PB is output, and the reverse output terminal is used to output the reverse signal of the phase signal PB. The pulse generator 445 includes an input terminal for receiving the reverse signal of the phase signal PB, and an output terminal for outputting the trigger signal TGB.

When the closed loop signal CLP is the low voltage VL, the AND gate 410 will be disabled, the flip-flop 420 can be triggered by the trigger signal TG1 to generate the phase signal P2, and can reset the phase signal P2 by the zero-crossing signal SZ. When the closed loop signal CLP is the high voltage VH, the AND gate 412 will be disabled, the flip-flop 420 can be triggered by the trigger signal TGA to generate the phase signal P2, and the phase signal can be reset by the zero-crossing signal SZ and/or the feedback signal SFB. No. P2. The pulse generator 430 can be used to generate a space-time delay of the trigger signal TG2. The longer the space-time delay of the trigger signal TG2 is, the more the start time of the phase signal P1/PB is delayed, increasing the space time between the end of the phase signal P2 and the start of the phase signal P1/PB.

When the closed loop signal CLP is the low voltage VL, the phase circuit 808 will be disabled. When the closed loop signal CLP is the high voltage VH, the phase circuit 808 will be enabled, the flip-flop 443 can be triggered by the trigger signal TG2 to generate the phase signal PB, and the phase signal PB can be reset by the cut-off signal SP. The pulse generator 445 can be used to generate a space-time delay of the trigger signal TGB. The longer the space-time delay of the trigger signal TGB is, the more the start time of the phase signal PB is delayed, increasing the space time between the end of the phase signal PB and the start of the phase signal P1.

When the power converter 1 is in a light load state, the control circuit 800 can additionally set the pulse generators 330, 345, 430, and 445 to increase the space-time delays of the trigger signals TG1, TGA, TG2, and TGB, thereby increasing the number of switches 10 and 445. 20. The cut-off time (OFF time) of switch 30 and switch 40 to achieve the purpose of power saving.

Embodiments of the present invention are used to control the power converter 1 to operate in the non-regulated mode or the regulated mode to achieve ZVS and ZCS to avoid damage to the load, while reducing switching losses and enhancing system efficiency.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

200:Control method

S202 and S204: steps

Claims (26)

A power converter includes: a first switch including a control end and a first end for receiving an input voltage and a second end; a second switch including a control end and a first end, Coupled to the second terminal of the first switch and a second terminal; a third switch including a control terminal and a first terminal coupled to the second terminal of the second switch and a first terminal Two terminals; a fourth switch, including a control terminal, a first terminal, coupled to the second terminal of the third switch, and a second terminal, coupled to a ground terminal; a flying capacitor, including a A first terminal is coupled to the second terminal of the first switch, and a second terminal is coupled to the second terminal of the third switch; an inductor includes a first terminal coupled to the third switch. the second terminal of two switches, and a second terminal; an output capacitor, including a first terminal coupled to the second terminal of the inductor, for outputting an output voltage, and a second terminal coupled to at the ground terminal; and a control circuit coupled to the first terminal of the first switch, the control terminal of the first switch, the control terminal of the second switch, the control terminal of the third switch and The control end of the fourth switch is used to switch the first switch, the second switch, the third switch and the fourth switch according to a resonant frequency in a non-regulation mode, and in a regulation mode, The first switch, the second switch, the third switch and the fourth switch are switched according to an adjustment frequency exceeding the resonant frequency; wherein when the flying capacitor is coupled to the inductor, the flying capacitor and the inductor will form A resonant circuit with this resonant frequency. The power converter of claim 1, wherein when the input voltage is between a high voltage threshold and a low voltage threshold, the control circuit is used to execute the non-regulation mode, and when an inductor current of the inductor When it is 0, the first switch, the second switch, the third switch and the fourth switch are switched to generate a divided voltage of the input voltage as the output voltage. The power converter of claim 1, wherein the control circuit is used to switch the first switch, the third switch when an inductor current of the inductor flows from the second end of the inductor to the first end of the inductor. the second switch, the third switch and/or the fourth switch. The power converter of claim 1, wherein when the input voltage is less than a low voltage threshold, the power converter is used to perform a single-stage operation of the regulation mode, thereby regulating the output voltage to be less than or equal to the input voltage. The power converter of claim 4, wherein the control circuit is used to turn off the third switch and the third switch after an inductor current of the inductor reaches 0 and a first predetermined delay during the single-stage operation mode. Four switches. The power converter of claim 5, wherein the control circuit is used to turn on the first switch after turning off the third switch and the fourth switch and after a second predetermined delay in the single-stage operation mode. the second switch. The power converter of claim 1, wherein when the input voltage exceeds a high voltage threshold, the power converter is used to perform one of the two-stage operations of the regulation mode, thereby regulating the output voltage to be less than or equal to the half the input voltage. The power converter of claim 7, wherein in the two-stage operation mode: when the first switch and the third switch are turned on, the input voltage charges the flying capacitor and the output capacitor through the inductor; and When the second switch and the fourth switch are turned on, the flying capacitor charges the output capacitor through the inductor. The power converter of claim 1, wherein in the regulation mode, the control circuit is used to reduce the ON time of the first switch and the second switch. The power converter of claim 1, wherein the control circuit is used in the regulation mode to turn off the first switch, the second switch, the third switch and/or before an inductor current of the inductor reaches 0. Or that fourth switch. The power converter of claim 1, wherein the control circuit is used in the regulation mode to turn off the first switch, the second switch, the third switch and/or when an inductor current of the inductor reaches 0 Or that fourth switch. The power converter of claim 1, wherein the control circuit is used in the regulation mode to turn off the first switch, the second switch, the third switch and/or after an inductor current of the inductor reaches 0. Or that fourth switch. The power converter of claim 1, wherein the power converter operates in discontinuous conduction mode (DCM). The power converter of claim 1, wherein the control circuit includes: a first phase circuit for generating a first phase signal and a first trigger signal based on a starting signal, a zero-crossing signal and a feedback signal ; A second phase circuit, coupled to the first phase circuit, for generating a second phase signal and a second trigger signal based on the first trigger signal, a closed loop signal and a cut-off signal; a third phase a circuit coupled to the second phase circuit for generating a third phase signal and a third trigger based on the first trigger signal, the second trigger signal, the closed loop signal, the zero-crossing signal and the feedback signal signal; a fourth phase circuit, coupled to the third phase circuit and the first phase circuit, for generating a fourth phase signal and a fourth phase signal based on the third trigger signal, the closed loop signal and the cut-off signal. a trigger signal; and an initial circuit, coupled to the first phase circuit, the second phase circuit, the third phase circuit and the fourth phase circuit, for based on a mode signal, the closed loop signal, the second The trigger signal, the third trigger signal and the fourth trigger signal generate the start signal; a signal generation circuit is coupled to the first phase circuit, the second phase circuit, the third phase circuit and the fourth phase A circuit for generating a first switching signal, a second switching signal, and a third switching signal based on the first phase signal, the second phase signal, the third phase signal, the fourth phase signal, and the mode signal. and a fourth switch signal. The first switch signal, the second switch signal, the third switch signal and the fourth switch signal respectively switch the first switch, the second switch, the third switch and the fourth switch. switch; a feedback circuit coupled to the first phase circuit, the third phase circuit and the first end of the output capacitor, for controlling the first phase signal, the third phase signal, the output voltage and a The reference voltage generates the feedback signal; a state detection circuit coupled to the first terminal of the output capacitor and the first terminal of the inductor for generating a switching voltage based on the output voltage, a degaussing reference voltage and the first terminal of the inductor The zero-crossing signal and the cut-off signal; and a closed-loop circuit coupled to the status detection circuit, the feedback circuit, the first phase circuit and the third phase circuit, for controlling the zero-crossing signal, the feedback circuit signal, the first phase signal and the third phase signal to generate the closed loop signal. The power converter of claim 14, wherein: the first phase circuit includes: a first AND gate, including: a first input terminal for receiving the first phase signal; a second input terminal for to receive the zero-crossing signal; and an output terminal; a second AND gate, including: a first input terminal to receive the first phase signal; a second input terminal to receive the feedback signal; and a Output terminal; a first NOR gate, including: a first input terminal coupled to the output terminal of the first AND gate; a second input terminal coupled to the output terminal of the second AND gate; and an output terminal; a first flip-flop, including: a data input terminal for receiving a supply voltage; a clock terminal for receiving the start signal; a reset terminal coupled to the output terminal of the first NOR gate; an output terminal for outputting the first phase signal; and an inverting output terminal for outputting an inverse of the first phase signal. direction signal; and a first pulse generator, including: an input terminal for receiving the reverse signal of the first phase signal; and an output terminal for outputting the first trigger signal; the second phase The circuit includes: a third AND gate, including: a first input end for receiving the closed loop signal; a second input end for receiving the first trigger signal; and an output end; a first NAND The gate includes: a first input terminal for receiving the cut-off signal; a second input terminal for receiving the second phase signal; and an output terminal; a second flip-flop including: a data input terminal , used to receive the supply voltage; a clock terminal coupled to the output terminal of the third AND gate; a reset terminal coupled to the output terminal of the first NAND gate; an output terminal used to Output the second phase signal; and a reverse output terminal for outputting a reverse signal of the second phase signal; and a second pulse generator including: an input terminal for receiving the second phase the reverse signal of the signal; and an output terminal for outputting the second trigger signal; and The initial circuit includes: a first inverter, including: an input end for receiving the closed loop signal; and an output end; a fourth AND gate, including: a first input end for receiving the a fourth trigger signal; a second input terminal for receiving the closed loop signal; and an output terminal; a fifth AND gate, including: a first input terminal for receiving a reverse signal of the closed loop signal ; a second input terminal for receiving the third trigger signal; and an output terminal; a first OR gate, including: a first input terminal coupled to the output terminal of the fourth AND gate; a second input terminal, coupled to the output terminal of the fifth AND gate; and an output terminal; a second inverter, including: an input terminal for receiving the mode signal; and an output terminal for outputting the mode signal. a reverse signal; a sixth AND gate, including: a first input terminal coupled to the output terminal of the first OR gate; a second input terminal for receiving the reverse signal of the mode signal; and a Output terminal; a seventh and gate, including: a first input terminal for receiving the mode signal; a second input terminal for receiving the second trigger signal; and an output terminal; and a second OR gate, including: a first input terminal coupled to At the output end of the sixth AND gate; a second input end coupled to the output end of the seventh AND gate; and an output end for outputting the start signal. The power converter of claim 14, wherein: the third phase circuit includes: a first AND gate, including: a first input terminal for receiving the third phase signal; a second input terminal for to receive the zero-crossing signal; and an output terminal; a second AND gate, including: a first input terminal to receive the third phase signal; a second input terminal to receive the feedback signal; and a Output terminal; a first NOR gate, including: a first input terminal coupled to the output terminal of the first AND gate; a second input terminal coupled to the output terminal of the second AND gate; and an output terminal; a first inverter, including: an input terminal for receiving the closed loop signal; and An output terminal; a fourth AND gate, including: a first input terminal for receiving the second trigger signal; a second input terminal for receiving the closed loop signal; and an output terminal; a fifth AND The gate includes: a first input terminal coupled to the output terminal of the first inverter; a second input terminal for receiving the first trigger signal; and an output terminal; a first OR gate, It includes: a first input terminal coupled to the output terminal of the fourth AND gate; a second input terminal coupled to the output terminal of the fifth AND gate; and an output terminal; a first positive and negative The device includes: a data input terminal for receiving a supply voltage; a clock terminal coupled to the output terminal of the fourth AND gate; a reset terminal coupled to the output of the first NOR gate terminal; an output terminal for outputting the third phase signal; and a reverse output terminal for outputting a reverse signal of the third phase signal; and a first pulse generator including: an input terminal , for receiving the reverse signal of the third phase signal; and an output terminal for outputting the third trigger signal; and the fourth phase circuit includes: a third AND gate, including: a first input terminal for receiving the closed loop signal; a second input terminal for receiving the third trigger signal; and an output terminal; a first NAND gate, including: a first input terminal for to receive the cut-off signal; a second input terminal to receive the fourth phase signal; and an output terminal; a second flip-flop including: a data input terminal to receive the supply voltage; a clock terminal , coupled to the output terminal of the third AND gate; a reset terminal coupled to the output terminal of the first NAND gate; an output terminal for outputting the fourth phase signal; and a reverse an output terminal for outputting a reverse signal of the fourth phase signal; and a second pulse generator including: an input terminal for receiving the reverse signal of the fourth phase signal; and an output terminal , used to output the third trigger signal. The power converter of claim 14, wherein: the signal generating circuit includes: a first buffer, including: an input terminal for receiving the first phase signal; and an output terminal for outputting the first phase signal. First switching signal: a first inverter, including: an input terminal for receiving the mode signal: and An output terminal: a first AND gate, including: a first input terminal for receiving the third phase signal: a second input terminal coupled to the output terminal of the first inverter: and an output terminal: a second AND gate, including: a first input terminal for receiving the mode signal: a second input terminal for receiving the first phase signal: and an output terminal: a first OR gate, including : a first input terminal coupled to the output terminal of the first AND gate: a second input terminal coupled to the output terminal of the second AND gate: and an output terminal: a second buffer, It includes: an input terminal coupled to the output terminal of the first OR gate; and an output terminal for outputting the second switch signal; a second OR gate, including: a first input terminal for receiving The first phase signal: a second input terminal for receiving the second phase signal: a third input terminal for receiving the fourth phase signal: and an output terminal: a second inverter, including: An input terminal for receiving the mode signal: and an output terminal: A third AND gate, including: a first input terminal coupled to the output terminal of the second OR gate: a second input terminal coupled to the output terminal of the second inverter: and an output Terminal: a fourth AND gate, including: a first input terminal, used to receive the mode signal: a second input terminal, used to receive the second phase signal: and an output terminal: a third OR gate, including : a first input terminal coupled to the output terminal of the third AND gate: a second input terminal coupled to the output terminal of the fourth AND gate: and an output terminal: a third buffer, including : an input terminal coupled to the output terminal of the third OR gate: and an output terminal for outputting the third switch signal: a fourth OR gate, including: a first input terminal for receiving the The third phase signal: a second input terminal for receiving the second phase signal: a third input terminal for receiving the fourth phase signal: and an output terminal: a third inverter, including: a An input terminal for receiving the mode signal: and an output terminal: a fifth AND gate, including: a first input terminal coupled to the output terminal of the fourth OR gate: a second input terminal coupled to the output terminal of the third inverter: and an output terminal: a sixth AND gate, It includes: a first input terminal for receiving the mode signal: a second input terminal for receiving the second phase signal: and an output terminal: a fifth OR gate, including: a first input terminal, coupled The output terminal connected to the fifth AND gate: a second input terminal, the output terminal coupled to the sixth AND gate: and an output terminal: and a fourth buffer, including: an input terminal, coupled to The output terminal connected to the fifth OR gate: and an output terminal for outputting the fourth switch signal. The power converter of claim 14, wherein: the feedback circuit includes: a first NOR gate, including: a first input terminal for receiving the first phase signal: and a second input terminal for To receive the third phase signal: and an output terminal: a current source, including: a first terminal coupled to a power supply terminal for receiving a supply voltage: and a second terminal: A transistor including: a control terminal coupled to the output terminal of the first NOR gate; a first terminal coupled to the second terminal of the current source; and a second terminal coupled to A ground terminal: a first capacitor, including: a first terminal, coupled to the first terminal of the transistor: and a second terminal, coupled to the ground terminal: a first resistor, including: a first One end for receiving the output voltage: and a second end: a second resistor, including: a first end coupled to the second end of the first resistor: and a second end coupled to The ground terminal: a third resistor, including: a first terminal for receiving the reference voltage; and a second terminal: a fourth resistor, including: a first terminal coupled to the third resistor. Second terminal: and a second terminal: a switch, including: a control terminal for receiving the closed loop signal: a first terminal coupled to the second terminal of the fourth resistor: and a second terminal , coupled to the ground terminal: an error amplifier, including: An inverting input terminal coupled to the second terminal of the first resistor: a forward input terminal coupled to the second terminal of the third resistor: and an output terminal: a fifth resistor, including: A first terminal coupled to the output terminal of the error amplifier: and a second terminal: a second capacitor, including: a first terminal coupled to the second terminal of the first resistor: and a first terminal Two terminals, coupled to the ground terminal: and a comparator, including: a forward input terminal, coupled to the first terminal of the first capacitor: a reverse input terminal, coupled to the fifth resistor The first terminal: and an output terminal for outputting the feedback signal. The power converter as described in claim 14, wherein: the status detection circuit includes: a first comparator, including: a forward input terminal for receiving the switching voltage: and a reverse input terminal for Receive the output voltage: and an output terminal: a zero-crossing detector, including: an input terminal coupled to the output terminal of the first comparator; and an output terminal for outputting the zero-crossing signal; The second comparator contains: A forward input terminal is used to receive the switching voltage: a reverse input terminal is used to receive the degaussing reference voltage: and an output terminal is used to output a degaussing signal: a first pulse generator, including: consistent The energy terminal is used to receive a control signal: an input terminal is used to receive the degaussing signal: and an output terminal is: a first AND gate, including: a first input terminal is used to receive the degaussing signal: a second The input terminal is coupled to the output terminal of the first pulse generator: and an output terminal is used to output the cut-off signal: and the closed loop circuit includes: a first inverter, including: an input terminal , for receiving the zero-crossing signal: and an output terminal for outputting an inverse signal of the zero-crossing signal: a first OR gate, including: a first input terminal for receiving the first phase signal: a second input terminal for receiving the third phase signal: and an output terminal: a second pulse generator including: an input terminal coupled to the output terminal of the first OR gate: and an output terminal for outputting a first pulse signal: a second inverter including: an input terminal for receiving the first pulse signal: and an output terminal for outputting a reset signal: and a flip-flop, including: a data input terminal for receiving the reverse signal of the zero-crossing signal: a clock terminal for receiving the feedback signal: a reversal A set terminal is used to receive the reset signal: and an output terminal is used to output the closed loop signal. A control method for a power converter. The power converter includes a first switch, a second switch, a third switch, a fourth switch, a flying capacitor, an inductor, an output capacitor and a control circuit. The first switch is A switch includes a control end, a first end for receiving an input voltage, and a second end. The second switch includes a control end, a first end, and is coupled to the second end of the first switch. terminal, and a second terminal, the third switch includes a control terminal, a first terminal coupled to the second terminal of the second switch, and a second terminal, the fourth switch includes a control terminal, A first terminal is coupled to the second terminal of the third switch, and a second terminal is coupled to a ground terminal. The flying capacitor includes a first terminal coupled to the third terminal of the first switch. Two terminals and a second terminal are coupled to the second terminal of the third switch. The inductor includes a first terminal coupled to the second terminal of the second switch and a second terminal. The output capacitor includes a first terminal coupled to the second terminal of the inductor for outputting an output voltage, and a second terminal coupled to the ground terminal, and the control circuit is coupled to the first switch. The first end, the control end of the first switch, the control end of the second switch, the control end of the third switch and the control end of the fourth switch, the control method includes: in a non- In the adjustment mode, the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to a resonant frequency; and in an adjustment mode, the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to an adjustment exceeding the resonant frequency. Frequency switching of this section A switch, the second switch, the third switch and the fourth switch; when the flying capacitor is coupled to the inductor, the flying capacitor and the inductor will form a resonant circuit with the resonant frequency. The method of claim 20, wherein the control circuit is used to switch the first switch and the second switch when an inductor current of the inductor flows from the second end of the inductor to the first end of the inductor. , the third switch and/or the fourth switch. The method of claim 20, wherein when the input voltage is less than a low voltage threshold, the power converter is used to perform a single-stage operation of the regulation mode, thereby regulating the output voltage to be less than or equal to the input voltage ; The control circuit switches the first switch, the second switch, the third switch and the fourth switch according to the adjustment frequency exceeding the resonant frequency, including: when an inductor current of the inductor reaches 0 and passes through a first predetermined After the time, the control circuit turns off the third switch and the fourth switch; and after turning off the third switch and the fourth switch and a second predetermined time passes, the control circuit turns on the first switch and the second switch. The method of claim 20, wherein when the input voltage exceeds a high voltage threshold, the power converter is used to perform a two-stage operation of the regulation mode, thereby regulating the output voltage to be less than or equal to the input voltage. One-half; the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to the adjustment frequency exceeding the resonant frequency, including: when the first switch and the third switch are turned on, The input voltage passes through the inductor to the flying current The capacitor and the output capacitor are charged; and when the second switch and the fourth switch are turned on, the flying capacitor charges the output capacitor through the inductor. The method of claim 20, wherein the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to the adjustment frequency exceeding the resonant frequency, including: the control circuit switches the inductor Before an inductor current reaches 0, the first switch, the second switch, the third switch and/or the fourth switch are turned off. The method of claim 20, wherein the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to the adjustment frequency exceeding the resonant frequency, including: the control circuit switches the inductor When an inductor current reaches 0, the first switch, the second switch, the third switch and/or the fourth switch are turned off. The method of claim 20, wherein the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to the adjustment frequency exceeding the resonant frequency, including: the control circuit switches the inductor After an inductor current reaches 0, the first switch, the second switch, the third switch and/or the fourth switch are turned off.

Images