CN103887952A - Output voltage dynamic sampling circuit in alternating current-direct current converter - Google Patents
Output voltage dynamic sampling circuit in alternating current-direct current converter Download PDFInfo
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- CN103887952A CN103887952A CN201410160556.7A CN201410160556A CN103887952A CN 103887952 A CN103887952 A CN 103887952A CN 201410160556 A CN201410160556 A CN 201410160556A CN 103887952 A CN103887952 A CN 103887952A
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Abstract
The invention relates to an output voltage dynamic sampling circuit in an alternating current-direct current converter. The circuit comprises an oscillator, a first sampling holding unit, a second sampling holding unit, a wire or unit and a third sampling holding unit. The first sampling holding unit is used for receiving a first pulse oscillating signal and sampling an output voltage signal to obtain a first sampling voltage signal when the first pulse oscillating signal is high electric level. The second sampling holding unit is used for receiving a second pulse oscillating signal and sampling an output voltage signal to obtain a second sampling voltage signal when the second pulse oscillating signal is high electric level. The a wire or unit is used for receiving the first sampling voltage signal and the second sampling voltage signal and outputting a third sampling voltage signal. The third sampling holding unit is used for receiving and sampling the third sampling voltage signal to obtain a fourth sampling voltage signal. By means of the sampling circuit, output voltages are detected accurately in any load conditions.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, be specifically related to the output voltage dynamic sampling circuit in AC-DC converter.
Background technology
In AC-DC converter circuit, can realize by the voltage of sampling transformer inductance the detection of output voltage, and main inductive drop can assist winding to be transferred to control chip by transformer.Fig. 1 is the structure chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter of the prior art.As shown in Figure 1, resistance R 1 represent the series connection dead resistance of secondary winding and the dead resistance of connecting of output lead and.Under different output load currents, the voltage of secondary winding is distinguishing.Fig. 2 be in prior art under different output load currents the waveform comparison diagram of the output voltage in AC-DC converter.As can be seen from Figure 2,, due to the difference of load, within the degaussing time (Tdmg), the output current of secondary winding is also different, causes the pressure drop difference in resistance R 1, finally makes the waveform difference at FB pin.But in the time that the degaussing time finishes, the electric current of secondary winding is reduced to 0A, 0V is also reduced in the pressure drop in resistance R 1.Therefore, ideally, control chip should carry out the sampling of output voltage before the secondary winding degaussing time finishes.
Summary of the invention
The object of the invention is for the deficiencies in the prior art, in AC-DC converter circuit, propose a kind of circuit of before the degaussing time finishes, output voltage being sampled, thereby made control chip can compare accurate detection to output voltage under any loading condition.
For achieving the above object, the invention provides the output voltage dynamic sampling circuit in a kind of AC-DC converter, described circuit comprises:
Oscillator, for generation of the first impulse oscillation signal and the second impulse oscillation signal;
The first sample holding unit, is connected with described oscillator, and for receiving described the first impulse oscillation signal, the described output voltage signal of sampling in the time that described the first impulse oscillation signal is high level, obtains the first sampled voltage signal;
The second sample holding unit, is connected with described oscillator, and for receiving described the second impulse oscillation signal, the described output voltage signal of sampling in the time that described the second impulse oscillation signal is high level, obtains the second sampled voltage signal;
Line or unit, be connected with the second sample holding unit with described the first sample holding unit respectively, for receiving described the first sampled voltage signal and described the second sampled voltage signal and exporting the 3rd sampled voltage signal;
The 3rd sample holding unit, is connected with described line or unit, for receiving and described the 3rd sampled voltage signal being sampled and obtained the 4th sampled voltage signal.
Preferably, described oscillator comprises the first current source, the second current source, the first switch, second switch, electric capacity, the first comparator, the second comparator, the 3rd comparator, rest-set flip-flop, inverter, the first d type flip flop, the second d type flip flop, the first three value and gate and the second three value and gate;
Described second switch is connected with described the second current source and ground connection, described the first current source is connected with described the first switch and accesses respectively the positive input of described the first comparator and the positive input of described the second comparator, described electric capacity is connected between described the first switch and the positive input of described the first comparator, the negative input of described the first comparator accesses the first compare threshold, the output of described the first comparator is connected with the R of described rest-set flip-flop end, the negative input of described the second comparator accesses the second compare threshold, the output of described the second comparator is connected with the S of described rest-set flip-flop end, the output of described rest-set flip-flop is connected with described the first d type flip flop, the output of described rest-set flip-flop is connected with described the second d type flip flop after via described inverter, the output of described the first d type flip flop, the output of the output of described rest-set flip-flop and described the 3rd comparator is connected with described the first three value and gate respectively, the output of described the second d type flip flop, the output of the output of described rest-set flip-flop and described the 3rd comparator is connected with described the second three value and gate respectively,
When described the first switch closure, described second switch disconnects, described the first current source charges to described electric capacity, when the voltage at described electric capacity two ends rises to described the first compare threshold, described the first comparator output high level makes the output of described rest-set flip-flop be set to low level, thereby controlling described the first switch disconnects, described second switch closure, described the second current source is described capacitor discharge, the voltage drop at described electric capacity two ends during to described the second compare threshold described in the second comparator output high level the output of described rest-set flip-flop is reset as high level, thereby control described the first switch closure, described second switch disconnects.
Preferably, described line or unit comprise the first operational amplifier, the second operational amplifier, a NMOS pipe, the 2nd NMOS pipe, the 3rd current source, the 4th current source and power supply;
The positive input of described the first operational amplifier accesses described the first sampled voltage signal, the source electrode of the negative input of described the first operational amplifier and a described NMOS pipe joins via described the 3rd current source ground connection, the positive input of described the second operational amplifier accesses described the second sampled voltage signal, the source electrode of the negative input of described the second operational amplifier and described the 2nd NMOS pipe joins via described the 4th current source ground connection, the drain electrode of the drain electrode of a described NMOS pipe and described the 2nd NMOS pipe connects respectively power supply, the source electrode of the source electrode of a described NMOS pipe and described the 2nd NMOS pipe joins and as the output of described line or unit, thereby export described the 3rd sampled voltage signal,
In the time that described the first sampled voltage signal is greater than described the second sampled voltage signal, the grid voltage of a described NMOS pipe is greater than the grid voltage of described the second metal-oxide-semiconductor, the source electrode of a described NMOS pipe drives described the 3rd current source and described the 4th current source to make described NMOS pipe conducting a 2nd NMOS pipe cut-off simultaneously, makes described the 3rd sampled voltage signal equal described the first sampled voltage signal;
In the time that described the first sampled voltage signal is less than described the second sampled voltage signal, the grid voltage of a described NMOS pipe is less than the grid voltage of described the second metal-oxide-semiconductor, the source electrode of a described NMOS pipe drives described the 3rd current source and described the 4th current source to make described NMOS pipe cut-off a 2nd NMOS pipe conducting simultaneously, makes described the 3rd sampled voltage signal equal described the second sampled voltage signal.
Preferably, the phase phasic difference half period of the phase place of described the first impulse oscillation signal and described the second impulse oscillation signal.
Preferably, described the first compare threshold is greater than described the second compare threshold.
Output voltage dynamic sampling circuit in a kind of AC-DC converter providing by the embodiment of the present invention, the oscillator of this circuit produces two impulse oscillation signals, control respectively the first sample holding unit and the second sample holding unit, output voltage in AC-DC converter obtains the first sampled voltage signal and the second sampled voltage signal by the first sample holding unit and the second sample holding unit, the first sampled voltage signal and the second sampled voltage signal obtain the 3rd sampled voltage signal by line or unit, the 3rd sampled voltage signal is sampled and is obtained the 4th sampled voltage signal by the 3rd sample holding unit under control signal, thereby realize the sampling to output voltage before the degaussing time finishes, make control chip can compare accurate detection to output voltage under any loading condition.
Brief description of the drawings
Fig. 1 is the structure chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter of the prior art;
Fig. 2 be in prior art under different output load currents the waveform comparison diagram of the output voltage in AC-DC converter;
The structure chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter that Fig. 3 provides for the embodiment of the present invention;
The sequential chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter that Fig. 4 provides for the embodiment of the present invention;
The structural representation of the pierce circuit that Fig. 5 provides for the embodiment of the present invention;
The sequential chart of the pierce circuit that Fig. 6 provides for the embodiment of the present invention;
The line that Fig. 7 provides for the embodiment of the present invention or the structural representation of unit.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
The present invention proposes a kind of circuit of before the degaussing time finishes, output voltage being sampled, thereby makes control chip can compare accurate detection to output voltage under any loading condition.
The structure chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter that Fig. 3 provides for the embodiment of the present invention, as shown in Figure 3, this output voltage dynamic sampling circuit comprises: oscillator U1, the first sample holding unit U21, the second sample holding unit U22, line or unit U3 and the 3rd sample holding unit U23.
The input of oscillator U1 is the voltage signal of the FB node shown in Fig. 1, and oscillator U1 is for generation of the first impulse oscillation signal CLK1 and the second impulse oscillation signal CLK2.Due to the negative feedback of whole Switching Power Supply, the high level of FB voltage waveform finally can approximate another input of error amplifier in Fig. 1, i.e. reference voltage Vref.Therefore oscillator U1 is inner can compare FB voltage waveform with a reference voltage (Vref-Voff) that is less than Vref voltage, the scope that wherein Voff can select is 0.01V-Vref: in the time that FB voltage waveform is higher than (Vref-Voff), output the first impulse oscillation signal CLK1 and the second impulse oscillation signal CLK2 of oscillator U1 are the impulse oscillation signal of two phase phasic difference half period; In the time that FB voltage waveform is lower than (Vref-Voff), output the first impulse oscillation signal CLK1 and the second impulse oscillation signal CLK2 of oscillator U1 are logic low.
The sequential chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter that Fig. 4 provides for the embodiment of the present invention, as shown in Figure 4.At FB voltage, during higher than (Vref-Voff), the first impulse oscillation signal CLK1 is high level at once, and the time of high level is t1, and the low level time is (t1+2*t2), and therefore the pulse period is (2*t1+2*t2); The second impulse oscillation signal CLK2 is high level after time delay (t1+t2), and the time of high level is t1, and the low level time is (t1+2*t2), and therefore the pulse period is (2*t1+2*t2).The delay of the rising edge of CLK2 and the rising edge of CLK1 is (t1+t2), therefore phase phasic difference half period.
The first sample holding unit U21 is connected with oscillator U1, the input of the first sample holding unit U21 is respectively FB and the first impulse oscillation signal CLK1, be output as the first sampled voltage signal VFBA, when the first impulse oscillation signal CLK1 is that logic is when high, the magnitude of voltage of VFBA sampling FB, in the time that the first pulse signal CLK1 is logic low, VFBA keeps last sampled value;
The second sample holding unit U22 is connected with oscillator U1, the input of the second sample holding unit U22 is respectively FB and the second impulse oscillation signal CLK2, be output as the second sampled voltage signal VFBB, when impulse oscillation signal CLK2 is that logic is when high, the magnitude of voltage of VFBB sampling FB, in the time that pulse signal CLK2 is logic low, VFBB keeps last sampled value.
Line or unit U3 are connected with the second sample holding unit U22 with described the first sample holding unit U21 respectively, the input of line or unit U3 is the first sampled voltage signal VFBA and the second sampled voltage signal VFBB, and VFBA and VFBB are carried out to line or processing and export the 3rd sampled voltage signal VFBC.Particularly, the 3rd sampled voltage signal VFBC is magnitude of voltage maximum in the output VFBA of line or unit and two voltages of VFBB.
The 3rd sample holding unit U23 is connected with line or unit U3, and the 3rd sampled voltage signal VFBC is sampled and obtains the 4th sampled voltage signal VFB.Concrete, the input of the 3rd sample holding unit U23 is the Gate signal in the 3rd sampled voltage signal VFBC and Fig. 1, and the voltage signal of the VFB node in being output as shown in Fig. 1, with an input of error amplifier.When Gate signal is logic when high, the magnitude of voltage of VFB sampling VFBC, in the time that Gate signal is logic low, VFB keeps last sampled value.
Further, the specific implementation of oscillator U1 as shown in Figure 5.Oscillator U1 comprises: the first current source I1, the second current source I2, the first switch SW 1, second switch SW2, capacitor C 1, the first comparator, the second comparator, the 3rd comparator, rest-set flip-flop, inverter, the first d type flip flop, the second d type flip flop, the first three value and gate AND1 and the second three value and gate AND2.
Second switch SW2 is connected with the second current source I2 and ground connection, the first current source I1 is connected with the first switch SW 1 and accesses respectively the positive input of the first comparator and the positive input of the second comparator, capacitor C 1 is connected between the first switch SW 1 and the positive input of the first comparator, the negative input of the first comparator accesses the first compare threshold VthH, the output of the first comparator is connected with the R of rest-set flip-flop end, the negative input of the second comparator accesses the second compare threshold VthL, the output of the second comparator is connected with the S of rest-set flip-flop end, the output of rest-set flip-flop is connected with the first d type flip flop, the output of rest-set flip-flop is connected with the second d type flip flop after via inverter, the output of the first d type flip flop, the output of the output of described rest-set flip-flop and the 3rd comparator is connected with the first three value and gate AND1 respectively, the output of the second d type flip flop, the output of the output of rest-set flip-flop and the 3rd comparator is connected with the second three value and gate AND2 respectively.
Wherein, the first current source I1, the second current source I2, the first switch SW 1, second switch SW2, capacitor C 1, the first comparator, the second comparator, and rest-set flip-flop has formed traditional oscillator.
The sequential chart of the pierce circuit that Fig. 6 provides for the embodiment of the present invention.As shown in Figure 6, when the first switch SW 1 closure, when the 2nd SW2 disconnects, the first current source I1 charges to capacitor C 1, the voltage at capacitor C 1 two ends rises, namely sawtooth waveforms Saw rises, in the time rising to the first compare threshold VthH of the first comparator, the first comparator output high level, the output Q1 of rest-set flip-flop is reset as low level, thereby control the first switch SW 1 and disconnect second switch SW2 closure, the second current source I2 is that capacitor C 1 is discharged, in the time that the voltage sawtooth waveforms Saw at capacitor C 1 two ends drops to the second compare threshold VthL of the second comparator, the second comparator output high level, the output Q1 of rest-set flip-flop is set to high level, thereby controlling the first switch SW 1 closed second switch SW2 disconnects.The output Q1 that makes and so forth rest-set flip-flop is oscillating pulse wave.Q1 is that time t1 and the low level time t2 of high level is respectively:
Oscillating pulse wave Q1 and the reverse signal of Q1 that produces via inverter, respectively by the first d type flip flop and the second d type flip flop frequency division, produce two fractional frequency signal Q2 and Q3.
The 3rd comparator is compared the voltage waveform of FB with threshold value (Vref-Voff), produce logic control signal VFBHigh.In the time that FB is lower than threshold value (Vref-Voff), VFBHigh is low, and output the first impulse oscillation signal CLK1 and the second impulse oscillation signal CLK2 of the first three value and gate AND1 and the second three value and gate AND2 are low; In the time that FB is higher than threshold value (Vref-Voff), VFBHigh is low, output the first impulse oscillation signal CLK1 of the first three value and gate AND1 be Q1 and Q2 with, output the second impulse oscillation signal CLK2 of the second three value and gate AND2 be Q1 and Q3 with.
Further, as shown in Figure 7, line or unit U3 comprise the specific implementation of line or unit U3: line or unit comprise the first operational amplifier, the second operational amplifier, a NMOS pipe NM1, the 2nd NMOS pipe NM2, the 3rd current source I3 and the 4th current source I4.
The positive input of the first operational amplifier accesses the first sampled voltage signal VFBA, the source electrode of the negative input of the first operational amplifier and NMOS pipe NM1 joins via the 3rd current source I3 ground connection, the positive input of the second operational amplifier accesses the second sampled voltage signal VFBB, the source electrode of the negative input of the second operational amplifier and the 2nd NMOS pipe NM2 joins via the 4th current source I4 ground connection, the drain electrode of the drain electrode of the one NMOS pipe NM1 and the 2nd NMOS pipe NM2 connects respectively power supply, the source electrode of the source electrode of the one NMOS pipe NM1 and the 2nd NMOS pipe NM2 joins and as output the 3rd sampled voltage signal VFBC of line or unit U3.
The source shorted formation gain of the negative input of the first operational amplifier and NMOS pipe NM1 is 1 amplifier, and positive input is connected with the first sampled voltage signal VFBA in Fig. 3.Operational amplifier drives the class A amplifier being made up of a NMOS pipe NM1 and the 3rd current source I3.
Equally, the source shorted formation gain of the negative input of the second operational amplifier and the 2nd NMOS pipe NM2 is 1 amplifier, and positive input is connected with the second sampled voltage signal VFBB in Fig. 3.Operational amplifier drives the class A amplifier being made up of the 2nd NMOS pipe NMOS pipe NM2 and the 4th current source I4.
The class A amplifier that the one NMOS pipe NM1 and the 3rd current source I3 form has larger high level driving force, with the low level driving force that is subject to the 3rd current source I3 restriction, the class A amplifier that the 2nd NMOS pipe NM2 and the 4th current source I4 form has larger high level driving force equally, and is subject to the low level driving force of the 4th current source I4 restriction.As shown in Figure 7, when the source shorted of NM1 and NM2 to together with and while being connected to VFBC, the voltage of VFBC determines by the ceiling voltage of VFBA and VFBB, " line or " function of Here it is line or unit.For example, in the time of VFBA>VFBB, the grid voltage of NM1 is greater than the grid voltage of NM2, the source electrode of NM1 drive current source I3 and I4 simultaneously so, NM1 conducting, makes VFBC=VFBA, and the negative input voltage of the second operational amplifier equals VFBA and is greater than VFBB, therefore the output of the second operational amplifier is lower, makes NM2 cut-off.Otherwise in the time of VFBB>VFBA, the grid voltage of NM2 is greater than the grid voltage of NM1, the source electrode of NM2 drive current source I3 and I4 simultaneously so, NM2 conducting, make VFBC=VFBB, and the negative input voltage of the first operational amplifier equals VFBB and is greater than VFBA, therefore the output of the first operational amplifier is lower, makes NM1 cut-off.
The embodiment of the present invention proposes a kind of circuit of before the degaussing time finishes, output voltage being sampled, comprising: oscillator produces two impulse oscillation signals and controls respectively two sample holding units, these two sample holding units are sampled and are obtained two sampled signals output voltage respectively, these two sampled signals obtain the 3rd sampled voltage signal by line or unit again, the final sampled voltage that the 3rd sampled voltage signal obtains output voltage to sample by a sample holding unit again, thereby make control chip can compare accurate detection to output voltage under any loading condition.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only the specific embodiment of the present invention; the protection range being not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (5)
1. the output voltage dynamic sampling circuit in AC-DC converter, is characterized in that, described circuit comprises:
Oscillator, for generation of the first impulse oscillation signal and the second impulse oscillation signal;
The first sample holding unit, is connected with described oscillator, and for receiving described the first impulse oscillation signal, the described output voltage signal of sampling in the time that described the first impulse oscillation signal is high level, obtains the first sampled voltage signal;
The second sample holding unit, is connected with described oscillator, and for receiving described the second impulse oscillation signal, the described output voltage signal of sampling in the time that described the second impulse oscillation signal is high level, obtains the second sampled voltage signal;
Line or unit, be connected with the second sample holding unit with described the first sample holding unit respectively, for receiving described the first sampled voltage signal and described the second sampled voltage signal and exporting the 3rd sampled voltage signal;
The 3rd sample holding unit, is connected with described line or unit, for receiving and described the 3rd sampled voltage signal being sampled and obtained the 4th sampled voltage signal.
2. the output voltage dynamic sampling circuit in AC-DC converter according to claim 1, it is characterized in that, described oscillator comprises the first current source, the second current source, the first switch, second switch, electric capacity, the first comparator, the second comparator, the 3rd comparator, rest-set flip-flop, inverter, the first d type flip flop, the second d type flip flop, the first three value and gate and the second three value and gate;
Described the first current source is connected with described the first switch and accesses respectively the positive input of described the first comparator and the positive input of described the second comparator, described electric capacity is connected between described the first switch and the positive input of described the first comparator, the negative input of described the first comparator accesses the first compare threshold, the output of described the first comparator is connected with the R of described rest-set flip-flop end, the negative input of described the second comparator accesses the second compare threshold, the output of described the second comparator is connected with the S of described rest-set flip-flop end, the output of described rest-set flip-flop is connected with described the first d type flip flop, the output of described rest-set flip-flop is connected with described the second d type flip flop after via described inverter, the output of described the first d type flip flop, the output of the output of described rest-set flip-flop and described the 3rd comparator is connected with described the first three value and gate respectively, the output of described the second d type flip flop, the output of the output of described rest-set flip-flop and described the 3rd comparator is connected with described the second three value and gate respectively,
When described the first switch closure, described second switch disconnects, described the first current source charges to described electric capacity, when the voltage at described electric capacity two ends rises to described the first compare threshold, described the first comparator output high level makes the output of described rest-set flip-flop be set to low level, thereby controlling described the first switch disconnects, described second switch closure, described the second current source is described capacitor discharge, the voltage drop at described electric capacity two ends during to described the second compare threshold described in the second comparator output high level the output of described rest-set flip-flop is reset as high level, thereby control described the first switch closure, described second switch disconnects.
3. the output voltage dynamic sampling circuit in AC-DC converter according to claim 1, it is characterized in that, described line or unit comprise the first operational amplifier, the second operational amplifier, a NMOS pipe, the 2nd NMOS pipe, the 3rd current source, the 4th current source and power supply;
The positive input of described the first operational amplifier accesses described the first sampled voltage signal, the source electrode of the negative input of described the first operational amplifier and a described NMOS pipe joins via described the 3rd current source ground connection, the positive input of described the second operational amplifier accesses described the second sampled voltage signal, the source electrode of the negative input of described the second operational amplifier and described the 2nd NMOS pipe joins via described the 4th current source ground connection, the drain electrode of the drain electrode of a described NMOS pipe and described the 2nd NMOS pipe connects respectively power supply, the source electrode of the source electrode of a described NMOS pipe and described the 2nd NMOS pipe joins and as the output of described line or unit, thereby export described the 3rd sampled voltage signal,
In the time that described the first sampled voltage signal is greater than described the second sampled voltage signal, the grid voltage of a described NMOS pipe is greater than the grid voltage of described the second metal-oxide-semiconductor, the source electrode of a described NMOS pipe drives described the 3rd current source and described the 4th current source to make described NMOS pipe conducting a 2nd NMOS pipe cut-off simultaneously, makes described the 3rd sampled voltage signal equal described the first sampled voltage signal;
In the time that described the first sampled voltage signal is less than described the second sampled voltage signal, the grid voltage of a described NMOS pipe is less than the grid voltage of described the second metal-oxide-semiconductor, the source electrode of a described NMOS pipe drives described the 3rd current source and described the 4th current source to make described NMOS pipe cut-off a 2nd NMOS pipe conducting simultaneously, makes described the 3rd sampled voltage signal equal described the second sampled voltage signal.
4. the output voltage dynamic sampling circuit in AC-DC converter according to claim 1, is characterized in that, the phase phasic difference half period of the phase place of described the first impulse oscillation signal and described the second impulse oscillation signal.
5. the output voltage dynamic sampling circuit in AC-DC converter according to claim 2, is characterized in that, described the first compare threshold is greater than described the second compare threshold.
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| CN201410160556.7A CN103887952A (en) | 2014-04-21 | 2014-04-21 | Output voltage dynamic sampling circuit in alternating current-direct current converter |
| CN201410364898.0A CN104143928B (en) | 2014-04-21 | 2014-07-29 | Output voltage dynamic sampling circuit in AC-DC converter |
| CN201420422108.5U CN204046448U (en) | 2014-04-21 | 2014-07-29 | Output voltage dynamic sampling circuit in AC-DC converter |
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| CN201410364898.0A Active CN104143928B (en) | 2014-04-21 | 2014-07-29 | Output voltage dynamic sampling circuit in AC-DC converter |
| CN201420422108.5U Active CN204046448U (en) | 2014-04-21 | 2014-07-29 | Output voltage dynamic sampling circuit in AC-DC converter |
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| CN103887952A (en) * | 2014-04-21 | 2014-06-25 | 美芯晟科技（北京）有限公司 | Output voltage dynamic sampling circuit in alternating current-direct current converter |
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| TWI436190B (en) * | 2010-09-16 | 2014-05-01 | System General Corp | Correction circuit, correction apparatus and correction method for power converter |
| CN103107688B (en) * | 2013-02-25 | 2016-12-28 | 昂宝电子（上海）有限公司 | The system and method for the live signal sampling in power converting system |
| CN103887952A (en) * | 2014-04-21 | 2014-06-25 | 美芯晟科技（北京）有限公司 | Output voltage dynamic sampling circuit in alternating current-direct current converter |
-
2014
- 2014-04-21 CN CN201410160556.7A patent/CN103887952A/en active Pending
- 2014-07-29 CN CN201410364898.0A patent/CN104143928B/en active Active
- 2014-07-29 CN CN201420422108.5U patent/CN204046448U/en active Active
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| CN105425008B (en) * | 2015-10-30 | 2018-06-12 | 张良 | Internet of Things high sensitivity magnetic senser sampling circuit |
| CN105915045A (en) * | 2016-03-16 | 2016-08-31 | 四川长虹电器股份有限公司 | Variable-frequency air conditioner PFC control method based on IGBT ringing time |
| CN105915045B (en) * | 2016-03-16 | 2018-10-19 | 四川长虹电器股份有限公司 | Convertible frequency air-conditioner PFC control methods based on IGBT ring times |
| CN112379153A (en) * | 2020-10-30 | 2021-02-19 | 阳光电源股份有限公司 | Direct current oscillation detection circuit, direct current arc detection circuit and inverter |
| CN112379153B (en) * | 2020-10-30 | 2023-05-26 | 阳光电源股份有限公司 | Direct current oscillation detection circuit, direct current arc detection circuit and inverter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104143928A (en) | 2014-11-12 |
| CN204046448U (en) | 2014-12-24 |
| CN104143928B (en) | 2017-09-12 |
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Application publication date: 20140625 |