CN106849915A - A kind of programmable clock phase-shift circuit - Google Patents
A kind of programmable clock phase-shift circuit Download PDFInfo
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- CN106849915A CN106849915A CN201611241208.8A CN201611241208A CN106849915A CN 106849915 A CN106849915 A CN 106849915A CN 201611241208 A CN201611241208 A CN 201611241208A CN 106849915 A CN106849915 A CN 106849915A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Abstract
The invention discloses a kind of programmable clock phase-shift circuit, belong to electronic circuit technology field.The clock phase-shift circuit, electric current in pseudo- phase inverter on clock signal link is adjusted by programming Control, so as to control the integrating capacitor discharge and recharge time, again by the positive feedback effect of the first Schmidt trigger SMIT1 and the second Schmidt trigger SMIT2, accelerate the adjustment to rising or falling edge, finally realize the adjustment of the first puppet phase inverter INVW1 and the second puppet phase inverter INVW2 to input clock signal phase；Only make simple programming, you can the charging current of different proportion is provided for electric capacity, it is ensured that the precision of transmission, while greatly reducing the expense and circuit design difficulty of chip area, save circuit power consumption.Clock is capable of achieving from 0 ° to 315 °, step-length is 45 ° of phase shift, totally 8 adjustment of phase shift, most quickly meets the optimum apjustment timing position requirement of late-class circuit.
Description
Technical field
The present invention relates to a kind of programmable clock phase-shift circuit, and in particular to one kind can be by three logical signals, soon
From 0 ° to 315 °, step-length is 45 ° of clock phase-shift circuit, belongs to technical field of integrated circuits for fast programming realization phase shift.
Background technology
In semiconductor integrated circuit application field, particularly analog-digital blended signal chip circuit, numeral output generally exists
The trailing edge of output clock CLKOUT or rising edge saltus step simultaneously, therefore output number can be locked with trailing edge or rising edge
According to.For example, in production line analog-digital converter, when locking data is exported, to obtain enough rise and fall times, it is necessary to phase
Phase shift is carried out to CLKOUT signals to data output bit, to meet the sample requirement of rear class FPGA circuitry, this is referred to as optimum apjustment
The position of sequential.It is final to obtain by complicated frequency dividing delay process generally with a reference clock signal when chip is realized
To heterogeneous output clock, the output driving circuit of multistage and the logic selection circuit of complexity are then recycled, by a plurality of special
Wiring, most multi-phase clock is exported to late-class circuit at last.
During transmission multi-phase clock, in order to transmit the output clock of out of phase respectively, it is necessary to design different phase-shift capacitors
Array and multiple transmission special circuits, this considerably increases chip layout area.Meanwhile, if transmission line distance is more long, or
Transmission path gap between person each phase shift is larger, and output clock transfer interference etc. can be caused between other signals
There is larger time lag between the clock phase shift of each phase.When output clock frequency is higher at that time, each phase is resulted even in
The clock duty cycle of shifting is distorted, so as to cannot ensure to export the normal locking data of clock, causes signal acquisition to occur losing
Code or error code.
For working frequency analog-digital converter higher, the matching to output clock and late-class circuit is required more
Strictly, it is therefore necessary to which a clock phase-shift circuit for phase-adjustable to be provided, trailing edge or rising are utilized to match late-class circuit
Along the accurate, requirement of quick lock in data, all kinds of non-ideal characteristics are overcome to data acquisition caused by the interference of clock signal
Mistake.
The content of the invention
The technology of the present invention solve problem：Overcome not enough present in existing clock phase-shift circuit technology, there is provided a kind of
Programmable clock phase-shift circuit, is encoded using three bit digital logic control signals, the adjustment of multiple clock phase shifts is realized, with full
The position of the sufficient optimal sequential adjustment of rear class.
The present invention solve technical scheme be：A kind of programmable clock phase-shift circuit, the circuit includes：Control modulus of conversion
Output module LA is amplified in block CTRL_TR, current encoded module I CODE, phase-adjusting circuit and latch, wherein：
Input control modular converter CTRL_TR, receives the first phase shift logic control signal CTRL1 and second of outside input
Phase shift logic control signal CTRL2, encode and obtains voltage control signal P1, P2, P3 and send to current encoded module
ICODE；
Current encoded module I CODE, receives the current signal I0 of current input terminal NIB inputs, shunts it to parallel connection even
Three current sources for connecing, according to voltage control signal P1, P2, P3 control being switched on and off for internal three current sources respectively, produce
Raw reference current I1, I2, I3；
Phase-adjusting circuit, including the second phase inverter INV2, the first pseudo- phase inverter INVW1, the first Schmidt trigger
SMIT1, the second pseudo- phase inverter INVW2, the second Schmidt trigger SMIT1 and the 3rd phase inverter INV3, metal-oxide-semiconductor MN61 and
MN62；Metal-oxide-semiconductor MN61 and MN62 source electrode and drain electrode short circuit constitute integrating capacitor；The clock signal of outside input is divided into two-way,
The second phase inverter INV2, the first puppet phase inverter INVW1 and the first Schmidt trigger SMIT1 are sequentially connected all the way and are latched amplify
The P ends of output module LA；First pseudo- phase inverter INVW1 output ends connect the grid of metal-oxide-semiconductor MN61 simultaneously；Clock signal it is another
Road is sequentially connected the second pseudo- phase inverter INVW2, the second Schmidt trigger SMIT2, the 3rd phase inverter INV3 and latches amplifies defeated
Go out the N-terminal of module LA, the output end of the second pseudo- phase inverter INVW2 connects the grid of metal-oxide-semiconductor MN62 simultaneously；
Described first pseudo- phase inverter INVW1 is produced and is formed ratio pass with the reference current I1 in current encoded module I CODE
The image current I4 of system；Described second pseudo- phase inverter INVW2 produces the tandem circuit with the electric current in current encoded module I CODE
I2 forms the image current I5 of proportionate relationship；Image current I4 and I5 control flow into the electric current of metal-oxide-semiconductor MN61 and metal-oxide-semiconductor MN62,
So as to control the integrating capacitor discharge and recharge time, then by the first Schmidt trigger SMIT1 and the second Schmidt trigger SMIT2
Positive feedback effect, accelerate the adjustment to rising or falling edge, finally realize the first puppet phase inverter INVW1 and the second pseudo- phase inverter
Adjustment of the INVW2 to input clock signal phase；
Latch and amplify output module LA, the two-way clock signal after phase adjustment is processed carries out defeated after synthesis amplification
Go out, obtain output clock phase shift signalling Z.
Described first pseudo- phase inverter INVW1 includes metal-oxide-semiconductor MP31, MN31 and MN32, wherein, the source electrode connection power supply of MP31
VDD, MP31, MN31 constitute inverter circuit, and its grid is commonly connected to the output of the second phase inverter INV2, and its drain electrode connects jointly
The input of the grid and the first Schmidt trigger SMIT1 of metal-oxide-semiconductor MN61 is connected to, the source electrode of MN31 connects the drain electrode of MN32,
The source ground of MN32, the grid of MN32 is connected with current encoded module I CODE；
Second pseudo- phase inverter INVW2 includes metal-oxide-semiconductor MP41, MN41 and MN42, wherein, the source electrode connection power vd D of MP41,
MP41, MN41 constitute inverter circuit, and its grid is commonly connected to input clock, and its drain electrode is commonly connected to metal-oxide-semiconductor MN62's
The input of grid and the second Schmidt trigger SMIT2, the drain electrode of the source electrode connection MN42 of MN41, the source ground of MN42,
The grid of MN42 is connected with current encoded module I CODE.
The input control modular converter CTRL_TR includes two input OR gate OR2, two inputs and the bufferings of door AND2 and second
Device BUF2, the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 connect two input OR gates respectively
The input of OR2, the output end output voltage control signal P1 of two input OR gate OR2；Meanwhile, the first phase shift logic control signal
CTRL1 and the second phase shift logic control signal CTRL2 connect the input of two inputs and door AND2, two inputs and door AND2 respectively
Output end output voltage control signal P2；First phase shift logic control signal CTRL1 connects the input of the second buffer BUF2
End, the second buffer BUF2 output voltage control signals P3.
The current encoded module I CODE includes metal-oxide-semiconductor MN11, MN12, MN13, MN14, MN15 and MN16；Electric current is input into
End NIB connects the drain electrode of metal-oxide-semiconductor MN11, MN13 and MN15 simultaneously, and the grid of metal-oxide-semiconductor MN11 meets voltage control signal P1, MN11's
Source class connects the drain and gate of metal-oxide-semiconductor MN12, and metal-oxide-semiconductor MN14, MN16 grid, the source ground GS of metal-oxide-semiconductor MN12,
The grid of metal-oxide-semiconductor MN13 meets voltage control signal P2, and source electrode connects the drain electrode of metal-oxide-semiconductor MN14, the source class ground connection GS of metal-oxide-semiconductor MN14；
The grid of metal-oxide-semiconductor MN15 meets voltage control signal P3, and source electrode connects the drain electrode of metal-oxide-semiconductor MN16, the source ground GS of metal-oxide-semiconductor MN16；
The grid of metal-oxide-semiconductor NM12, MN14, MN16 is connected in the first pseudo- phase inverter INVW1 as the output of current encoded module I CODE
The grid of metal-oxide-semiconductor MN42 in the grid of metal-oxide-semiconductor MN32 and the second pseudo- phase inverter INVW2.
The ratio between the metal-oxide-semiconductor MN12, metal-oxide-semiconductor MN14, metal-oxide-semiconductor MN16, metal-oxide-semiconductor MN32, breadth length ratio of metal-oxide-semiconductor MN42 are 1：
1：1：4：4.
The amplification output module LA that latches includes PMOS MP91, MP92, MP93 and NMOS tube MN91, MN92, MN93；
The grid of MP91 connects the output of the first Schmidt trigger SMIT1, and the source electrode of MP91 connects the drain electrode of supply voltage VDD, MP91
Connect the grid of metal-oxide-semiconductor MN92 and metal-oxide-semiconductor MP93, and metal-oxide-semiconductor MP92, MN91 drain electrode；Metal-oxide-semiconductor MP92's and metal-oxide-semiconductor MP93
Source electrode meets supply voltage VDD；The output of the 3rd phase inverter INV3 of grid connection of MN93, the source ground GS of metal-oxide-semiconductor MN93,
Drain electrode, the drain electrode of the grid, MN91 of MP93, metal-oxide-semiconductor MN91 and the metal-oxide-semiconductor of the grid, MP92 of the drain electrode connection MN92 of MN93
The source ground GS of MN92；The grid of metal-oxide-semiconductor MP92 and metal-oxide-semiconductor MN91 connects the drain electrode of metal-oxide-semiconductor MP93 and metal-oxide-semiconductor MN92 jointly,
As the output clock phase shift signalling Z for latching amplification output module LA.
Used as further scheme, above-mentioned clock phase-shift circuit also includes reseting switch circuit RESET, the reset switch electricity
Road RESET includes metal-oxide-semiconductor MP51 and MP52, and the source electrode of metal-oxide-semiconductor MP51 and MP52 connects power vd D, metal-oxide-semiconductor MP51's and MP52
Grid connects voltage control signal P1, the output of the pseudo- phase inverter INVW1 of drain electrode connection first of metal-oxide-semiconductor MP51, metal-oxide-semiconductor jointly
The output of the pseudo- phase inverter INVW2 of drain electrode connection second of MP52.
Used as further scheme, above-mentioned clock phase-shift circuit also includes phase inverter INV1, two input XOR gate XOR, two choosings
One non-MUX MX21, output buffer BUF1, third phase move logic control signal CTRL3；Two input OR gate OR2's is defeated
Go out terminal voltage control signal P1, selection the control end S, input clock signal CLK for meeting the non-MUX MX21 of alternative connect two
The low selection end S0 of a non-MUX MX21 is selected, the output clock phase shift signalling Z for amplifying output module LA is latched, two choosings are connect
The high selection end S1 of one non-MUX MX21, the output end Z3 of the non-MUX MX21 of alternative connects two input XOR gates
The second input X2 of XOR, third phase moves the input that logic control signal CTRL3 meets phase inverter INV, and phase inverter INV's is defeated
The first input end X1, the output end Z4 of two input XOR gate XOR for going out the input XOR gate of termination two XOR meet output buffer BUF1
Input, the output termination output clock signal clk OUT of output buffer BUF1.
Present invention beneficial effect compared with prior art is：
(1), a kind of programmable clock phase-shift circuit proposed by the invention, it is only necessary to three logic control signals, i.e.,
Clock is capable of achieving from 0 ° to 180 °, step-length is 45 ° of phase shift, totally 4 adjustment of phase shift；
(2), the present invention is different from traditional clock phase-shift circuit, it is necessary to the bias-voltage generating circuit of complexity could be produced
Different capacitance charging currents；Needing more capacitor array could complete the adjustment of different phase shifts；Proposed by the invention can
The clock phase-shift circuit of programming, can be according to the requirement of output clock phase shift, it is only necessary to simple to two phase shift logic control signals
Programming, you can six metal-oxide-semiconductors of utilization different size of charging current for charging capacitor is provided, substantially reduces opening for chip area
Pin and circuit design difficulty, save circuit power consumption；
(3), a kind of programmable clock phase-shift circuit proposed by the invention, using accurate breadth length ratio between metal-oxide-semiconductor
Example relation, it is ensured that the accurate transmission of current encoded module image electric current, so as to ensure the accurate of charging current in integrating capacitor
Transmission, and then ensure the accurate phase modulation of clock phase shift；
(4), a kind of programmable clock phase-shift circuit proposed by the invention, is amplified using Schmidt trigger and latch
The positive feedback effect of output module so that output signal has more precipitous rising edge and trailing edge；
(5), a kind of programmable clock phase-shift circuit proposed by the invention, its reseting switch circuit can be in clock phase shift
When circuit does not work, current encoded blocks current is closed, so as to reduce the overall dynamics power consumption of circuit；
(6), a kind of programmable clock phase-shift circuit proposed by the invention, it is only necessary to increase by four simple criterion numerals
Word logic unit and a phase shift logic control signal, you can so that clock is from 0 ° to 180 °, step-length is 45 ° of phase shift adjustment model
Enclose, expand to from 0 ° to 360 °, step-length is 45 °, and totally 8 adjusting ranges of phase shift, most quickly meet the optimal of late-class circuit
Adjustment timing position requirement.
Brief description of the drawings
Fig. 1 is a kind of programmable clock phase-shift circuit of the invention；
Electric capacity charging voltage waveform in phase-adjusting circuit when Fig. 2 is for the present invention；
Fig. 3 is 0 ° to 315 ° phase shifted waveforms of clock phase-shift circuit of the present invention；
Specific embodiment
The present invention is explained with specific embodiment below in conjunction with the accompanying drawings.
As shown in figure 1, a kind of programmable clock phase-shift circuit, it is characterised in that including：Control modular converter CTRL_
Output module LA is amplified in TR, current encoded module I CODE, phase-adjusting circuit and latch, wherein：
Input control modular converter CTRL_TR, receives the first phase shift logic control signal CTRL1 and second of outside input
Phase shift logic control signal CTRL2, encode and obtains voltage control signal P1, P2, P3 and send to current encoded module
ICODE；
Current encoded module I CODE, receives current signal I0, the voltage control signal P1 of current input terminal NIB inputs,
P2, P3 are connected at three current sources of current input terminal NIB, unlatching and pass according to the different control electric current sources for encoding
It is disconnected, produce reference current I1, I2, I3；
Phase-adjusting circuit, including the second phase inverter INV2, the first pseudo- phase inverter INVW1, the first Schmidt trigger
SMIT1, the second pseudo- phase inverter INVW2, the second Schmidt trigger SMIT1 and the 3rd phase inverter INV3, metal-oxide-semiconductor MN61 and
MN62；Metal-oxide-semiconductor MN61 and MN62 source electrode and drain electrode short circuit constitute integrating capacitor；The clock signal of outside input is divided into two-way,
The second phase inverter INV2, the first puppet phase inverter INVW1 and the first Schmidt trigger SMIT1 are sequentially connected all the way and are latched amplify
The P ends of output module LA；First pseudo- phase inverter INVW1 output ends connect the grid of metal-oxide-semiconductor MN61 simultaneously；Clock signal it is another
Road is sequentially connected the second pseudo- phase inverter INVW2, the second Schmidt trigger SMIT2, the 3rd phase inverter INV3 and latches amplifies defeated
Go out the N-terminal of module LA, the output end of the second pseudo- phase inverter INVW2 connects the grid of metal-oxide-semiconductor MN62 simultaneously；
Described first pseudo- phase inverter INVW1 is produced and is formed ratio pass with the reference current I1 in current encoded module I CODE
The image current I4 of system；Described second pseudo- phase inverter INVW2 produces the tandem circuit with the electric current in current encoded module I CODE
I2 forms the image current I5 of proportionate relationship；Image current I4 and I5 control flow into the electric current of metal-oxide-semiconductor MN61 and metal-oxide-semiconductor MN62,
So as to control the integrating capacitor discharge and recharge time, then by the first Schmidt trigger SMIT1 and the second Schmidt trigger SMIT2
Positive feedback effect, accelerate the adjustment to rising or falling edge, finally realize the first puppet phase inverter INVW1 and the second pseudo- phase inverter
Adjustment of the INVW2 to input clock signal phase；
Latch and amplify output module LA, the two-way clock signal after phase adjustment is processed carries out defeated after synthesis amplification
Go out, obtain output clock phase shift signalling Z.
First pseudo- phase inverter INVW1 includes metal-oxide-semiconductor MP31, MN31 and MN32, wherein, the source electrode connection power vd D of MP31,
MP31, MN31 constitute inverter circuit, and its grid is commonly connected to the output of the second phase inverter INV2, and its drain electrode is commonly connected to
The input of the grid of metal-oxide-semiconductor MN61 and the first Schmidt trigger SMIT1, the source electrode of MN31 connects the drain electrode of MN32, MN32's
Source ground, the grid of MN32 is connected with current encoded module I CODE；
Second pseudo- phase inverter INVW2 includes metal-oxide-semiconductor MP41, MN41 and MN42, wherein, the source electrode connection power vd D of MP41,
MP41, MN41 constitute inverter circuit, and its grid is commonly connected to input clock, and its drain electrode is commonly connected to metal-oxide-semiconductor MN62's
The input of grid and the second Schmidt trigger SMIT2, the drain electrode of the source electrode connection MN42 of MN41, the source ground of MN42,
The grid of MN42 is connected with current encoded module I CODE.
The input control modular converter CTRL_TR includes two input OR gate OR2, two inputs and the bufferings of door AND2 and second
Device BUF2, the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 connect two input OR gates respectively
The input of OR2, the output end output voltage control signal P1 of two input OR gate OR2；Meanwhile, the first phase shift logic control signal
CTRL1 and the second phase shift logic control signal CTRL2 connect the input of two inputs and door AND2, two inputs and door AND2 respectively
Output end output voltage control signal P2；First phase shift logic control signal CTRL1 connects the input of the second buffer BUF2
End, the second buffer BUF2 output voltage control signals P3.
The current encoded module I CODE includes metal-oxide-semiconductor MN11, MN12, MN13, MN14, MN15 and MN16；Electric current is input into
End NIB connects the drain electrode of metal-oxide-semiconductor MN11, MN13 and MN15 simultaneously, and the grid of metal-oxide-semiconductor MN11 meets voltage control signal P1, MN11's
Source class connects the drain and gate of metal-oxide-semiconductor MN12, and metal-oxide-semiconductor MN14, MN16 grid, the source ground GS of metal-oxide-semiconductor MN12,
The grid of metal-oxide-semiconductor MN13 meets voltage control signal P2, and source electrode connects the drain electrode of metal-oxide-semiconductor MN14, the source class ground connection GS of metal-oxide-semiconductor MN14；
The grid of metal-oxide-semiconductor MN15 meets voltage control signal P3, and source electrode connects the drain electrode of metal-oxide-semiconductor MN16, the source ground GS of metal-oxide-semiconductor MN16；
The grid of metal-oxide-semiconductor NM12, MN14, MN16 is connected in the first pseudo- phase inverter INVW1 as the output of current encoded module I CODE
The grid of metal-oxide-semiconductor MN42 in the grid of metal-oxide-semiconductor MN32 and the second pseudo- phase inverter INVW2.
Clock phase shift module utilizes the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2
The electric current of coding regulation ICODE modules so that flow through the electric current of metal-oxide-semiconductor MN11 and metal-oxide-semiconductor MN12 to receive current input terminal NIB
Whole, the half or 1/3 of electric current I0 are flowed through, by current encoded, finally realizing the adjustment to phase shift.
The ratio between the metal-oxide-semiconductor MN12, metal-oxide-semiconductor MN14, metal-oxide-semiconductor MN16, metal-oxide-semiconductor MN32, breadth length ratio of metal-oxide-semiconductor MN42 are 1：
1：1：4：4.
If the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 in clock phase shift module
During coding output logical zero 1, metal-oxide-semiconductor MN62 grids connecting node (305) voltage rises to the second Schmitt trigger SMIT2's
Turnover voltage (VTH) time be t1, now, receive current input terminal NIB flow through electric current I0 it is whole flow into metal-oxide-semiconductor MN11 and
MN12, then branch current I5 is 4*I0；
If the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 in clock phase shift module
During coding output logic 10, metal-oxide-semiconductor MN62 grids connecting node (305) voltage rises to the second Schmitt trigger SMIT2's
Turnover voltage (VTH) time be t2, now, the branch current I5 of metal-oxide-semiconductor MN42 is 4*I0/2；
If the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 in clock phase shift module
During coding output logic 11, metal-oxide-semiconductor MN62 grids connecting node (305) voltage drops to the second Schmitt trigger SMIT2's
Turnover voltage (VTH) time be t3, now, the branch current I5 of metal-oxide-semiconductor MN42 is 4*I0/3；
If metal-oxide-semiconductor MN62 gate-source capacitances are C0, then the first phase shift logic control signal CTRL1 and the second phase shift logic control
During signal CTRL2 coding output logical zero 1,10,11, relation of the correspondence between t1, t2, t3, as shown in Figure 3：
Then t3=3*t1, t2=2*t1,
T1, t2, t3 are by the half period T/2 deciles of input clock signal CLK for 4 parts, i.e. t1=T/2/4, half period
The phase shift number of degrees be 180 °, therefore the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 coding
The phase shift number of degrees of corresponding each time step are 180 °/4=45 °, you can realize 0 °, 45 °, the 90 ° or 135 ° adjustment of phase shift.
As from the foregoingI.e. in half clock cycle, electric capacity C0On integral voltage at least to reach
VTH, phase shift could now be regulated and controled using Schmidt trigger.The electric current for meeting integral condition is I0If, I0It is smaller, nothing
Method causes electric capacity C within the half period0On integral voltage reach VTH, then Schmidt trigger can be caused not overturn, so that
The adjustment of rising edge or trailing edge cannot be carried out, i.e., cannot exactly adjust the phase shift of clock；If I0It is larger so that in the half period
Electric capacity C0On integral voltage almost just charge reach V in a flashTH, that is to say that coding is different, but almost in the same time
Point, electric capacity C0On integral voltage may be such that Schmidt trigger overturn, now every time coding regulation rising edge and decline
Along almost equal, then adjust with cannot accurately completing clock phase shift.Therefore, integration current I0Can be by clock cycle, MOS electricity
Capacitance, and the threshold value of Schmidt trigger is together decided on.
The first Schmidt trigger SMIT1 is identical with the second Schmidt trigger SMIT1 circuit structures, its
In, the first Schmidt trigger SMIT1 includes metal-oxide-semiconductor MP71, metal-oxide-semiconductor MP73, metal-oxide-semiconductor MP72, metal-oxide-semiconductor MN71, metal-oxide-semiconductor
MP74, metal-oxide-semiconductor MN73, metal-oxide-semiconductor MN72 and metal-oxide-semiconductor MN74；The source electrode of metal-oxide-semiconductor MP71 meets supply voltage VDD, grounded-grid GS,
Drain electrode connects the source electrode of metal-oxide-semiconductor MP72 with the drain electrode of metal-oxide-semiconductor MP73 jointly, and the drain electrode of metal-oxide-semiconductor MP72 and metal-oxide-semiconductor MN71 connects jointly
The grid of metal-oxide-semiconductor MP74 and metal-oxide-semiconductor MN73, the source electrode of metal-oxide-semiconductor MN71 connects the drain electrode of metal-oxide-semiconductor MN72 and metal-oxide-semiconductor MN74, metal-oxide-semiconductor
The grid of MN72 meets supply voltage VDD, and source ground GS, the grid of metal-oxide-semiconductor MN74, metal-oxide-semiconductor MP73 and metal-oxide-semiconductor MP91 connects jointly
The drain electrode of metal-oxide-semiconductor MP74 and metal-oxide-semiconductor MN73, the source electrode of metal-oxide-semiconductor MP73 meets supply voltage VDD；The source electrode of metal-oxide-semiconductor MP74 connects power supply
Voltage VDD, the source ground of metal-oxide-semiconductor MN73.
The amplification output module LA that latches includes PMOS MP91, MP92, MP93 and NMOS tube MN91, MN92, MN93；
The grid of MP91 connects the output (node 306) of the first Schmidt trigger SMIT1, and the source electrode of MP91 meets supply voltage VDD,
The drain electrode of MP91 connects the grid of metal-oxide-semiconductor MN92 and metal-oxide-semiconductor MP93, and metal-oxide-semiconductor MP92, MN91 and metal-oxide-semiconductor MP91 drain electrode；
The source electrode of metal-oxide-semiconductor MP92 and metal-oxide-semiconductor MP93 meets supply voltage VDD；The grid of MN93 connects the output (section of the 3rd phase inverter INV3
Point 309), the drain electrode of grid, MP92 of the drain electrode connection MN92 of the source ground GS of metal-oxide-semiconductor MN93, MN93, the grid of MP93,
The source ground GS of the drain electrode of MN91, metal-oxide-semiconductor MN91 and metal-oxide-semiconductor MN92；The grid of metal-oxide-semiconductor MP92 and metal-oxide-semiconductor MN91 connects jointly
The drain electrode of metal-oxide-semiconductor MP93 and metal-oxide-semiconductor MN92, as the output Z for latching amplification output module LA.
Node 306 and node 309 are output as that pulsewidth is different but phase identical signal, when node 306 and node 309 drop
As little as zero level when, metal-oxide-semiconductor MP91 conductings, node 307 drawn high, and metal-oxide-semiconductor MN92 conductings, output Z is dragged down so that metal-oxide-semiconductor MP92
Rapid conducting, node 307 is driven high latch again, and metal-oxide-semiconductor MN93 and MN91 shut-off, the process are made using the latch of positive feedback
With rapidly the trailing edge of shaping output signal Z, makes it more precipitous.Conversely, when node 306 and node 309 are increased to electricity
During the voltage of source, metal-oxide-semiconductor MP93 conductings, node 307 is dragged down, and metal-oxide-semiconductor MN93 conductings, output Z draws high so that metal-oxide-semiconductor MP91 is rapid
Conducting, node 307 is dragged down latch again, and metal-oxide-semiconductor MN92 and MN92 shut-off, the process are acted on using the latch of positive feedback, soon
The rising edge of fast ground shaping output signal Z, makes it more precipitous.Final output rising and falling edges are precipitous, by phase shift
Clock signal Z afterwards.
Further, programmable clock phase-shift circuit can also include reseting switch circuit RESET, the reset switch
Circuit RESET includes metal-oxide-semiconductor MP51 and MP52, source electrode connection the power vd D, metal-oxide-semiconductor MP51 and MP52 of metal-oxide-semiconductor MP51 and MP52
Grid connect voltage control signal P1 jointly, the output of the pseudo- phase inverter INVW1 of drain electrode connection first of metal-oxide-semiconductor MP51, metal-oxide-semiconductor
The output of the pseudo- phase inverter INVW2 of drain electrode connection second of MP52.；
When P1 is 1, metal-oxide-semiconductor MP51 and metal-oxide-semiconductor MP52 disconnects, on node (304) and node (305) without influence, circuit
Normal work；
When P1 is 0, current encoded module I CODE is without image current, while metal-oxide-semiconductor MP51 and metal-oxide-semiconductor MP52 is opened, section
Point (304) and node (305) are pulled to high level, and phase adjusting module resets.
Reset switch RESET moves logic control signal CTRL3 and directly adjusts programmable clock phase shift electricity using third phase
The output clock signal clk OUT polarity chrons on road, the quiescent current of shut-off clock phase shift module DT, reduce the overall power of path.
As shown in Figure 1.Preferably, programmable clock phase-shift circuit can also include phase inverter INV, two inputs
XOR gate XOR, the non-MUX MX21 of alternative, output buffer BUF1, third phase moves logic control signal CTRL3；Two
The output end P1 of input OR gate OR, meets the selection control end S of the non-MUX MX21 of alternative, and input clock signal CLK connects
The low selection end S0 of the non-MUX MX21 of alternative, the output Z for latching amplification output module LA connects the non-multichannel choosing of alternative
The high selection end S1 of device MX21 is selected, the output end Z3 (node 204) of the non-MUX MX21 of alternative connects two input XOR gates
The second input X2 of XOR, third phase moves the input that logic control signal CTRL3 meets phase inverter INV, and phase inverter INV's is defeated
Go out the first input end X1 that end (node 201) meets two input XOR gate XOR, the output end Z4 (nodes of two input XOR gate XOR
205) input of output buffer BUF1, the output termination output clock signal clk OUT of output buffer BUF1 are connect.So,
Third phase moves logic control signal CTRL3 and can directly adjust the output clock signal clk OUT poles of programmable clock phase-shift circuit
Property.
Do not relied on because third phase moves the adjustable directly output clock signal clk OUT polarity of logic control signal CTRL3
Phase-adjusting circuit, therefore, on the basis of original 0~135 ° of phase shift adjustment of phase-adjusting circuit, can be moved by third phase
The polarity of logic control signal CTRL3 regulation output clock signal clks OUT, quickly and easily will output clock signal clk OUT
Phase shift range extend one times, entire combination may be such that final output clock signal clk OUT phase shift ranges expand to 0~
315°。
Operation principle of the invention is introduced below in conjunction with specific embodiment.
Logic control signal CTRL3, the first phase shift logic control signal CTRL1 are moved to the third phase in clock phase-shift circuit
Programmed with the second phase shift logic control signal CTRL2, input control logic signal can design 8 control codes, respectively CTRL1:
CTRL2:CTRL3=000；001；010；011；100；101；110；111；
During the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 coding output logical zeros 0,
Voltage control signal P1 (node 203) exports logical zero, and the selection control end S selections two of the non-MUX MX21 of alternative are selected
The low selection end S0 of one non-MUX MX21, node (204) is output as 180 ° of inversion signals of CLK；Third phase moves logic
When control signal CTRL3 is encoded to logical zero, the inverted device INV of node (201) exports logic 1, and now node (205) is output as
The XOR of node (201) and node (204), does not postpone with input clock signal CLK with phase；Third phase moves logic control signal
When CTRL3 is encoded to logic 1, the inverted device INV of node (201) exports logical zero, and now node (205) is output as node (201)
With the XOR of node (204), with 180 ° of input clock signal CLK inverse delayeds；
First phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 coding outputs logical zero 1,
10th, 11 when, voltage control signal P1 (node 203) output logic 1, the selection control end S of the non-MUX MX21 of alternative
The high selection end S1 of the non-MUX MX21 of selection alternative, node (204) is output as clock signal Z's (node 206)
180 ° of inversion signals；When third phase shifting logic control signal CTRL3 is encoded to logical zero, the inverted device INV outputs of node (201)
Logic 1, now node (205) be output as the XOR of node (201) and node (204), i.e. clock signal Z (node 206) same to phase
Do not postpone；When third phase shifting logic control signal CTRL3 is encoded to logic 1, the inverted device INV outputs logical zero of node (201),
Now node (205) is output as the XOR of node (201) and node (204), i.e., clock phase shift signalling Z (node 206) is anti-phase prolongs
Slow 180 °；
In clock phase-shift circuit, metal-oxide-semiconductor MN11 and metal-oxide-semiconductor MN12 constitute tie point electric current I1, metal-oxide-semiconductor MN13 and
Metal-oxide-semiconductor MN14 constitutes the second branch current I2, metal-oxide-semiconductor MN15 and metal-oxide-semiconductor MN16 and constitutes the 3rd branch current I3, metal-oxide-semiconductor MN32
The 4th branch current I4 is constituted, NMOS tube 42 constitutes branch current I5.
If the ratio between metal-oxide-semiconductor MN12, metal-oxide-semiconductor MN14, metal-oxide-semiconductor MN16, metal-oxide-semiconductor MN32, breadth length ratio of metal-oxide-semiconductor MN42 are 1：1：
1：4：4；Therefore, I1:I2:I3:I4:I5=1:1:1:4:4；Wherein total current NIB (I0) is I1, I2, I3 sum.
The first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 is compiled in clock phase shift module
During code output logical zero 0, voltage control signal P1 (node 203) is output as logical zero；Now, metal-oxide-semiconductor MN11 shut-offs so that MOS
Pipe MN14, metal-oxide-semiconductor MN16, metal-oxide-semiconductor MN32 and metal-oxide-semiconductor MN42 are simultaneously turned off, without image current, metal-oxide-semiconductor MP51 and metal-oxide-semiconductor MP52
Open, node (304) and node (305) are pulled to high level, and phase-adjusting circuit resets；
If metal-oxide-semiconductor MN62 gate-source capacitances are C0, then the first phase shift logic control signal CTRL1 and the second phase shift logic control
During signal CTRL2 coding output logical zero 1,10,11, the relation between t1, t2, t3, as shown in Figure 2：
The first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 is compiled in clock phase shift module
During code output logical zero 1, voltage control signal P1 (node 203) is output as logic 1, and voltage control signal P2 is logical zero, voltage
Control signal P3 is logical zero, and metal-oxide-semiconductor MN11, metal-oxide-semiconductor MN12 are opened, metal-oxide-semiconductor MN13, metal-oxide-semiconductor MN15, metal-oxide-semiconductor MN14 and MOS
Pipe MN16 is turned off, and receives the electric current I0 that current input terminal NIB is produced, and is all injected into metal-oxide-semiconductor MN11 and metal-oxide-semiconductor MN12, i.e.,
I1 is opened equal to I0, metal-oxide-semiconductor MN32 and metal-oxide-semiconductor MN42, the electric current in mirror image metal-oxide-semiconductor MN12 so that I4 and I5 are equal for branch current
It is 4 times of I1, is also equal to 4 times of I0；At this moment, node (304) and node (305) are to metal-oxide-semiconductor MN61 and the grid of metal-oxide-semiconductor MN62
Capacitance discharge current is 4*I0, and node (304) and node (305) increase to the discharge time of metal-oxide-semiconductor MN61 and metal-oxide-semiconductor MN62,
Because of the turn threshold (V of the first Schmitt trigger SMIT1 and the second Schmitt trigger SMIT2TH) equal so that node
(306) and node (308) trailing edge in VTHPlace's upset, node (309) is node (308) by reverse after phase inverter INV3
Output signal, and pulsewidth is less than node (306)；The voltage signal at node (306) and node (309) place adjusts latch and amplifies respectively
The voltage upset of the tail pipe metal-oxide-semiconductor MP91 and metal-oxide-semiconductor MN93 of circuit LA, the trailing edge of its interior joint (306) determines clock phase shift
The trailing edge of signal Z (node 206), the rising edge of node (309) determines the rising edge of clock phase shift signalling Z (node 206), most
Composition rising, trailing edge are more precipitous eventually, and relative CLK time delays elapse 1/8 clock phase shift signalling Z of clock cycle.
If the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 in clock phase shift module
During coding output logical zero 1, metal-oxide-semiconductor MN62 grids connecting node (305) voltage drops to the second Schmitt trigger SMIT2's
The time of turnover voltage (VTH) is t1, now, receive current input terminal NIB flow through electric current I0 it is whole flow into metal-oxide-semiconductor MN11 and
MN12, then branch current I5 is 4*I0；
The first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 is compiled in clock phase-shift circuit
During code output logic 10, voltage control signal P1 (node 203) is output as logic 1；Now, voltage control signal P2 is logical zero,
Voltage control signal P3 is logic 1, and metal-oxide-semiconductor MN11, metal-oxide-semiconductor MN12, metal-oxide-semiconductor MN15 and metal-oxide-semiconductor MN16 are opened, metal-oxide-semiconductor MN13
With metal-oxide-semiconductor MN14 shut-offs, the electric current I0 that current input terminal NIB is produced is received, half is injected into metal-oxide-semiconductor MN11 and metal-oxide-semiconductor MN12
In, i.e. I1 is equal to I0/2, and second half is injected into metal-oxide-semiconductor MN15 and metal-oxide-semiconductor MN16, i.e. I3 is equal to I0/2, now, metal-oxide-semiconductor
MN32 and metal-oxide-semiconductor MN42 is opened, the electric current in mirror image metal-oxide-semiconductor MN12 so that branch current I4 and I5 are 4 times of I1, also etc.
In 2 times of I0；At this moment, the grid capacitance charging and discharging currents of node (304) and node (305) to metal-oxide-semiconductor MN61 and metal-oxide-semiconductor MN62
It is 2*I0, node (304) and node (305) are doubled to the discharge and recharge time of metal-oxide-semiconductor MN61 and metal-oxide-semiconductor MN62, because of first
Turn threshold (the V of Schmitt trigger SMIT1 and the second Schmitt trigger SMIT2TH) equal so that node (306) and section
The trailing edge of point (308) is in VTHPlace's upset, node (309) is node (308) by the reverse output signal after phase inverter INV3,
And pulsewidth is less than node (306)；The voltage signal at node (306) and node (309) place adjusts latching amplification circuit LA's respectively
The voltage upset of tail pipe metal-oxide-semiconductor MP91 and metal-oxide-semiconductor MN93, the trailing edge of its interior joint (306) determines clock phase shift signalling Z (sections
Point trailing edge 206), the rising edge of node (309) determines the rising edge of clock phase shift signalling Z (node 206), finally constitutes
Liter, trailing edge are more precipitous, and relative CLK time delays elapse 2/8 clock phase shift signalling Z of clock cycle.
If the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 in clock phase shift module
During coding output logic 10, metal-oxide-semiconductor MN62 grids connecting node (305) voltage drops to the second Schmitt trigger SMIT2's
Turnover voltage (VTH) time be t2, now, the branch current I5 of metal-oxide-semiconductor MN42 is 4*I0/2；
The first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 is compiled in clock phase-shift circuit
During code output logic 11, voltage control signal P1 (node 203) is output as logic 1, and voltage control signal P2 is logic 1, voltage
Control signal P3 is logic 1, metal-oxide-semiconductor MN11, metal-oxide-semiconductor MN12, metal-oxide-semiconductor MN13, metal-oxide-semiconductor MN14, metal-oxide-semiconductor MN15 and metal-oxide-semiconductor
MN16 is opened, and receives the electric current I0 that current input terminal NIB is produced, and 1/3 is injected into metal-oxide-semiconductor MN11 and metal-oxide-semiconductor MN12, i.e. I1 etc.
It is injected into metal-oxide-semiconductor MN13 and metal-oxide-semiconductor MN14 in I0/3,1/3, i.e. I2 is equal to I0/3, and 1/3 is injected into metal-oxide-semiconductor MN15 and metal-oxide-semiconductor
In MN16, i.e. I3 is equal to I0/3.Now, metal-oxide-semiconductor MN32 and metal-oxide-semiconductor MN42 is opened, the electric current in mirror image metal-oxide-semiconductor MN12 so that
Branch current I4 and I5 are 4 times of I1, are also equal to 4/3 times of I0；At this moment, node (304) and node (305) are to metal-oxide-semiconductor
The grid capacitance discharge current of MN61 and metal-oxide-semiconductor MN62 is 4/3*I0, node (304) and node (305) to metal-oxide-semiconductor MN61 with
The discharge and recharge time of metal-oxide-semiconductor MN62 is with respect to the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2
Increase twice during coding output logical zero 1, because of the upset of the first Schmitt trigger SMIT1 and the second Schmitt trigger SMIT2
Threshold value (VTH) equal so that the trailing edge of node (306) and node (308) is in VTHPlace's upset, node (309) is node (308)
By the reverse output signal after phase inverter INV3, and pulsewidth is less than node (306)；Node (306) and the electricity at node (309) place
Pressure signal adjusts the voltage upset of the tail pipe metal-oxide-semiconductor MP91 and metal-oxide-semiconductor MN93 of latching amplification circuit LA, its interior joint respectively
(306) trailing edge determines the trailing edge of clock phase shift signalling Z (node 206), and the rising edge of node (309) determines clock phase shift
The rising edge of signal Z (node 206), it is more precipitous to finally constitute rising, trailing edge, and relative CLK time delays elapse 3/8 clock
The clock phase shift signalling Z in cycle.
If the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 in clock phase shift module
During coding output logic 11, metal-oxide-semiconductor MN62 grids connecting node (305) voltage drops to the second Schmitt trigger SMIT2's
The time of turnover voltage (VTH) is t3, and now, the branch current I5 of metal-oxide-semiconductor MN42 is 4*I0/3；
Then t3=3*t1, t2=2*t1,
, by the half period T/2 deciles of input clock signal CLOCK for 4 parts, the corresponding phase shift number of degrees are for t1, t2, t3
180 °/4=45 °.
Therefore regulation is capable of achieving the phase shift adjustment that step-length is 45 ° every time, you can realize 0 °, 45 °, 90 ° or 135 ° phase shift
Adjustment.
When third phase moves logic control signal CTRL3 coding output logics 1, to the first phase shift logic control signal
CTRL1 and the second phase shift logic control signal CTRL2 programmings 00,01,10,11, phase shift elapses 45 ° successively；Third phase is moved and is patrolled
Control signal CTRL3, the first phase shift logic control signal CTRL1 and the second phase shift logic control signal CTRL2 codings 000 are collected,
001,010,011,100,101,110, finally, after extension corresponding tunable phase shift be 0 °, 45 °, 90 °, 135 °, 180 °, 225 °,
270 °, 315 °.
To sum up, logic control signal CTRL3, the first phase shift logic control signal CTRL1 and second are moved by third phase
Phase shift logic control signal CTRL2 carries out coding and is capable of achieving phase shift relation as shown in table 1 below, and actual emulation output relation is as schemed
Shown in 3：
Table 1
| CTRL3 | CTRL3 | CTRL3 | Degree of phase shift (°) |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 45 |
| 0 | 1 | 0 | 90 |
| 0 | 1 | 1 | 135 |
| 1 | 0 | 0 | 180 |
| 1 | 0 | 1 | 225 |
| 1 | 1 | 0 | 270 |
| 1 | 1 | 1 | 315 |
Non-elaborated part of the present invention belongs to techniques well known.
Claims (8)
1. a kind of programmable clock phase-shift circuit, it is characterised in that including：Control modular converter CTRL_TR, current encoded mould
Output module LA is amplified in block ICODE, phase-adjusting circuit and latch, wherein：
Input control modular converter CTRL_TR, receives the first phase shift logic control signal CTRL1 and second phase shift of outside input
Logic control signal CTRL2, encode and obtains voltage control signal P1, P2, P3 and send to current encoded module I CODE；
Current encoded module I CODE, receive the current signal I0 of current input terminal NIB input, shunts it to being connected in parallel
Three current sources, according to voltage control signal P1, P2, P3 control being switched on and off for internal three current sources respectively, produce base
Quasi- electric current I1, I2, I3；
Phase-adjusting circuit, including the second phase inverter INV2, the first pseudo- phase inverter INVW1, the first Schmidt trigger SMIT1,
Second pseudo- phase inverter INVW2, the second Schmidt trigger SMIT1 and the 3rd phase inverter INV3, metal-oxide-semiconductor MN61 and MN62；Metal-oxide-semiconductor
MN61 and MN62 source electrodes and drain electrode short circuit constitute integrating capacitor；The clock signal of outside input is divided into two-way, is connected successively all the way
Meet the second phase inverter INV2, the first puppet phase inverter INVW1 and the first Schmidt trigger SMIT1 and latch and amplify output module LA
P ends；First pseudo- phase inverter INVW1 output ends connect the grid of metal-oxide-semiconductor MN61 simultaneously；Another road of clock signal is sequentially connected
The N of output module LA is amplified in second pseudo- phase inverter INVW2, the second Schmidt trigger SMIT2, the 3rd phase inverter INV3 and latch
End, the output end of the second pseudo- phase inverter INVW2 connects the grid of metal-oxide-semiconductor MN62 simultaneously；
Described first pseudo- phase inverter INVW1 is produced and is formed proportionate relationship with the reference current I1 in current encoded module I CODE
Image current I4；Described second pseudo- phase inverter INVW2 produces the tandem circuit I2 shapes with the electric current in current encoded module I CODE
The image current I5 of proportional relation；Image current I4 and I5 control flow into the electric current of metal-oxide-semiconductor MN61 and metal-oxide-semiconductor MN62, so that
The control integrating capacitor discharge and recharge time, then by the first Schmidt trigger SMIT1 and the second Schmidt trigger SMIT2 just
Feedback effect, accelerates the adjustment to rising or falling edge, finally realizes the pseudo- phase inverters of the first puppet phase inverter INVW1 and second
Adjustment of the INVW2 to input clock signal phase；
Latch and amplify output module LA, the two-way clock signal after phase adjustment is processed is exported after carrying out synthesis amplification, is obtained
To output clock phase shift signalling Z.
2. a kind of programmable clock phase-shift circuit according to claim 1, it is characterised in that：First pseudo- phase inverter
INVW1 includes metal-oxide-semiconductor MP31, MN31 and MN32, wherein, source electrode connection the power vd D, MP31, MN31 of MP31 constitute phase inverter
Circuit, its grid is commonly connected to the output of the second phase inverter INV2, and its drain electrode is commonly connected to the grid and the of metal-oxide-semiconductor MN61
The input of one Schmidt trigger SMIT1, the source electrode of MN31 connects the drain electrode of MN32, the source ground of MN32, the grid of MN32
It is connected with current encoded module I CODE；
Second pseudo- phase inverter INVW2 includes metal-oxide-semiconductor MP41, MN41 and MN42, wherein, the source electrode connection power vd D of MP41,
MP41, MN41 constitute inverter circuit, and its grid is commonly connected to input clock, and its drain electrode is commonly connected to metal-oxide-semiconductor MN62's
The input of grid and the second Schmidt trigger SMIT2, the drain electrode of the source electrode connection MN42 of MN41, the source ground of MN42,
The grid of MN42 is connected with current encoded module I CODE.
3. a kind of programmable clock phase-shift circuit according to claim 1, it is characterised in that：The input control conversion
Module CTRL_TR includes two input OR gate OR2, two inputs and door AND2 and the second buffer BUF2, the first phase shift logic control
Signal CTRL1 and the second phase shift logic control signal CTRL2 connect the input of two input OR gate OR2, two input OR gates respectively
The output end output voltage control signal P1 of OR2；Meanwhile, the first phase shift logic control signal CTRL1 and the second phase shift logic control
Signal CTRL2 processed connects the output end output voltage control of the input of two inputs and door AND2, two inputs and door AND2 respectively
Signal P2；First phase shift logic control signal CTRL1 connects the input of the second buffer BUF2, the second buffer BUF2 outputs
Voltage control signal P3.
4. a kind of programmable clock phase-shift circuit according to claim 1, it is characterised in that：The current encoded module
ICODE includes metal-oxide-semiconductor MN11, MN12, MN13, MN14, MN15 and MN16；Current input terminal NIB connect simultaneously metal-oxide-semiconductor MN11,
The drain electrode of MN13 and MN15, the source class that the grid of metal-oxide-semiconductor MN11 meets voltage control signal P1, MN11 connects the drain electrode of metal-oxide-semiconductor MN12
And grid, and metal-oxide-semiconductor MN14, MN16 grid, the source ground GS of metal-oxide-semiconductor MN12, the grid of metal-oxide-semiconductor MN13 connects voltage control
Signal P2 processed, source electrode connects the drain electrode of metal-oxide-semiconductor MN14, the source class ground connection GS of metal-oxide-semiconductor MN14；The grid of metal-oxide-semiconductor MN15 connects voltage control
Signal P3 processed, source electrode connects the drain electrode of metal-oxide-semiconductor MN16, the source ground GS of metal-oxide-semiconductor MN16；The grid of metal-oxide-semiconductor NM12, MN14, MN16
Pole is connected to the grid and the second puppet of metal-oxide-semiconductor MN32 in the first pseudo- phase inverter INVW1 as the output of current encoded module I CODE
The grid of metal-oxide-semiconductor MN42 in phase inverter INVW2.
5. a kind of programmable clock phase-shift circuit according to claim 2, it is characterised in that：The metal-oxide-semiconductor MN12,
The ratio between metal-oxide-semiconductor MN14, metal-oxide-semiconductor MN16, metal-oxide-semiconductor MN32, breadth length ratio of metal-oxide-semiconductor MN42 are 1：1：1：4：4.
6. a kind of programmable clock phase-shift circuit according to claim 1, it is characterised in that：Described latch amplifies output
Module LA includes PMOS MP91, MP92, MP93 and NMOS tube MN91, MN92, MN93；The grid of MP91 connects the first Schmidt
The output of trigger SMIT1, the drain electrode that the source electrode of MP91 meets supply voltage VDD, MP91 connects metal-oxide-semiconductor MN92's and metal-oxide-semiconductor MP93
Grid, and metal-oxide-semiconductor MP92, MN91 drain electrode；The source electrode of metal-oxide-semiconductor MP92 and metal-oxide-semiconductor MP93 meets supply voltage VDD；MN93's
The output of the 3rd phase inverter INV3 of grid connection, the grid of the drain electrode connection MN92 of the source ground GS, MN93 of metal-oxide-semiconductor MN93,
The source ground GS of the drain electrode of MP92, the grid of MP93, the drain electrode of MN91, metal-oxide-semiconductor MN91 and metal-oxide-semiconductor MN92；Metal-oxide-semiconductor MP92 and
The grid of metal-oxide-semiconductor MN91 connects the drain electrode of metal-oxide-semiconductor MP93 and metal-oxide-semiconductor MN92 jointly, used as the output for latching amplification output module LA
Clock phase shift signalling Z.
7. a kind of programmable clock phase-shift circuit according to claim 1, it is characterised in that also including reset switch electricity
Road RESET, the reseting switch circuit RESET include metal-oxide-semiconductor MP51 and MP52, the source electrode connection electricity of metal-oxide-semiconductor MP51 and MP52
The grid of source VDD, metal-oxide-semiconductor MP51 and MP52 connects voltage control signal P1 jointly, and the drain electrode connection first of metal-oxide-semiconductor MP51 is pseudo- anti-
The output of phase device INVW1, the output of the pseudo- phase inverter INVW2 of drain electrode connection second of metal-oxide-semiconductor MP52.
8. a kind of programmable clock phase-shift circuit according to claim 3, it is characterised in that also including phase inverter INV1,
Two input XOR gate XOR, the non-MUX MX21 of alternative, output buffer BUF1, third phase moves logic control signal
CTRL3；The output end voltage control signal P1 of two input OR gate OR2, connects the selection control of the non-MUX MX21 of alternative
End S, input clock signal CLK meet the low selection end S0 of the non-MUX MX21 of alternative, latch and amplify output module LA's
Output clock phase shift signalling Z, meets the high selection end S1 of the non-MUX MX21 of alternative, the non-MUX MX21 of alternative
Output end Z3 meet the second input X2 of two input XOR gate XOR, third phase moves logic control signal CTRL3 and connects phase inverter
The input of INV, the output termination two of phase inverter INV is input into the first input end X1, two input XOR gate XOR of XOR gate XOR
Output end Z4 connect the input of output buffer BUF1, the output termination output clock signal of output buffer BUF1
CLKOUT。
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