CN2355350Y - Interferrence-free multi-channel switch controller - Google Patents

Abstract

The utility model relates to an interference-free multi-channel switch controller. The utility model is composed of an input buffering drive circuit, a switch controller circuit, an output buffering driver circuit, a latching interrupt controller circuit, a microprocessor circuit, a command buffering drive circuit and a signal distributor circuit. Standard data signals are received through two redundant input interfaces; the signals are judged and latched through the microprocessor circuit and the latching interrupt controller circuit; one group of data signal is output to the redundant output interfaces through the output buffering driver circuit. When the group of the signal does not normally work, an instruction is sent out, and another group of signal is output through the switch controller circuit.

Description

No disturbance multichannel switch controller

The utility model belongs to electronic technology field, is a kind of multiple signals switch controller.

Existing multichannel switch controller adopts hardware circuit to finish mostly, and criterion is less, and sensitivity is lower, the signal phase that two-shipper is sent out can not be just the same, switches not reach no disturbance switching, and computing machine may crash, occur losing information phenomenon, and can introduce interference, produce burr, level saltus step.

The purpose of this utility model is to provide a kind of general highly reliable no disturbance multichannel switch controller, is applied to redundant system to satisfy the needs of high reliability.

Solution of the present utility model is to adopt the input buffering driving circuit, the switch controller circuit, output buffering driver circuit, latch the interruptable controller circuit, microprocessor circuit, order buffering drive circuit and signal distribution circuit are formed, the input buffering driving circuit is two groups, be divided into input buffering driving circuit I, II, input end meets redundant input interface I respectively, II, output terminal connects the switch controller circuit altogether, interruptable controller circuit and microprocessor circuit are latched in one tunnel connection of switch controller circuit, another road connects the output buffering driver, the redundant output interface of output termination of output buffering driver circuit; Order buffering drive circuit I input termination control order interface, output terminal connects signal distribution circuit respectively and latchs the interruptable controller circuit, signal distribution circuit meets order buffering drive circuit II, and order buffering drive circuit II output terminal connects redundant input interface I, II and microprocessor circuit respectively.The input buffering driving circuit is selected U for use ₁-U ₄Four bus buffer driving circuit LS245, the switch controller circuit is selected U for use ₆-U ₉Four four alternative MUX LS157 integrated circuit latch the interruptable controller circuit and select U for use ₁₁-U ₁₈Be double D trigger LS74 and U ₁₉-U ₂₂Be eight bus buffer driving circuit LS244, output buffering driver circuit is by U ₂₈, U ₂₉Two eight bus driver LS244 form.Order buffering drive circuit I selects U for use ₂₃, be eight bus buffer driver LS244, signal distribution circuit is 12 AND circuit, order buffering drive circuit II selects U for use ₃₆, U ₃₇, be eight bus buffer driver LS244, U ₃₀-U ₃₅But be repeated trigger univibrator LS123, microprocessor circuit is selected 89C51 series 8-bit microcontroller for use.This device is by two redundant input interface I, II acceptance criteria data-signal, by micro-processor interface circuit with latch the interruptable controller circuit and signal is judged latched, and pass through output buffering driver circuit and export wherein one group of data-signal to redundant output interface, if this group signal work is undesired, sends instruction and make the switch controller circuit export another group signal.

The utility model utilizes the Time synchronization technique principle, makes the two-shipper difference concurrent working down synchronously at one time that puts into operation, guarantee that the two-shipper transmission is identical in time with information and consistent, thereby the no disturbance of realization system is switched.Circuit structure is simple, adopts intelligent multichannel to switch, can flexible combination and alternative use, have highly reliable, high performance-price ratio, advantage such as anti-interference.

Below in conjunction with accompanying drawing and embodiment the utility model is specified:

Fig. 1 is the utility model block diagram;

Fig. 2 is input buffering driving circuit figure;

Fig. 3 is the switch controller circuit diagram;

Fig. 4 is for latching the interruptable controller circuit diagram;

Fig. 5 is signal distribution circuit figure;

Fig. 6 is microcontroller circuit figure;

Fig. 7 is signal condition indicating circuit figure.

In input buffering driving circuit I3 and input buffering driving circuit II4, U ₁, U ₂Input end connect redundant input interface I1, input signal A ₁-A ₁₆, U ₃, U ₄The redundant input interface II2 of input termination, input signal B ₁-B ₁₆, U ₁-U ₄Buffering drives back output signal a ₁-a ₁₆And b ₁-b ₁₆Send into switch controller circuit 5 and signal condition indication driving circuit 6, U ₁And U ₂Be connected U ₁The OE pin connect not gate U _51/6, C ₁, C ₂, R ₁, R ₂, by not gate U _51/6Meet redundant input interface I1, U ₃And U ₄Connect, the OE pin of U4 connects not gate U _52/6, C ₃, C ₄, R ₃, R ₄, by not gate U _52/6Meet redundant input interface II2, C ₁-C ₄Strobe, improve the antijamming capability of circuit, R ₁And R ₃Be not gate level reference, R ₂, R ₄Be pull-up resistor, improve the amplitude of not gate output high level.U among input buffering driving circuit I3 and the input buffering driving circuit II4 ₁-U ₄The corresponding U that connects in the signal condition indication driving circuit 6 of output terminal pin ₂₄-U ₂₇The input end pin, U ₂₄-U ₂₇The output terminal pin be connected to a light emitting diode respectively, but the duty of light emitting diode display converter.U ₁-U ₄The corresponding again U that connects in the switch controller 5 of output terminal pin ₆-U ₉The input end pin, U ₆-U ₉Each control end pin by not gate U _10-2Meet the P of microprocessor circuit 10 _2.5Pin, U ₁-U ₄Send signal a ₁-a ₁₆And b ₁-b ₁₆Deliver to U respectively ₆-U ₉Corresponding pin is exported wherein one group of signal S after selecting control ₁-S ₁₆, work as P _2.5During for high level, through not gate U _10-2Anti-phase back output low level, control are selected output A group signal, find that the work of A group signal is undesired if microprocessor circuit 10 detects, and send switching command and make P _2.5Port step-down level, U ₆-U ₉The output group-b signal.Latch the U of interruptable controller 9 ₁₁-U ₁₈The corresponding U that connects of input end pin ₆-U ₉The output terminal pin, U ₁₁-U ₁₈The corresponding U that connects of output terminal pin ₁₉-U ₂₂The output terminal pin, U ₁₉-U ₂₂The output terminal pin, U ₁₉-U ₂₂The corresponding corresponding end pin that connects microcontroller circuit 10 single-chip microcomputers of output terminal pin, by U ₆-U ₉The signal S that transmits ₁-S ₁₆Receive double D trigger U respectively ₁₁-U ₁₈Input clock end pin, when signal by low level during to the high level saltus step, trigger upset output high level, and remaining unchanged is realized the effect of latching of signal, this signal is delivered to U ₁₉, U ₂₁Input end, U ₁₉, U ₂₁Output terminal receive on the common data bus of microcontroller circuit 10 single-chip microcomputers, single-chip microcomputer constantly reads U in the specific moment ₁₉, U ₂₁The information of output is analyzed, is handled and judge whether signal is normal, for switching provides reliable basis.Microcontroller circuit 10 in detection signal, U ₂₀, U ₂₂The corresponding trigger that detection signal is provided is removed resetted, latch for detection next time and prepare.So more than detection of latching that realizes signal of circulation.10 pairs of entire circuit of microcontroller circuit are controlled, and realize correctly switching reliably of system.U ₆-U ₉The output terminal pin corresponding connect U in the output buffering driver circuit 7 ₂₈, U ₂₉The input end pin, the signal S that is sent ₁-S ₁₆Through U ₂₈, U ₂₉Buffering drives from redundant output interface 8 outputs.U among the order buffering drive circuit I12 ₂₃The input end pin meets control command interface 11, U ₂₃The P of output terminal pin and microprocessor circuit 10 _2.5Port meets 12 AND circuit R in the signal distribution circuit 13 respectively _A1-6And R _B1-6Corresponding input end pin, P _2.5The end pin by a not gate connect with the door R _A1,3,5And R _B1,3,5Meet R by a not gate again _A2,4,6And R _B2,4,6, AND circuit output terminal pin is the U of bind command buffering drive circuit 14 respectively ₃₀-U ₃₅Corresponding input end pin, U ₃₀-U ₃₂The corresponding U that connects of output terminal pin ₃₆The input end pin, U ₃₃-U ₃₅, the corresponding U that connects of output terminal pin ₃₇The input end pin, U ₃₆, U ₃₇The output terminal pin meet redundant input interface I, II by data bus.By the next order R of computing machine _X1-R _X6By control command interface 11 through U ₂₃Deliver to the corresponding input end of 12 AND circuit after the buffering respectively, P _2.5Port control command signal R _X1-R _X6Whereabouts, work as P _2.5When port is high level, R _X1-R _X6Through AND circuit control output R _A1-R _A6, deliver on the current equipment that uses as main frame through interface then, also deliver to latch cicuit U simultaneously respectively ₃₀-U ₃₅And buffering drive circuit U ₃₆, U ₃₇, U ₃₆, U ₃₇Output terminal receive on the bus of microprocessor, make microprocessor judges have or not control command, switching for no disturbance provides important evidence.

Claims (2)

1, a kind of no disturbance multichannel switch controller, it is characterized in that: it adopts the input buffering driving circuit, the switch controller circuit, output buffering driver circuit, latch the interruptable controller circuit, microprocessor circuit, order buffering drive circuit and signal distribution circuit are formed, the input buffering driving circuit is two groups, be divided into input buffering driving circuit I, II, input end meets redundant input interface I respectively, II, output terminal connects the switch controller circuit altogether, interruptable controller circuit and microprocessor circuit are latched in one tunnel connection of switch controller circuit, another road connects the output buffering driver, the redundant output interface of output termination of output buffering driver circuit; Order buffering drive circuit I input termination control command interface, output terminal connects signal distribution circuit respectively and latchs the interruptable controller circuit, signal distribution circuit meets order buffering drive circuit II, order buffering drive circuit II output terminal connects redundant input interface I, II and microprocessor circuit respectively, and wherein the input buffering driving circuit is selected U for use ₁-U ₄Four eight bus buffer driving circuit LS245, the switch controller circuit is selected U for use ₆-U ₉Four four alternative MUX LS157 integrated circuit latch the interruptable controller circuit and select U for use ₁₁-U ₁₈Be double D trigger LS74 and U ₁₉-U ₂₂Be eight bus buffer driving circuit LS244, output buffering driver circuit is by U ₂₈, U ₂₉Two eight bus driver LS244 form, order buffering drive circuit IU ₂₃Be eight bus buffer driver LS244, signal distribution circuit is 12 AND circuit, the U of order buffering drive circuit II ₃₆, U ₃₇Be eight bus driver LS244, U ₃₀-U ₃₅But be repeated trigger univibrator LS123, microprocessor circuit is selected 89C51 series 8-bit microcontroller for use.

2, switch controller according to claim 1 is characterized in that: in input buffering driving circuit I3 and input buffering driving circuit II4, and U ₁, U ₂Input end connect redundant input interface I1, U ₃, U ₄The redundant input interface II2 of input termination, U ₁And U ₂Be connected U ₁The OE pin connect not gate U _51/6And C ₁, C ₂, R ₁, R ₂, by not gate U _51/6Meet redundant input interface I1, U ₃, U ₄Connect U ₄The OE pin connect not gate U _52/6And C ₃, C ₄, R ₃, R ₄, by not gate U _52/6Meet redundant input interface II2, U ₁-U ₄The corresponding U that connects in the signal condition indication driving circuit 6 of output terminal pin ₂₄-U ₂₇The input end pin, U ₁-U ₄The corresponding again U that connects switch controller 5 of output terminal pin ₆-U ₉The input end pin, U ₆-U ₉Each control end pin by not gate U _10-2Meet the P of microprocessor circuit 10 _2.5Pin latchs the U of interruptable controller 9 ₁₁-U ₁₈The corresponding U that connects of input end pin ₆-U ₉The output terminal pin, U ₁₁-U ₁₈The corresponding U that connects of output terminal pin ₁₉-U ₂₂The output terminal pin, U ₁₉-U ₂₂The corresponding corresponding end pin that connects microcontroller circuit 10 single-chip microcomputers of output terminal pin, U ₆-U ₉The output terminal pin corresponding connect U in the output buffering driver circuit 7 ₂₈, U ₂₉The input end pin; U in the order buffering drive circuit 112 ₂₃The input end pin meets control command interface 11, U ₂₃The P of output terminal pin and microprocessor circuit 10 _2.5Port meets 12 AND circuit R in the signal distribution circuit 13 respectively _A1-6And R _B1-6Corresponding input end pin, P _2.5The end pin connects and door R by a not gate _A1,3,5And R _B1,3,5, meet R by a not gate again _A2,4,6And R _B2,4,6, AND circuit output terminal pin is the U of bind command buffering drive circuit 14 respectively ₃₀-U ₃₅Corresponding input end pin, U ₃₀-U ₃₂The corresponding U that connects of output terminal pin ₃₆The input end pin, U ₃₃-U ₃₅The corresponding U that connects of output terminal pin ₃₇The input end pin, U ₃₆And U ₃₇The output terminal pin by the redundant input interface I of data bus, II.

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