CN2318759Y

CN2318759Y - Multiplexer capable of programming

Info

Publication number: CN2318759Y
Application number: CN 98202182
Authority: CN
Inventors: 裴文端; 尤静; 贾士军
Original assignee: INST NO 54 MINISTRY OF ELECTRONIC INDUSTRY
Current assignee: INST NO 54 MINISTRY OF ELECTRONIC INDUSTRY
Priority date: 1998-03-17
Filing date: 1998-03-17
Publication date: 1999-05-12
Anticipated expiration: 2008-03-17

Abstract

The utility model discloses a multiplexer capable of programming, which is composed of a code stream combiner, a code stream splitter, a dual port memory, a frame synchronization word generator, a frame synchronization word address generator, a multiplexing time sequence generator, a tapping time sequence generator, a multiplexing time sequence address generator, a tapping time sequence address generator, a multiplexing and a tapping clock generator, a digital signal processor, a program memory, etc. The utility model adopts a programmable logic device and the digital signal processor to realize the multiplexer capable of programming with complicated frame structure and changeable frame structure and a changeable rate. The multiplexer capable of programming has the advantages of high intelligence, high integration, small size, light weight, convenient application, etc. The utility model can be used as a multiplexer apparatus capable of programming for a communication apparatus.

Description

A kind of programmable demultiplexer

The utility model relates to the programmable demultiplexer in a kind of communications field, and the communication equipment that is specially adapted to complex frames structure and change frame structure, variable Rate is made the programmable demultiplexer device.

At present most multiplexers that use are to belong to anchor-frame structure, fixedly frame length, fixing frame alignment word in the communication equipment, such multiplexer to realize in the communication equipment ITU-T H.221 the multiplexer of standard be helpless, therefore the application of multiplexer is restricted, bring certain difficulty for the manufacturing of communication equipment, and improved the cost and the volume of communication equipment.

The purpose of this utility model is to avoid the weak point in the above-mentioned background technology and a kind of suitable complex frames structure is provided and becomes the programmable demultiplexer of frame structure, variable Rate, and the utility model also to have an intellectuality, integrated degree height, volume little, in light weight, use characteristics such as convenient.

The purpose of this utility model is to realize like this; It is made up of dual-ported memory 1, frame alignment word generator 2, frame alignment word address generator 3, code stream mixer 4,

interface level transducer

5,6, multiple connection clock generator 7, multiple connection sequential address generator 8, multiple connection information clock generator 9, digital signal processor 10, tap clock generator 11, tap sequential address generator 12, program storage 13, code stream splitter 14, tap clock generator 15 and power supply 16.Wherein external control data goes into to hold A to go into to hold 1 pin to be connected by data/address bus and dual-ported memory 1, external control address goes into to hold B to go into end 2 pin by address bus and dual-ported memory 1 to be connected, dual-ported memory 1 come in and go out end 3 pin by data/address bus, go into end 4 pin and come in and go out with each of frame alignment word generator 2, multiple connection clock generator 7, tap clock generator 11, digital signal processor 10 and program storage 13 respectively by address bus and hold 1,2 pin to be connected in parallel; Interface level transducer 6 goes into that

end

1,2 pin are connected, go into C, the D end that receives data terminal that

end

3,4 pin are connected with receive clock E, F end respectively respectively, the tap data go out that end 5 pin and digital signal processor 10 go into that end 3 pin are connected, the tap clock goes out to hold 6 pin to go into to hold 4 pin, tap sequential address generator 12 to go into to hold 3 pin and tap clock generator 15 to go into to hold 2 pin and connect with digital signal processor 10 respectively; Frame alignment word generator 2 goes into to hold 3 pin to go into to hold 1 pin to be connected, to go out to hold 4 pin to go into to hold 2 pin to be connected, to go out to hold 5 pin to go into to hold 1 pin to be connected by frame alignment output line and code stream mixer 4 by address zero clearing line and frame alignment word address generator 3 by frame alignment address bus and frame alignment word address generator 3; Frame alignment word address generator 3 is gone into end 3 pin and is gone out to hold 3 pin to be connected with multiple connection information clock generator 9; Code stream mixer 4 goes into to hold 2-1 to 2-N to be connected, to go into end 3 pin respectively with multiple connection information input terminal T1 to TN end to go out end 5 pin, multiple connection information clock generator 9 with multiple connection clock generator 7 respectively by the multiple connection timing bus and go into end 1 pin and multiple connection sequential output P end and connect, go out end 4 pin and interface level transducer 5 goes into to hold 1 pin to be connected; Interface level transducer 5 is gone into end 2 pin and is gone into to hold M end, multiple connection sequential address generator 8 to go into end 3 pin and multiple connection information clock generator 9 with the multiple connection clock respectively to go into end 2 pin and connect, go out

end

3,4 pin and dateout end G, H end to be connected, to go out

end

5,6 pin and export clock end J, K and hold and be connected; Multiple connection clock generator 8 goes out end 1 pin and goes into to hold 3 pin to be connected, to go into to hold 2 pin to go out to hold 4 pin to be connected by address zero clearing line and multiple connection clock generator 7 by multiple connection sequential address bus and multiple connection clock generator 7; Multiple connection information generator 9 goes out to hold 4-1 to 4-N pin to go into to hold L1 to LN end to be connected with multiple connection information clock respectively; Tap clock generator 11 is gone into end 3 pin and is gone out end 1 pin by tap sequential address bus and tap sequential address generator 12 and is connected, goes out end 4 pin and go into end 2 pin by address zero clearing line and tap sequential address generator 12 and is connected, goes out end 5 pin and go into to hold 1 pin, branch to go into to hold 1 pin and divide chronologically that bus goes out to hold N to hold and connects by clock generator 15 with code stream splitter 14 respectively by the tap timing bus; Code stream splitter 14 goes out to hold 3-1 to 3-N pin to go out to hold R1 to RN end to be connected with tap information respectively; Tap clock generator 15 goes out to hold 3-1 to 3-N pin to go out to hold S1 to SN end to be connected with the tap clock respectively; Digital signal processor 10 goes out end 5 pin and goes into to hold 2 pin to be connected with code stream splitter 14; Power supply 16 goes out end+V voltage end and each parts power supply and goes into end and be connected.

The purpose of this utility model can also reach by following measure:

The utility model dual-ported memory 1, frame synchronization generator 2 are made of dual-ported memory integrated

package

20,21 respectively; Interface level transducer 6 is made of level shifter interface integrated package 27; Digital signal processor 10 is made of microprocessor integrated package 24, d type flip flop 17, crystal oscillator 18; Program storage 13 is made of eprom memory integrated package 25; Tap sequential address generator 12, code stream splitter 14 and tap clock generator 15 are made of programmable logic device integrated package 26, wherein dual-ported memory integrated package 20 goes into to hold 5 to 16 pin to go into to hold B to be connected with external control data address bus, going into end 17 to 24 pin goes into to hold A to be connected with external control data, end 27 to 34 pin of coming in and going out are come in and gone out with dual-ported memory integrated package 21 respectively by data/address bus and are held 17 to 24 pin, eprom memory integrated package 25 is come in and gone out and is held 11 to 19 pin, digital signal processor integrated package 24 is come in and gone out and is held 6 to 13 and 23 to 30 pin, programmable logic device integrated package 26 is come in and gone out and is held 1,2,3,21 to 29 and 32 to 39 pin, multiple connection clock generator 7 is come in and gone out and is held 1 pin and tap clock generator 11 discrepancy ends 1 pin to be connected in parallel, go into end 36 to 47 pin and go into end 5 to 16 pin with dual-ported memory integrated package 21 respectively by address bus, eprom memory integrated package 25 is gone into end 2 to 10 and 21,23,24,25 pin, digital signal processor integrated package 24 goes out end 55 to 64 and 72 to 77 pin, programmable logic device integrated package 26 is gone into end 190 to 198 pin, end 2 pin gone into by multiple connection clock generator 7 and tap clock generator 11 goes into to hold 2 pin to be connected in parallel, and goes into to hold 52 pin to go out end+V voltage end with power supply 16 and is connected, going into end 26 pin is connected with the ground end; Dual-ported memory integrated package 21 is gone into end 36 to 45,47 pin and is gone out end 1 pin by frame alignment address bus and frame alignment word address generator 3 and is connected, goes out end 27 pin and go into end 1 pin by frame alignment output line and code stream mixer 4 and be connected, go into to hold 50,52 pin and power supply 16 to go out end+V voltage end to be connected, to go into to hold 26 pin to hold with ground to be connected; Eprom memory integrated package 25 is gone into

end

1,27,28 pin and power supply 16 and is gone out end+V voltage end and be connected, go into to hold 14,22 pin to hold with ground to be connected; Level conversion connects an integrated package 27 goes into

end

1,2 pin and is connected, goes into

end

6,7 pin with C, the D end that receives data terminal respectively and is connected with receive clock end E, F end respectively, and the tap data go out that end 3 pin and programmable logic device integrated package 26 go into that end 178 pin are connected, the tap clock goes out end 5 pin and programmable logic device integrated package 26 goes into to hold 177 pin to be connected, to go into to hold 16,4 pin and power supply 16 to go out end+V voltage end to be connected, to go into to hold 8,12 pin to hold with ground to be connected; Digital signal processor integrated package 24 goes out end 46,109 pin and d type flip flop 17 and goes into

end

2,3 pin and is connected, goes into end 45 pin and d type flip flop 17 and go into end 5 pin and is connected, goes into to hold 96 pin and crystal oscillator 18 to go out to hold 3 pin to be connected, to go into to hold 66,132 pin and power supply 16 to go out end+V voltage end to be connected, to go into to hold 5,36,71,102,103 pin and earth terminals; D type flip flop 17 is gone into end 14 pin and power supply 16 and is gone out terminal voltage+V voltage end and is connected, goes into to hold 7 pin to hold with ground to be connected; Crystal oscillator 18 is gone into end 4 pin and is connected, goes into to hold 2 pin to be connected with the ground end with power supply 16 voltages+V voltage end; Programmable logic device integrated package 26 goes out end 157 to 163 pin and goes into end 5 pin and tap timing bus by tap timing bus and tap clock generator 11 and go out to hold N to hold and connect, going out end 54 to 57 goes out to hold R1 to RN end to be connected with tap information respectively, going out end 73 to 76 pin goes out to hold S1 to SN to be connected with the tap clock respectively, going out end 58 to 70 pin goes into to hold 3 pin by tap sequential address bus and tap clock generator 11 and connects, going into to hold 200 pin to go out end+V voltage end with power supply 16 is connected, going into end 104 pin is connected with the ground end.

The utility model tap clock generator 11, multiple connection clock generator 7 is respectively by dual-ported memory integrated

package

28,29 constitute, frame alignment word address generator 3, code stream mixer 4, multiple connection sequential address generator 8 and multiple connection information clock generator 9 are by programmable logic device integrated package 30, not gate 19 constitutes, wherein the dual-ported memory integrated

package

28,29 each end 8 to 16 pin of coming in and going out, pass through data/address bus, each end 55 to 67 pin of coming in and going out is come in and gone out with dual-ported memory 1 respectively by address bus and is held 3,4 pin, frame alignment word generator 2 is come in and gone out and is held 1,2 pin, digital signal processor 10 is come in and gone out and is held 1,2 pin and program storage 13 are come in and gone out and are held 1,2 pin are connected in parallel, dual-ported memory 28, each end 19 to 27 pin of coming in and going out is by tap timing bus and code stream splitter 14, tap clock generator 15 is respectively gone into to hold 1 pin and tap timing bus to go out to hold the N end and is connect, respectively going into end 36 to 48 pin goes out to hold 1 pin by tap sequential address bus and tap sequential address generator 12 and connects; Dual-ported memory 29 goes out each 19 to 27 pin of end and goes into

end

23,26 to 29 and 32 to 34 pin and multiple connection sequential output P end by multiple connection timing bus and programmable logic device integrated package 30 and connect, respectively go into end 36 to 48 pin to go out to hold 90,92 to 103 pin by multiple connection sequential address bus and programmable logic device 30 and connect; Dual-ported memory integrated

package

28,29 respectively go into

end

4,51 and 68 pin go out end+V voltage end with power supply 16 and connect, respectively 35,52 pin are held with ground and are connected; Programmable logic device integrated package 30 goes out end 55 pin and goes into to hold the M end to be connected with the multiple connection clock, going into end 63 pin goes out to hold 5 pin to be connected with frame alignment word generator 2, go out end 129 to 137,154 to 157 pin are gone into end 3 pin by frame alignment address bus and frame alignment word generator 2 and are connected, going out end 163 to 169 pin is connected with multiple connection clock output L1 to LN, going into end 64 to 67 pin is connected with multiple connection information input terminal T1 to TN end, go out end 77,80 pin and interface level transducer 5 are gone into

end

1,7 pin connect, go into end 177 pin NAND gate 19 and go out the connection of end 3 pin; Going into to hold 200 pin and power supply 16 to go out end+V voltage end is connected, goes into to hold 104,105 pin to be connected with the ground end; Not gate 19 go into end 2 pin with resistance R 1, capacitor C 1 and K switch one end and connect, go into

end

6,7 pin with resistance R 2, capacitor C 2 one ends and connect, go into end 5 pin serial connection capacitor C 3 back earth terminals, go into

end

4,8 pin and resistance R 1, the R2 other end goes out end+V voltage end with power supply 16 and is connected, the K switch other end, capacitor C 1, the C2 other end and hold also and connect.

The utility model has been compared following advantage with background technology:

1. the utility model adopts the scale programmable logic device integrated package to make, therefore integrated degree height, and frame structure, frame length, frame alignment word and bit rate that can the real time altering multiplexer-demultiplexer realize that complex frames structure multiplexer-demultiplexer changes.

2. the utility model is because integrated degree height, therefore intelligent degree height, and volume is little, and is in light weight.

3. the utility model adopts surface mounting technology, and is therefore stable and reliable for performance, easy to use.

Below in conjunction with accompanying drawing the utility model is described in further detail.

Fig. 1 is an electric functional-block diagram of the present utility model.

Fig. 2 is the electrical schematic diagram of the utility model dual-ported memory 1, frame alignment word generator 2, interface level transducer 6, digital signal processor 10, program storage 13, tap sequential address generator 12, code stream splitter 14 and tap clock generator 15.

Fig. 3 is the electrical schematic diagram of the utility model multiple connection clock generator 7, tap clock generator 11, frame alignment word address generator 3, code stream mixer 4, multiple connection sequential address generator 8 and multiple connection information clock generator 9.

Referring to figs. 1 through Fig. 3, the utility model is made up of dual-ported memory 1, frame alignment word generator 2, frame alignment word address generator 3, code stream mixer 4,

interface level transducer

5,6, multiple connection clock generator 7, multiple connection sequential address generator 8, multiple connection information clock generator 9, digital signal processor 10, tap clock generator 11, tap sequential address generator 12, program storage 13, code stream splitter 14, tap clock generator 15 and power supply 16.Wherein external control data goes into to hold A to go into to hold 1 pin to be connected by data/address bus and dual-ported memory 1, external control address goes into to hold B to go into to hold 2 pin to be connected by address bus and dual-ported memory 1, its effect of dual-ported memory 1 receives the control data and the control address signal of external control unit input, and 3, each comes in and goes out and holds 1,2 pin to be connected in parallel 4 pin by data/address bus and address bus and frame alignment word generator 2, multiple connection clock generator 7, tap clock generator 11, digital signal processor 10 and program storage 13 respectively.The generation frame synchronizing signal was stored in frame alignment word generator 2 after digital signal processor 10 received dual-ported memory 1 output control data, the frame synchronization address signal of frame alignment word address generator 3 generations simultaneously is by frame alignment address bus incoming frame synchronization character generator 2, and the address clear signal that frame alignment word generator 2 goes out the generation of end 4 pin carries out zero clearing, its frame alignment signal input code flow mixer 4 that goes out to hold 5 pin to produce by address zero clearing line to frame alignment word address generator 3 addresses.

The utility model dual-ported memory 1, frame alignment word generator 2 are made of dual-ported memory integrated

package

20,21 respectively; Interface level transducer 6 is made of level shifter interface integrated package 27; Digital signal processor 10 is made of microprocessor integrated package 24, d type flip flop 17, crystal oscillator 18; Program storage 13 is made of eprom memory integrated package 25; Tap sequential address generator 12, code stream splitter 14 and tap clock generator 15 are made of programmable logic device integrated package 26.Fig. 2 is the embodiment electricity principle connection line figure of the utility model dual-ported memory 1, frame alignment word generator 2, interface level transducer 6, digital signal processor 10, program storage 13, tap sequential address generator 12, code stream splitter 14 and tap clock generator 15, and embodiment presses Fig. 2 connection line.

Embodiment dual-ported memory integrated

package

20,21 adopt commercially available IDT7132 type integrated package to make, dual-port storage integrated package 20 its effects of dual-ported memory 1 are data and the address informations that receive the control unit input, import control data information by 17 to 24 pin by the A input port, import the control data address information by 5 to 16 pin by the B input port, 27 to 34 pin dateout information of dual-ported memory integrated package 20 are imported 17 to 24 pin of dual-ported memory integrated package 21 respectively, 11 to 19 pin of eprom memory integrated

package

25,6 to 13 pin of digital signal processor integrated

package

24 and 23 to 30 pin, its 36 to 47 pin address information is imported 5 to 16 pin of dual-ported memory integrated package 21 respectively, 2 to 10 and 21 of eprom memory integrated

package

25,23 to 25 pin, 55 to 64 and 72 to 77 pin of digital signal processor integrated package 24; The frame alignment word address signal of 36 to 45 pin incoming frame synchronization character address generators, 3 inputs of dual-ported memory integrated package 21, effect is to produce frame synchronizing signal; Level shifter interface integrated package 27 embodiment adopt commercially available 26LS32 type integrated package to make, effect is to be level shifter interface, the data RS422 equilibrium level conversion of signals that inbound port C, D termination are received is the TTL digital signal level, the clock RS422 equilibrium level conversion of signals that inbound port E, F termination are received is the TTL digital signal level, goes into the TTL digital demulplexing clock signal input programmable logic device integrated package 26 of end 117 pin, output through the TTL digital demulplexing data-signal input programmable logic device 26 of level shifter interface integrated package 27 outputs and goes into end 178 pin.Digital signal processor integrated package 24 embodiment adopt commercially available TMS320C50 type digital signal processor integrated package to make, its effect is that control produces sequential and frame synchronization is searched for, it goes into end 96 pin are provided digital signal processor integrated package 24 by crystal oscillator 18 clock source signal, embodiment is the 57MHz signal, and crystal oscillator 18 adopts the crystal oscillator source of commercially available 57MHz to be made; 109, the triggering signal of 46 pin input d type flip flop 17, effect provides the serial port frame synchronizing signal of digital signal processor integrated package 24, and embodiment d type flip flop 17 adopts commercially available 74F74 type integrated package to make.The clock signal that digital signal processor integrated package 24 produces is input to dual-ported memory integrated

package

28,29 by data/address bus, after digital signal processor integrated package 24 produces sequential, carries out the frame synchronization search.The utility model eprom memory integrated package 25 embodiment adopt commercially available WS57C49 type integrated package to make, and its effect is the stored program signal.

Programmable logic device integrated package 26 embodiment of the utility model tap sequential address generator 12, code stream splitter 14 and tap clock generator 15 adopt a commercially available EPM9320 type programmable logic device to make, wherein 12 effects of tap sequential address generator are to produce tap sequential address signal, go into end 5 pin by 157 to 163 pin of programmable logic device integrated package 26 by tap sequential address bus input tap clock generator 11.Code stream splitter 14 effect is that one road code stream is resolved into each branch road information, by 54 to 57 pin of programmable logic device integrated package 26 each branch road tap information is exported to tap information and goes out to hold R1 to RN to hold, and embodiment is exported by 10 road branch road tapped off signal.Tap clock generator 15 effect is to produce the tap clock signal, by 73 to 76 pin of programmable logic device integrated package 26 each branch road tap clock signal is exported to the tap clock information and goes out to hold S1 to SN to hold, and embodiment is exported by 10 road branch road tap clock signals.The tap time sequence information of 157 to the 163 pin input of programmable logic device integrated package 26 goes out end 5 pin and tap sequential output N end by tap timing bus and tap clock generator 11 and connects, the address information of the data message of the discrepancy end 1 to 3,21 to 29 of programmable logic device integrated

package

26 and 20 input and output of 32 to 39 pin input and output dual-ported memory integrated packages, end 190 to 199 pin input and output dual-ported memory integrated packages 20 input and output of coming in and going out.

The utility model tap clock generator 11, multiple connection clock generator 7 are made of dual-ported memory integrated

package

28,29 respectively, and frame alignment word address generator 3, code stream mixer 4, multiple connection sequential address generator 8 and multiple connection information clock generator 9 are made of programmable logic device integrated package 30, not gate 19.Fig. 3 is the embodiment electricity principle connection line figure of the utility model multiple connection clock generator 7, tap clock generator 11, frame alignment word address generator 3, code stream mixer 4, multiple connection sequential address generator 8 and multiple connection information clock generator 9, not gate 19, and embodiment is by Fig. 3 connection line, wherein dual-ported memory integrated

package

28,29 embodiment all adopt commercially available IDT7005B type dual-ported memory integrated package to make.28 effects of dual-ported memory integrated package are to produce the tap clock signal, and 29 effects of dual-ported memory integrated package are to produce the multiple connection clock signal.By the data message of 3 pin of dual-ported memory 1 output through data/address bus import 8 to 16 pin of dual-ported

memory

28,29 respectively, 55 to 67 pin that the address information of its 4 pin output is imported dual-ported

memory

28,29 respectively through address bus connect.End 19 to 27 pin that go out of dual-ported memory 28 are exported 7 tunnel tap clock signals input code flow splitter 14, tap clock generator 15 are gone into end 1 pin and the tap sequential goes out to hold the N end respectively by the tap timing bus, go out to hold the external branch road of N end output by the tap sequential, the tap sequential address signal of 36 to the 48 pin input of dual-ported memory 28 goes out end 1 pin by tap sequential address bus and tap sequential address generator 12 and is connected, goes out to hold the address clear signal of 49 pin output to go into to hold 2 pin to be connected with tap sequential address generator 12, the input reset signal.7 tunnel multiple connection clock signals that go out the output of end 19 to 27 pin of dual-ported memory 29 go out to hold the P end by go into to hold 23,26 to 29,32 and 34 pin and the multiple connection sequential of multiple connection timing bus input programmable logic device integrated package 30, go out to hold the external branch road of P end output by the multiple connection sequential, the multiple connection sequential address signal of 36 to the 48 pin input of dual-ported memory 29 is connected with programmable logic device integrated package 30 output multiple connection sequential address signals 90,92 to 103 pin by multiple connection sequential address bus; Dual-ported memory 29 wherein goes out the address clear signal of end 27 pin output and wherein goes into to hold 33 pin to be connected with programmable logic device 30, and the time sequence address of multiple connection sequential address generator 8 is carried out zero clearing.

The programmable logic device integrated package 30 of the utility model frame alignment word address generator 3, code stream mixer 4, multiple connection sequential address generator 8 and multiple connection information clock generator 9 adopts a commercially available EPM9320 type programmable logic device to make, wherein 3 effects of frame alignment word address generator are to produce the frame synchronization address signal, and end 3 pin are gone into by frame alignment address bus incoming frame synchronization character generator 2 in the frame alignment signal address of its 129 to 137,154 to 157 pin output; 4 effects of code stream mixer are synthetic one road signal bit stream of the multichannel branch road information of input, imported 64 to 67 pin by multiple connection information by input T1 to TN end, closing the road code stream closes the road signal bit stream to Transistor-Transistor Logic level by 77,80 pin input interface level transducers 5, interface level transducer 5 and converts RS422 equilibrium level signal to, close the circuit-switched data signal by the output of J, K end, the road clock signal is closed in the output of G, H end; 8 effects of multiple connection sequential address generator are to produce multiple connection sequential address signal, and the multiple connection clock is by going into to hold M end input 55 pin; 9 effects of multiple connection information clock generator are to produce by the clock signal of multiple connection information, are exported to L1, L2 by multiple connection information clock by 163,164 pin and hold output, being exported to each branch road by multiple connection information clock.The utility model not gate 19 adopts commercially available 74F04 type integrated package to make, effect is to the reset signal shaping, reset signal is produced by the K switch that not gate 19 connects, and 177 pin by not gate 19 outputs 3 pin input programmable logic device integrated package 30 reset to programmable logic device.

The utility model power supply 16 embodiment adopt general D.C. regulated power supply circuit self-control to form, and its output+V voltage is+5v voltage.All resistance, capacitor element also adopts commercially available general-purpose device to make in the utility model.

The concise and to the point operation principle of the utility model is as follows: constitute the utility model multiple connection part by digital signal processor 10, program storage 13, frame alignment word generator 2, frame alignment word address generator 3, multiple connection clock generator 7, multiple connection sequential address generator 8, dual-ported memory 1, code stream mixer 4, multiple connection information clock generator 9 and interface level transducer 5.The order that digital signal processor 10 is read according to dual-ported memory 1, form corresponding sequential and write multiple connection clock generator 7, the address signal that the sequential of multiple connection simultaneously address generator 8 produces is read the sequential in the multiple connection clock generator 7 for multiple connection and is used, this sequence generating method is flexible, highly versatile, revise command word and just can change frame length, frame structure and sequential, realize the real-time variable multiple connection of kinds of frame.

The frame alignment word of multiple connection is deposited in frame alignment word generator 2, can change the content of frame alignment word by dual-ported memory 1, and promptly synchronization character is variable.Under the control of multiple connection information clock generator 9, read frame alignment word input code flow mixer 4 in the frame alignment word generator 2 by frame alignment word address generator 3, finish the synchronization character multiple connection.

Code stream mixer 4 will be exported by multiple connection message queue under sequencing control, finish multiple connection, and multiple connection is after interface level transducer 5 is sent to outlet line.

Multiple connection clock generator 9 produces the inner clock signal of using of multiplexer, is sent to the continuous clock and the interrupted clock that are used by the multiple connection information unit.The utility model multiplexer partly adopts the external clock mode, and being provides P * 64kHz clock by outside miscellaneous equipment, and wherein P=1 to 30 is imported by input M end.It all is to carry out control interface by dual-ported memory 1 that any state of multiplexer changes, and specifically controlling clock frequency is the content and the frame synchronization mode of bit rate, frame structure, frame length, frame alignment word, supplied with digital signal processor 10.

The utility model constitutes the coupler part by digital signal processor 10, program storage 13, tap clock generator 11, tap sequential address generator 12, code stream splitter 14 and tap clock generator 15.At first produce the tap sequential, receive the composite bit stream signal of importing from interface level transducer 6 and carry out the frame synchronization search by digital signal processor then by tap clock generator 11.

The order that digital signal processor 10 is read according to dual-ported memory 1, the corresponding sequential of formation write tap clock generator 11, the address that tap sequential address generator 12 produces is read the sequential in the tap clock generator 11 for tap and is used, tap clock generator 15 produces tap branch road information clock under the tap sequencing control, exported through S1 to SN end by tap clock generator 15.

The process that digital signal processor 10 carries out the frame synchronization search is as follows:

1. dual-ported memory 1 is set up the sliding window that meets the frame synchronization requirement according to the method for synchronization and the synchronization character of external communication device.

2. digital signal processor 10 is in search window, the search frame synchronization character.If the synchronization character contract that searches step rule then is judged to synchronously, enters synchronous checking, otherwise continue the search synchronization character, till meeting synchronization rules.

3. digital signal processor 10, then is judged to step-out, otherwise is in synchronous regime if synchronization character the error code number of times occurs and satisfies the step-out rule at synchronous Qualify Phase.

4. digital signal processor 10 is after synchronous searching finishes, the sequential of forcing tap clock generator 7 to produce is aimed at sync bit, guaranteeing that 14 pairs of code streams of code stream splitter carry out correct tap, code stream splitter 14 carries out shunt with composite bit stream according to tap sequential and sync bit and obtains each branch road information and finish tap.

The utility model mounting structure is as follows: Fig. 1 in the utility model, Fig. 2, it is on 320 * 400 millimeters the printing version that all components and parts among Fig. 3 are installed in a block length * wide, wherein the programmable logic device integrated

package

26,30, digital signal processor integrated package 24, dual-ported memory integrated

package

20,21,28,29 large scale integrated circuits such as grade adopt surface mounting technology, therefore the circuit volume is little, in light weight, to be installed in length * wide * height be in 340 * 420 * 100 millimeters the cabinet printing version then, on the panel of cabinet, mains switch is installed, control data, A is gone into to hold in the address, B end cable socket, receive data, clock C, D, E, F end cable socket, the cable socket that tap information and clock go out to hold R1 to RN end and S1 to SN end also is installed on panel, multiple connection information clock goes into to hold L1 to LN end cable socket, dateout, clock G, H, J, K end cable socket, on the rear board of cabinet, power input socket is installed, power supply of the present utility model also can adopt outside+5v power supply power supply, assembly cost utility model.

Claims

1. one kind by code stream mixer (4), code stream splitter (14), the programmable demultiplexer that power supply (16) is formed, it is characterized in that dual-ported memory (1) in addition, frame alignment word generator (2), frame alignment word address generator (3), interface level transducer (5), (6), multiple connection clock generator (7), multiple connection sequential address generator (8), multiple connection information clock generator (9), digital signal processor (10), tap clock generator (11), tap sequential address generator (12), program storage (13), tap clock generator (15) is formed, wherein external control data goes into to hold A to go into to hold 1 pin to be connected by data/address bus and dual-ported memory (1), external control address goes into to hold B to go into to hold 2 pin to be connected by address bus and dual-ported memory (1), and dual-ported memory (1) is come in and gone out and held 3 pin to pass through data/address bus, go into end 4 pin by address bus respectively with frame alignment word generator (2), multiple connection clock generator (7), tap clock generator (11), each of digital signal processor (10) and program storage (13) come in and gone out and held 1,2 pin are connected in parallel; Interface level transducer (6) goes into that end 1,2 pin are connected, go into C, the D end that receives data terminal that end 3,4 pin are connected with receive clock E, F end respectively respectively, the tap data go out that end 5 pin and digital signal processor (10) go into that end 3 pin are connected, the tap clock goes out to hold 6 pin to go into to hold 4 pin, tap sequential address generator (12) to go into to hold 3 pin and tap clock generator (15) to go into to hold 2 pin and connect with digital signal processor (10) respectively; Frame alignment word generator (2) goes into to hold 3 pin to go into to hold 1 pin to be connected, to go out to hold 4 pin to go into to hold 2 pin to be connected, to go out to hold 5 pin to go into to hold 1 pin to be connected by frame alignment output line and code stream mixer (4) by address zero clearing line and frame alignment word address generator (3) by frame alignment address bus and frame synchronization address generator (3); Frame alignment word address generator (3) is gone into end 3 pin and is gone out to hold 3 pin to be connected with multiple connection information clock generator (9); Code stream mixer (4) is gone into to hold 2-1 to 2-N to be connected, to go into to hold 3 pin to go out to hold 5 pin, multiple connection information clock generator (9) to go into end 1 pin and multiple connection sequential output P end with multiple connection clock generator (7) respectively by the multiple connection timing bus respectively with multiple connection information input terminal T1 to TN end and is connect, goes out to hold 4 pin and interface level transducer (5) to go into to hold 1 pin to be connected; Interface level transducer (5) is gone into end 2 pin and is gone into to hold M end, multiple connection sequential address generator (8) to go into end 3 pin and multiple connection information clock generator (9) with the multiple connection clock respectively to go into end 2 pin and connect, go out end 3,4 pin and dateout end G, H end to be connected, to go out end 5,6 pin and export clock end J, K and hold and be connected; Multiple connection sequential address generator (8) goes out end 1 pin and goes into to hold 3 pin to be connected, to go into to hold 2 pin to go out to hold 4 pin to be connected by address zero clearing line and multiple connection clock generator (7) by multiple connection sequential address bus and multiple connection clock generator (7); Multiple connection information generator (9) goes out to hold 4-1 to 4-N pin to go into to hold L1 to LN end to be connected with multiple connection information clock respectively; Tap clock generator (11) is gone into end 3 pin and is gone out end 1 pin by tap sequential address bus and tap sequential address generator (12) and is connected, goes out end 4 pin and go into to hold 2 pin to be connected, to go out to hold 5 pin to go into to hold 1 pin, tap clock generator (15) to go into to hold 1 pin and tap timing bus to go out to hold N to hold and connect with code stream splitter (14) respectively by the tap timing bus by address zero clearing line and tap sequential address generator (12); Code stream splitter (14) goes out to hold 3-1 to 3-N pin to go out to hold R1 to RN end to be connected with tap information respectively; Tap clock generator (15) goes out to hold 3-1 to 3-N pin to go out to hold S1 to SN end to be connected with the tap clock respectively; Digital signal processor (10) goes out end 5 pin and goes into to hold 2 pin to be connected with code stream splitter (14); Power supply (16) goes out end+V voltage end and each parts power supply and goes into end and be connected.

2. a kind of programmable demultiplexer according to claim 1 is characterized in that dual-ported memory (1), frame alignment word generator (2) are made of dual-ported memory integrated package (20), (21) respectively; Interface level transducer (6) is made of level shifter interface integrated package (27); Digital signal processor (10) is made of microprocessor integrated package (24), d type flip flop (17), crystal oscillator (18); Program storage (13) is made of eprom memory integrated package (25); Tap sequential address generator (12), code stream splitter (14) and tap clock generator (15) are made of programmable logic device integrated package (26), and wherein dual-ported memory integrated package (20) goes into to hold 5 to 16 pin to go into to hold B to be connected with external control data address bus, going into end 17 to 24 pin goes into to hold A to be connected with external control data, end 27 to 34 pin of coming in and going out are come in and gone out with dual-ported memory integrated package (21) respectively by data/address bus and are held 17 to 24 pin, eprom memory integrated package (25) is come in and gone out and is held 11 to 19 pin, digital signal processor integrated package (24) is come in and gone out and is held 6 to 13 and 23 to 30 pin, programmable logic device integrated package (26) is come in and gone out and is held 1,2,3,21 to 29 and 32 to 39 pin, multiple connection clock generator (7) is come in and gone out and is held 1 pin and tap clock generator (11) discrepancy end 1 pin to be connected in parallel, go into end 36 to 47 pin and go into end 5 to 16 pin with dual-ported memory integrated package (21) respectively by address bus, eprom memory integrated package (25) is gone into end 2 to 10 and 21,23,24,25 pin, digital signal processor integrated package (24) goes out end 55 to 64 and 72 to 77 pin, programmable logic device integrated package (26) is gone into end 190 to 198 pin, end 2 pin gone into by multiple connection clock generator (7) and tap clock generator (11) goes into to hold 2 pin to be connected in parallel, going into to hold 52 pin to go out end+V voltage end with power supply (16) is connected, going into end 26 pin is connected with the ground end; Dual-ported memory integrated package (21) is gone into end 36 to 45,47 pin and is gone out end 1 pin by frame alignment address bus and frame alignment word address generator (3) and is connected, goes out end 27 pin and go into to hold 1 pin to be connected, to go into to hold 50,52 pin and power supply (16) to go out end+V voltage end by frame alignment output line and code stream mixer (4) to be connected, to go into to hold 26 pin to hold with ground to be connected; Eprom memory integrated package (25) is gone into end 1,27,28 pin and power supply (16) and is gone out end+V voltage end and be connected, go into to hold 14,22 pin to hold with ground to be connected; Level shifter interface integrated package (27) goes into that end 1,2 pin are connected, go into C, the D end that receives data terminal that end 6,7 pin are connected with receive clock end E, F end respectively respectively, the tap data go out that end 3 pin and programmable logic device integrated package (26) go into that end 178 pin are connected, the tap clock goes out end 5 pin and programmable logic device integrated package (26) goes into to hold 177 pin to be connected, to go into to hold 16,4 pin and power supply (16) to go out end+V voltage end to be connected, to go into to hold 8,12 pin to hold with ground to be connected; Digital signal processor integrated package (24) goes out end 46,109 pin and d type flip flop (17) and goes into end 2,3 pin and is connected, goes into end 45 pin and d type flip flop (17) and go into end 5 pin and is connected, goes into to hold 96 pin and crystal oscillator (18) to go out to hold 3 pin to be connected, to go into to hold 66,132 pin and power supply (16) to go out end+V voltage end to be connected, to go into to hold 5,36,71,102,103 pin and earth terminals; D type flip flop (17) is gone into end 14 pin and power supply (16) and is gone out terminal voltage+V voltage end and is connected, goes into to hold 7 pin to hold with ground to be connected; Crystal oscillator (18) is gone into end 4 pin and power supply (16) and is gone out terminal voltage+V voltage end and is connected, goes into to hold 2 pin to hold with ground to be connected; Programmable logic device integrated package (26) goes out end 157 to 163 pin and goes into to hold 5 pin and tap timing bus to go out to hold N to hold by tap timing bus and tap clock generator (11) and connect, going out end 54 to 57 goes out to hold R1 to RN end to be connected with tap information respectively, going out end 73 to 76 pin goes out to hold S1 to SN to be connected with the tap clock respectively, going out end 58 to 70 pin goes into to hold 3 pin by tap sequential address bus and tap clock generator (11) and connects, going into to hold 200 pin to go out end+V voltage end with power supply (16) is connected, going into end 104 pin is connected with the ground end.

3. a kind of programmable demultiplexer according to claim 1 and 2, it is characterized in that tap clock generator (11), multiple connection clock generator (7) is respectively by dual-ported memory integrated package (28), (29) constitute, frame alignment word address generator (3), code stream mixer (4), multiple connection sequential address generator (8) and multiple connection information clock generator (9) are by programmable logic device integrated package (30), not gate (19) constitutes, dual-ported memory integrated package (28) wherein, (29) each end 8 to 16 pin of coming in and going out, pass through data/address bus, each end 55 to 67 pin of coming in and going out is come in and gone out with dual-ported memory (1) respectively by address bus and is held 3,4 pin, frame alignment word generator (2) is come in and gone out and is held 1,2 pin, digital signal processor (10) is come in and gone out and is held 1,2 pin and program storage (13) are come in and gone out and are held 1,2 pin are connected in parallel, and each end 19 to 27 pin of coming in and going out of dual-ported memory (28) are by tap timing bus and code stream splitter (14), tap clock generator (15) is respectively gone into to hold 1 pin and tap timing bus to go out to hold the N end and is connect, respectively going into end 36 to 48 pin goes out to hold 1 pin by tap sequential address bus and tap sequential address generator (12) and connects; Dual-ported memory (29) goes out each 19 to 27 pin of end and goes into end 23,26 to 29 and 32 to 34 pin and multiple connection sequential output P end by multiple connection timing bus and programmable logic device integrated package (30) and connect, respectively go into to hold 36 to 48 pin to go out to hold 90,92 to 103 pin by multiple connection sequential address bus and programmable logic device (30) and connect; Dual-ported memory integrated package (28), (29) respectively go into end 4,51 and 68 pin go out end+V voltage end with power supply (16) and connect, respectively 35,52 pin are held with ground and are connected; Programmable logic device integrated package (30) goes out end 55 pin and goes into to hold the M end to be connected with the multiple connection clock, going into end 63 pin goes out to hold 5 pin to be connected with frame alignment word generator (2), go out end 129 to 137,154 to 157 pin are gone into end 3 pin by frame alignment address bus and frame alignment word generator (2) and are connected, going out end 163 to 169 pin is connected with multiple connection clock output L1 to LN, going into end 64 to 67 pin is connected with multiple connection information input terminal T1 to TN end, go out end 77,80 pin and interface level transducer (5) are gone into end 1,7 pin connect, go into end 177 pin NAND gate (19) and go out the connection of end 3 pin; Going into to hold 200 pin and power supply (16) to go out end+V voltage end is connected, goes into to hold 104,105 pin to be connected with the ground end; Not gate (19) go into end 2 pin with resistance R 1, capacitor C 1 and K switch one end and connect, go into end 6,7 pin with resistance R 2, capacitor C 2 one ends and connect, go into end 5 pin serial connection capacitor C 3 back earth terminals, go into end 4,8 pin and resistance R 1, the R2 other end goes out end+V voltage end with power supply (16) and is connected, the K switch other end, capacitor C 1, the C2 other end and hold also and connect.