CN1832553A - DVI launching circuit and regulating method of its image data and clock phase - Google Patents
DVI launching circuit and regulating method of its image data and clock phase Download PDFInfo
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- CN1832553A CN1832553A CN 200510022210 CN200510022210A CN1832553A CN 1832553 A CN1832553 A CN 1832553A CN 200510022210 CN200510022210 CN 200510022210 CN 200510022210 A CN200510022210 A CN 200510022210A CN 1832553 A CN1832553 A CN 1832553A
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Abstract
This invention discloses an adjustment method for DVI emitting circuit, its image data and clock phase including a TMDS coder, a serial device, a clock channel delay and control module and a data channel delay module, in which, the clock channel delay and control module delays a the phase delay of the image data a first phase delay volume and outputs it to the TMDS coder, the data channel delay module delays the phase delay a second volume and outputs it to the TMDS coder and one of the two delay volumes is adjustable, the two volumes are laminated to bring forward or backward the phase of the clock corresponding to the image data so as to meet the needs of bring forward or backward.
Description
[technical field]
The present invention relates to digital visual interface (the being called for short DVI) technology in the Digital Video System, relate in particular to the radiating circuit in digital visual interface and realize high-speed data and the method for clock phase adjustment.
[background technology]
DVI is a kind of standard that connects information source system and display device, particularly cardinar number sign indicating number display device, such as LCD etc.The DVI system diagram as shown in Figure 1, a DVI display system comprises a transtation mission circuit and a receiving circuit, transtation mission circuit is the source of signal, it receives view data (being R.G.B digital signal to be shown), H.V synchronizing signal and the clock signal that image processing circuit is exported, and is transferred to receiving circuit by the DVI connecting line after treatment.Transtation mission circuit can in build in the video card chip, also can appear on the video card PCB with the form of additional chips, transtation mission circuit is realized by the DVI transmitting chip usually.Receiving circuit then is a circuit on the display, it can accept digital signal, with its decoding and be delivered in the digital display circuit, by transtation mission circuit, DVI connecting line and receiving circuit, the signal that video card sends becomes the image on the display at last, has realized the digitlization transmission between the source device numerical display device.
Because what the DVI transmitting chip received is view data and the clock signal that various image processing circuit produces, view data that various picture processing chip produced and the phase relation between the clock differ widely, make it consistent if the view data of input is not carried out the phase place adjustment with clock, just might produce the Data Receiving mistake.Therefore, be necessary that entering chip internal at data and clock carries out carrying out the phase place adjustment before TMDS (Transition Minimized Differential Signaling, the transition minimized differential signal) coding.General processing method is to add a circuit in chip exterior clock is carried out delay process, and as shown in Figure 2, view data is directly inputted to the TMDS encoder, and the clock signal experience is that circuit carries out being input to the TMDS encoder after a certain amount of time-delay.Conversion carried out also → gone here and there to view data with each pixel by the digital signal of 10hit by serializer after the TMDS encoder encodes, 4 groups of signals such as R.G.B digital stream behind the coding and pixel clock are transmitted according to the T.M.D.S. mode.But the shortcoming of this transmission means is: only be applicable to the situation that clock phase need be delayed, do not fit into the situation that clock phase need shift to an earlier date, can not adapt to the requirement of various picture processing chips.
[summary of the invention]
Main purpose of the present invention is exactly in order to solve prior art problems, a kind of DVI radiating circuit is provided, before carrying out the TMDS coding, carry out the adjustment of phase place unanimity, can either be applicable to the situation that clock phase need be delayed with respect to view data, also can be adapted to the situation that clock phase need shift to an earlier date with respect to view data, thereby adapt to the requirement of various picture processing chips.
Another object of the present invention is exactly in order to solve prior art problems, the method of adjustment of view data and clock phase in a kind of DVI radiating circuit is provided, make view data before carrying out the TMDS coding, carry out the adjustment of phase place unanimity, can either be applicable to the situation that clock phase need be delayed with respect to view data, also can be adapted to the situation that clock phase need shift to an earlier date with respect to view data, thereby adapt to the requirement of various picture processing chips.
For achieving the above object, the invention discloses a kind of DVI radiating circuit, comprising:
The TMDS encoder uses special algorithm to carry out transition minimized and data high-low level balance code and output the view data and the control signal that receive;
Serializer receives the digital signal of TMDS encoder output, carries out and go here and there the conversion back exporting; It is characterized in that also comprising:
Clock communication channel delay and control module are used to receive the clock signal of image processing circuit output, and the phase place of clock signal is delayed time outputs to the TMDS encoder behind the first phase place amount of delay;
The data channel time delay module is used to receive the view data of image processing circuit output, and the phase place of view data is delayed time outputs to the TMDS encoder behind the second phase place amount of delay;
Have at least one to be adjustable in the described first phase place amount of delay and the second phase place amount of delay.
Preferably, the described first phase place amount of delay is adjustable, described clock communication channel delay and control module comprise N delay cells connected in series and N switch element, the connect one to one output of N delay unit of the input of a described N switch element, the output of a described N switch element is connected in parallel, the control end of a described N switch element responds corresponding first group of control signal respectively, so that N switch element has only a conducting, wherein N is the integer more than or equal to 2.
Further improvement of the present invention is: also comprise the control signal decoding circuit, the input of described control signal decoding circuit is used to respond corresponding second group of control signal, the connect one to one control end of N switch element of N output.
Preferably, described N equals 8, and described control signal decoding circuit is 3 to 8 decoding circuit.
Described data channel time delay module comprises 4 delay cells connected in series.
For achieving the above object, the invention also discloses the method for adjustment of view data and clock phase in a kind of DVI radiating circuit, be used for the phase place adjustment of DVI radiating circuit before data and clock carry out the TMDS coding, it is characterized in that may further comprise the steps:
Clock communication channel delay and control module receive the clock signal of image processing circuit output, and the phase place of clock signal is delayed time outputs to the TMDS encoder behind the first phase place amount of delay;
The data channel time delay module receives the view data of image processing circuit output, and the phase place of view data is delayed time outputs to the TMDS encoder behind the second phase place amount of delay; Have at least one to be adjustable in the described first phase place amount of delay and the second phase place amount of delay.
Preferably, described clock communication channel delay and control module comprise N delay cells connected in series and N switch element, the connect one to one output of N delay unit of the input of a described N switch element, the output of a described N switch element is connected in parallel, and the phase place time-delay of clock may further comprise the steps:
The control end of A1, a N switch element responds corresponding first group of control signal respectively, so that N switch element has only a conducting;
B1, clock signal are imported from the input of N delay cells connected in series, and the first phase place amount of delay of delaying time is after the output output of this actuating switch unit; Wherein N is the integer more than or equal to 2.
Further improvement of the present invention is: further comprising the steps of before steps A 1:
The input of control signal decoding circuit responds corresponding second group of control signal, and output is exported first group of control signal and one one correspondence is coupled to the control end of N switch element.
Preferably, described N equals 8, and described control signal decoding circuit is 3 to 8 decoding circuit.
Described data channel time delay module comprises 4 delay cells connected in series.
The invention has the beneficial effects as follows: 1) clock and data are carried out the phase place time-delay respectively, wherein have at least one to be adjustable in the first phase place amount of delay and the second phase place amount of delay, can adjust according to actual conditions, the phase place that makes clock after the stack of the first phase place amount of delay and the second phase place amount of delay can shift to an earlier date also and can delay with respect to the phase place of view data, can either be applicable to the situation that clock phase need be delayed with respect to view data, also can be adapted to the situation that clock phase need shift to an earlier date with respect to view data, thereby adapt to the requirement of various picture processing chips.2) increase the control signal decoding circuit, convenient control by m input signal, can realize 2
mPlant control, simplified control port of the present invention.
Feature of the present invention and advantage will be elaborated in conjunction with the accompanying drawings by embodiment.
[description of drawings]
Fig. 1 is a DVI systematic square frame schematic diagram;
Fig. 2 is the block diagram of DVI transtation mission circuit in the prior art;
Fig. 3 is the block diagram of a kind of embodiment of DVI transtation mission circuit of the present invention;
Fig. 4 is the block diagram of the another kind of embodiment of DVI transtation mission circuit of the present invention;
Fig. 5 is the block diagram of clock communication channel delay of the present invention and control module.
[embodiment]
Specific embodiment one, as shown in Figure 3, the data channel time delay module receives the view data of image processing circuit output, output to the TMDS encoder behind the second phase place amount of delay that the phase place of view data time-delay one is fixing, clock communication channel delay and control module receive the clock signal of image processing circuit output, output to the TMDS encoder behind the first phase place amount of delay that the phase place time-delay of clock signal is adjustable, the TMDS encoder carries out the view data that receives transition minimized difference sample code and outputs to serializer, and serializer carries out the digital signal that receives and goes here and there and change back output R, G, B signal and clock signal.
The data channel time delay module is the fixing delay circuit of time-delay, and the view data of output has been delayed the second phase place amount of delay than the view data of input, is used for balance clock passage maximum delay.
Clock communication channel delay and control module are adjustable delay circuit, comprise N delay cells connected in series and N switch element, the connect one to one output of N delay unit of the input of N switch element, the output of N switch element is connected in parallel, the control end of N switch element responds corresponding first group of control signal 100 respectively, so that N switch element has only a conducting, promptly because the selection of control circuit, control the time-delay length of clock passage by N control signal in first group of control signal, realize the adjustable of the first phase place amount of delay.Wherein N is the integer more than or equal to 2.If the clock signal of clock communication channel delay and control module output is the first phase place amount of delay than the amount of delaying of the clock signal of input, the amount of delay of each delay unit is D, then D≤first phase place amount of delay≤N*D.When the first phase place amount of delay during greater than the second phase place amount of delay, clock signal is delayed with respect to view data; When the first phase place amount of delay during less than the second phase place amount of delay, clock signal with respect to view data by in advance.By this adjustment, make the phase place of clock signal and view data consistent.
Adopt N=8 in the present embodiment, promptly clock communication channel delay and control module comprise 8 identical delay units and 8 identical switch elements, and delay unit and switch element can adopt existing.Circuit diagram as shown in Figure 5,8 delay units order head and the tail are cascaded, clock signal is by the input input of first delay unit 301, through the time-delay back by the some output output in 8 switch elements.For example when first switch element 401 conductings and other switch elements when disconnecting, clock signal is delayed by 8 delay units successively, and promptly the first phase place amount of delay equals 8D.When second switch element 402 conducting and other switch elements when disconnecting, clock signal is only delayed through first delay unit 301, and promptly the first phase place amount of delay equals D.When the 3rd switch element 403 conductings and other switch elements when disconnecting, clock signal is delayed through first delay unit 301 and second delay unit 302, and promptly the first phase place amount of delay equals 2D.The rest may be inferred for other.The data channel time delay module comprises 4 identical head and the tail delay cells connected in series, and view data is delayed by 4 delay units, and the second phase place amount of delay equals 4D.Add corresponding first group of control signal 100, i.e. the switch element conducting of may command correspondence by 8 control ends giving 8 switch elements.When switch element is the high level conducting, have only one to be high level in first group of control signal 100, other are low level, only control a switch element conducting.When switch element is the low level conducting, have only one to be low level in first group of control signal 100, other are high level.
The quantity of delay unit and switch element can also be other value in clock communication channel delay and the control module.
Specific embodiment two, has as shown in Figure 4 increased the control signal decoding circuit on the basis of specific embodiment one, the control signal decoding circuit is 3 to 8 decoding circuits, and input is imported second group of control signal 200, comprises three level signals; Output is exported first group of control signal 100, comprises 8 level signals.When three input control signals when 000～111 changes, have 8 kinds to change combination, can produce 8 output signals, have one and only have one to be low level in 8 output signals all the time, all the other signals are high level.8 level signals are added to 8 control ends of switch element, only apply low level switch element conducting.Like this, if import the difference setting of three control signals, the phase place adjustment of 8 kinds of different clocks and data channel can be arranged.Just can carry out the phase place adjustment with three control signals at the input data and the clock signal of out of phase difference, output is fit to the clock of internal data processing logic and the phase relation of data.
During actual the use, determine the kind of the image processing circuit that this DVI radiating circuit is connected earlier, view data and clock according to the output of this kind image processing circuit, utilize oscilloscope adjustment, determine the combination of three level signals of the input of 3 to 8 decoding circuits, stipulate the level of these three input terminals, when using afterwards, directly three input terminals at this DVI radiating circuit add that the level of regulation gets final product.
In addition, also the first phase place amount of delay can be designed to fix, the second phase place amount of delay is designed to adjustable.
In sum, by 8 signals path length of selecting to delay time, and the delay time of delay unit circuit can accurately be controlled within limits, thereby reaches the purpose of adjusting data channel and clock channel phases relation.
Claims (10)
1. DVI radiating circuit comprises:
The TMDS encoder uses special algorithm to carry out transition minimized and data high-low level balance code and output the view data and the control signal that receive;
Serializer receives the digital signal of TMDS encoder output, carries out and go here and there the conversion back exporting; It is characterized in that also comprising:
Clock communication channel delay and control module are used to receive the clock signal of image processing circuit output, and the phase place of clock signal is delayed time outputs to the TMDS encoder behind the first phase place amount of delay;
The data channel time delay module is used to receive the view data of image processing circuit output, and the phase place of view data is delayed time outputs to the TMDS encoder behind the second phase place amount of delay;
Have at least one to be adjustable in the described first phase place amount of delay and the second phase place amount of delay.
2. DVI radiating circuit as claimed in claim 1, it is characterized in that: the described first phase place amount of delay is adjustable, described clock communication channel delay and control module comprise N delay cells connected in series and N switch element, the connect one to one output of N delay unit of the input of a described N switch element, the output of a described N switch element is connected in parallel, the control end of a described N switch element responds corresponding first group of control signal respectively, so that N switch element has only a conducting, wherein N is the integer more than or equal to 2.
3. DVI radiating circuit as claimed in claim 2, it is characterized in that: also comprise the control signal decoding circuit, the input of described control signal decoding circuit is used to respond corresponding second group of control signal, the connect one to one control end of N switch element of N output.
4. DVI radiating circuit as claimed in claim 3 is characterized in that: described N equals 8, and described control signal decoding circuit is 3 to 8 decoding circuit.
5. DVI radiating circuit as claimed in claim 4 is characterized in that: described data channel time delay module comprises 4 delay cells connected in series.
6. the method for adjustment of view data and clock phase in the DVI radiating circuit is used for the phase place adjustment of DVI radiating circuit before data and clock carry out the TMDS coding, it is characterized in that may further comprise the steps:
Clock communication channel delay and control module receive the clock signal of image processing circuit output, and the phase place of clock signal is delayed time outputs to the TMDS encoder behind the first phase place amount of delay;
The data channel time delay module receives the view data of image processing circuit output, and the phase place of view data is delayed time outputs to the TMDS encoder behind the second phase place amount of delay; Have at least one to be adjustable in the described first phase place amount of delay and the second phase place amount of delay.
7. method of adjustment as claimed in claim 6, it is characterized in that: described clock communication channel delay and control module comprise N delay cells connected in series and N switch element, the connect one to one output of N delay unit of the input of a described N switch element, the output of a described N switch element is connected in parallel, and the phase place time-delay of clock may further comprise the steps:
The control end of A1, a N switch element responds corresponding first group of control signal respectively, so that N switch element has only a conducting;
B1, clock signal are imported from the input of N delay cells connected in series, and the first phase place amount of delay of delaying time is after the output output of this actuating switch unit; Wherein N is the integer more than or equal to 2.
8. method of adjustment as claimed in claim 7 is characterized in that: further comprising the steps of before steps A 1:
The input of control signal decoding circuit responds corresponding second group of control signal, and output is exported first group of control signal and one one correspondence is coupled to the control end of N switch element.
9. method of adjustment as claimed in claim 8 is characterized in that: described N equals 8, and described control signal decoding circuit is 3 to 8 decoding circuit.
10. method of adjustment as claimed in claim 9 is characterized in that: described data channel time delay module comprises 4 delay cells connected in series.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200510022210 CN1832553A (en) | 2005-11-28 | 2005-11-28 | DVI launching circuit and regulating method of its image data and clock phase |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200510022210 CN1832553A (en) | 2005-11-28 | 2005-11-28 | DVI launching circuit and regulating method of its image data and clock phase |
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| CN1832553A true CN1832553A (en) | 2006-09-13 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101252673B (en) * | 2008-02-04 | 2010-08-25 | 西安电子科技大学 | Leakage proof apparatus and method of high speed digital video signal |
| CN101365123B (en) * | 2007-08-07 | 2011-11-02 | 日立欧姆龙金融系统有限公司 | Information display device and information display method |
| CN105372468A (en) * | 2014-08-26 | 2016-03-02 | 苏州普源精电科技有限公司 | System and method for adjusting data decoding function in oscilloscope |
| CN107479609A (en) * | 2017-09-29 | 2017-12-15 | 丁毅 | Pressure-controlled conversion switch circuit |
| CN107590093A (en) * | 2017-09-15 | 2018-01-16 | 中国科学院长春光学精密机械与物理研究所 | A kind of asynchronous view data method of reseptance based on variable phase clock module |
| CN110771159A (en) * | 2018-09-26 | 2020-02-07 | 深圳市大疆创新科技有限公司 | Image processing system and image processing method |
-
2005
- 2005-11-28 CN CN 200510022210 patent/CN1832553A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101365123B (en) * | 2007-08-07 | 2011-11-02 | 日立欧姆龙金融系统有限公司 | Information display device and information display method |
| CN101252673B (en) * | 2008-02-04 | 2010-08-25 | 西安电子科技大学 | Leakage proof apparatus and method of high speed digital video signal |
| CN105372468A (en) * | 2014-08-26 | 2016-03-02 | 苏州普源精电科技有限公司 | System and method for adjusting data decoding function in oscilloscope |
| CN105372468B (en) * | 2014-08-26 | 2019-03-05 | 苏州普源精电科技有限公司 | In the system and method for oscillograph up-regulation entire data decoding function |
| CN107590093A (en) * | 2017-09-15 | 2018-01-16 | 中国科学院长春光学精密机械与物理研究所 | A kind of asynchronous view data method of reseptance based on variable phase clock module |
| CN107590093B (en) * | 2017-09-15 | 2020-05-05 | 中国科学院长春光学精密机械与物理研究所 | Asynchronous image data receiving method based on variable phase clock module |
| CN107479609A (en) * | 2017-09-29 | 2017-12-15 | 丁毅 | Pressure-controlled conversion switch circuit |
| CN110771159A (en) * | 2018-09-26 | 2020-02-07 | 深圳市大疆创新科技有限公司 | Image processing system and image processing method |
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Open date: 20060913 |