CN212724664U

CN212724664U - Drive IC control device, display device, and electronic apparatus

Info

Publication number: CN212724664U
Application number: CN202021494178.3U
Authority: CN
Inventors: 田博仁; 谢川龙; 宋晓亮
Original assignee: Chongqing Kangjia Photoelectric Technology Research Institute Co Ltd
Current assignee: Chongqing Kangjia Optoelectronic Technology Co ltd
Priority date: 2020-07-24
Filing date: 2020-07-24
Publication date: 2021-03-16
Anticipated expiration: 2030-07-24

Abstract

The utility model relates to a drive IC controlling means, display device and electronic equipment, the device includes: FPGA and M drive ICs; the FPGA comprises N data output pins, M data output pins in the N data output pins are connected with M drive ICs in a one-to-one correspondence mode, clock pins of the FPGA are respectively connected with the M drive ICs, M is an integer larger than 1, and N is an integer larger than or equal to M. Therefore, the problem that the refresh rate of the LED display screen is low in the related technology can be solved, and the refresh rate of the LED display screen is improved.

Description

Drive IC control device, display device, and electronic apparatus

Technical Field

The utility model relates to a LED technical field especially relates to a drive IC controlling means, display device and electronic equipment.

Background

In the related art, the LED display driving IC chips are usually cascaded in series. However, in the serial cascade method, the maximum clock rate of DCLK (pixel clock signal) is determined by the driver IC chip, and when the clock rate is determined, the data rate of serial communication is 1/2 of the clock frequency. When a plurality of driving IC chips are connected in series, the time for transmitting image information for one frame becomes long because the image information transmitted by each group of serial buses increases, and the corresponding refresh rate decreases. There are also problems as follows: the data communication rate influences the number of the cascaded driving IC chips in each area and influences the subareas of the LED screen. The refresh rate is limited by the data communication rate. The cascade mode is limited by the data communication speed, and the chroma and the gray information of each region are limited.

Therefore, the problem that the refresh rate of the LED display screen is low exists in the related art. Therefore, how to increase the refresh rate of the LED screen is an urgent problem to be solved.

In view of the above problems in the related art, no effective solution has been proposed.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a driving IC control device, which aims to solve the problem of low refresh rate of the led display panel in the related art.

A drive IC control apparatus comprising: the field-editable gate array and the M drive ICs; the field editable gate array comprises N data output pins, wherein M data output pins in the N data output pins are connected with data input pins of M drive ICs in a one-to-one correspondence mode, clock pins of the field editable gate array are respectively connected with clock pins of the M drive ICs, M is an integer larger than 1, and N is an integer larger than or equal to M.

In the device, M data output pins included in the data output pins of the field editable gate array are connected with M drive ICs in a one-to-one correspondence manner, and the clock pins of the field editable gate array are respectively connected with the clock pins of the M drive ICs, so that the M drive ICs are connected in parallel, the problem of low refresh rate of the LED display screen in the related technology can be solved, and the refresh rate of the LED display screen is improved.

Optionally, the apparatus further includes a first central processing unit, wherein the first central processing unit is embedded in the field-editable gate array, and the first central processing unit is configured to perform block processing on a first image to obtain M image blocks, and correspondingly transmit the M image blocks to the M driver ICs through the M data output pins of the field-editable gate array. By carrying out block processing on the first image, the image information required by each drive IC is reduced, and the time for transmitting one frame of image information is 1/n of the time of the cascade chips (n is the number of the cascade chips), so that the refresh rate is greatly improved.

Optionally, the first central processor is a central processor capable of adjusting a parameter of the first image, wherein the parameter includes at least one of: hue, saturation, lightness, grayscale. The processing workload of the driving ICs is reduced, and the consistency of the color saturation and the gray scale of the image blocks sent to the driving ICs is ensured.

Optionally, the apparatus further includes a second central processing unit, where the second central processing unit is connected to the first central processing unit, and the second central processing unit is configured to parse a multimedia file to obtain the first image, and transmit the first image to the first central processing unit.

Optionally, the models of the M driving ICs are the same. Therefore, the consistency of the data processing rate of each driving IC is ensured, and the refresh rate of the LED display screen is further improved.

Optionally, each of the M driver ICs independently uses a set of serial buses. Thereby ensuring an increase in the number of ICs per area and a reduction in the number of receiving cards.

Optionally, the apparatus further includes a fault location module, configured to locate a faulty drive IC based on the defective area if it is determined that the content displayed on the target display screen controlled by the M drive ICs is defective. The serial communication mode is modified into the parallel communication mode, the fault location analysis of the light-emitting diode panel is facilitated, and the drive IC of the fault can be located quickly.

Optionally, the fault location module is configured to locate the fault driver IC based on the defective area by: determining control areas which are respectively controlled by the M drive ICs on the target display screen; determining a driver IC for controlling the defective region as the defective driver IC. Therefore, the fault driving can be quickly positioned by adopting a parallel connection mode, the fault positioning analysis of the light-emitting diode panel is facilitated, and the maintenance is convenient.

A display device, comprising: the light emitting diode display panel and the drive IC control device of any one of the above, wherein the drive IC control device is connected with the light emitting diode display panel.

An electronic device comprises the display device.

Drawings

Fig. 1 is a block diagram of a driving IC control device according to an embodiment of the present invention;

fig. 2 is a block diagram of a driving IC control device according to an embodiment of the present invention.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

In the related art, a CPU sends image information to a driver IC chip using a serial interface, the driver IC uses a cascade method, a DI of a first driver IC receives the image information, and the first driver IC extracts image information of its driving range and then sequentially transmits the remaining images to a next driver IC chip. The CPU simultaneously sends the clock of serial communication to the cascaded driving IC chips, the DATA signal is firstly sent to the first driving IC, the DATA output signal of the first driving IC is sent to the DATA input port of the second driving IC, and the like. With the driver IC cascade method, the maximum clock rate of DCLK (pixel clock signal) is determined by the driver IC chip, and when the clock rate is determined, the data rate of serial communication is 1/2 of the clock frequency. When a plurality of driving IC chips are connected in series, the time for transmitting image information for one frame becomes long because the image information transmitted by each group of serial buses increases, and the corresponding refresh rate decreases. The data communication rate can affect the number of the cascaded driving IC chips in each area and the subarea of the LED screen. Also, the refresh rate of the LED display is limited by the data communication rate. In addition, the use of the cascade method is limited by the data communication rate, and the chroma and the gray information of each region are limited.

Based on this, the present application intends to provide a solution to the above technical problem, the details of which will be explained in the following embodiments.

In this embodiment, a driving IC control device is provided, and fig. 1 is a block diagram of a driving IC control device according to an embodiment of the present invention, and as shown in fig. 1, the driving IC control device includes:

a Field Programmable Gate Array (FPGA) 12 and M driver ICs 14; the FPGA12 comprises N data output pins, M data output pins of the N data output pins are connected with M data input pins of the driver ICs in a one-to-one correspondence manner, clock pins of the FPGA12 are respectively connected with M clock pins of the driver ICs, M is an integer greater than 1, and N is an integer greater than or equal to M.

In the above embodiments, the FPGA12 may have multiple data output pins, each of which may be connected to a data input pin of a driver IC. The device can be applied to equipment with a display screen, such as a mobile phone, a computer, a flat panel, a display and the like.

In the device, M data output pins included in the data output pins of the FPGA12 are connected with M drive ICs 14 in a one-to-one correspondence manner, and the clock pins of the FPGA12 are respectively connected with the clock pins of the M drive ICs 14, so that the M drive ICs 14 are connected in parallel, the problem of low refresh rate of an LED display screen in the related technology can be solved, and the refresh rate of the LED display screen is improved.

In an exemplary embodiment, the apparatus further includes a first Central Processing Unit (CPU), where the first CPU is embedded in the FPGA12, and is configured to perform block Processing on a first image to obtain M image blocks, and correspondingly transmit the M image blocks to the M driving ICs 14 through the M data output pins of the FPGA12, respectively. In this embodiment, the first image may be subjected to the blocking process by the CPU embedded in the FPGA 12. After receiving the first image, the FPGA12 sends the first image to the CPU, and the CPU performs block processing on the first image and then transmits image blocks to the corresponding driver ICs 14. The FPGA12 receives image information from the CPU and simultaneously sends CLK signals (clock signals) to the driver ICs 14, each driver IC14 transmitting using one DATA line. Each driver IC14 uses a set of serial bus, that is, each driver IC14 uses a set of data line and clock line to form a serial bus, so that the communication speed can be increased without being limited by the number of driver ICs 14 that can be carried by the serial bus. When the driver ICs 14 are controlled by the pins of the FPGA12(CPU), the image information required by each driver IC14 becomes smaller, the time for transmitting one frame of image information is 1/n of the time of the cascade chips (n is the number of the cascade chips), and the refresh rate is greatly increased.

In an exemplary embodiment, the first CPU is configured to perform a blocking process on the received first image by: determining control areas controlled by the M driving ICs 14 on the target display screen respectively; and partitioning the first image according to the distribution mode of the control area on the target display screen. In this embodiment, the image may be partitioned according to the processing area corresponding to the driver IC14, one driver IC14 corresponds to one image block, that is, an area controlled by each driver IC14 on the target display screen is determined, and the first image may be partitioned according to the distribution of the control area of each driver IC14 on the target display screen.

In one exemplary embodiment, the first CPU is a CPU capable of adjusting parameters of the first image, wherein the parameters include at least one of: hue, saturation, lightness, grayscale. In this embodiment, the first CPU may adjust the hue, saturation, lightness, gradation, and the like of the received first image before performing the blocking process on the first image. That is, the CPU embedded in the FPGA12 may be used to process the image first to increase the color saturation and the gray scale of the image, that is, to adjust the color and the gray scale of the whole image, and then to perform the blocking after the adjustment. The luminance and gray scale information can also be increased by increasing the communication bandwidth of each drive IC14 chip. Therefore, the color saturation and the gray scale of the image are adjusted before the image is sent to the driving IC14, the processing workload of the driving IC14 is reduced, and the consistency of the color saturation and the gray scale of the image block sent to each driving IC14 is ensured.

In an exemplary embodiment, the first CPU is further configured to parse the received multimedia file to obtain the first image before performing the blocking process on the first image. In this embodiment, the multimedia file may be a video file or the like. When the multimedia file is a video, the first CPU analyzes the video file after receiving the video file to obtain a current frame image, and then performs blocking processing on the current frame image.

In an exemplary embodiment, the apparatus further includes a second CPU, where the second CPU is connected to the first CPU, and the second CPU is configured to parse a multimedia file to obtain the first image, and transmit the first image to the first CPU. In this embodiment, the second CPU may be a CPU embedded in the FPGA12, or may be a CPU independent from the FPGA12, and the second CPU is connected to the first CPU and configured to parse the multimedia file to obtain the first image, and transmit the parsed multimedia file to the first CPU.

In one exemplary embodiment, the M driver ICs 14 are the same model. In the embodiment, the same driving IC14 is used, so that the consistency of the data processing rate of each driving IC14 is ensured, and the refresh rate of the LED display screen can be improved.

In one exemplary embodiment, each of the M driver ICs 14 of the driver ICs 14 independently uses a set of serial buses. In this embodiment, the number of ICs in a set of serial buses is called a local IC. Each driver IC14 uses a set of serial buses individually, which corresponds to only one driver IC14 in one sector, so that there is no need to consider the number of driver ICs 14 that can be carried by a set of serial buses, and more sectors can be used, i.e., parallel communication is used, the number of ICs per sector is increased, and the number of receiving cards can be reduced. The structural block diagram of the Driver IC14 control device according to the embodiment of the present invention can be seen in fig. 2, as shown in fig. 2, the data input pin of each Driver IC14 (i.e., Driver IC) is connected to the data output pin of the FPGA12 (e.g., the DI pin of the Driver IC is connected to the D0 (e.g., D01, D02, D03) pin of the FPGA), the clock pin of the FPGA12 is also connected to the clock pins of the plurality of Driver ICs 14, in addition, there may be a spare data output pin in the FPGA12, and when the Driver IC14 needs to be extended, the spare data output pin in the FPGA12 may be used to connect to the extended Driver IC14, so as to implement the extension of the Driver IC 14.

In one exemplary embodiment, the apparatus further comprises a fault location module for locating a faulty drive IC14 based on a defective area if it is determined that a defect occurs in content displayed on a target display screen controlled by M of the drive ICs 14. In the embodiment, a serial communication mode is modified into a parallel communication mode, so that the LED screen fault location analysis is facilitated.

In one exemplary embodiment, the fault location module is used to locate the fault driver IC14 based on the defective region by: determining control areas controlled by the M driving ICs 14 on the target display screen respectively; the driver IC14 for controlling the defective region is determined as the failed driver IC 14. In this embodiment, after determining the control region controlled by each driver IC14, when a failure occurs in a certain region, the driver IC14 corresponding to the region may be determined to be the failed driver IC 14. Therefore, the parallel connection mode can be used for quickly positioning the fault drive, the fault positioning analysis of the LED screen is facilitated, and the maintenance is convenient.

In this embodiment, an LED display device is further provided, which includes an LED display panel and the driver IC control device described in any one of the above, where the driver IC control device is connected to the LED display panel. In this embodiment, the LED display device may be a display screen, for example, a mobile phone display screen, a computer display screen, a tablet computer display screen, a display screen in an intelligent wearable device, a television display screen, and the like.

In the embodiment, an electronic device is also provided, and the electronic device comprises the LED display device. In this embodiment, the electronic device may be a mobile phone, a computer, a tablet computer, a television, a smart wearable device, or other devices including a display device.

The light emitting diode driven by the driving IC14 may be a miniLED or a micro led (micro light emitting diode). It is to be understood that the invention is not limited to the above-described embodiments, and that modifications and variations may be made by those skilled in the art in light of the above teachings, and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.

Claims

1. A drive IC control apparatus, comprising:

the field-editable gate array and the M drive ICs;

the field editable gate array comprises N data output pins, wherein M data output pins in the N data output pins are connected with data input pins of M drive ICs in a one-to-one correspondence mode, clock pins of the field editable gate array are respectively connected with clock pins of the M drive ICs, M is an integer larger than 1, and N is an integer larger than or equal to M.

2. The driver IC control apparatus according to claim 1, further comprising a first central processor, wherein the first central processor is embedded in the field-editable gate array,

the first central processing unit is used for carrying out blocking processing on a first image to obtain M image blocks, and correspondingly transmitting the M image blocks to the M driving ICs through the M data output pins of the field editable gate array.

3. The drive IC control apparatus according to claim 2, wherein the first cpu is a cpu capable of adjusting parameters of the first image, wherein the parameters include at least one of:

hue, saturation, lightness, grayscale.

4. The drive IC control apparatus of claim 2, further comprising a second central processing unit, wherein the second central processing unit is connected to the first central processing unit, and the second central processing unit is configured to parse a multimedia file to obtain the first image, and transmit the first image to the first central processing unit.

5. The drive IC control apparatus according to claim 1, wherein M drive ICs are the same in model number.

6. The drive IC control apparatus according to claim 1, wherein each of the M drive ICs independently uses a set of serial buses.

7. The drive IC control apparatus according to claim 1, further comprising a failure location module for locating a failed drive IC based on a defective region in a case where it is determined that a defect occurs in content displayed on a target display screen controlled by the M drive ICs.

8. The drive IC control apparatus according to claim 7, wherein the fault location module is configured to locate the faulty drive IC based on the defective area by:

determining control areas which are respectively controlled by the M drive ICs on the target display screen;

determining a driver IC for controlling the defective region as the defective driver IC.

9. A display device, comprising:

a light emitting diode display panel and the driver IC control apparatus of any one of claims 1 to 8, wherein the driver IC control apparatus is connected to the light emitting diode display panel.

10. An electronic device, comprising: the display device of claim 9.