CN100530259C - Power system data transmission device - Google Patents
Power system data transmission device Download PDFInfo
- Publication number
- CN100530259C CN100530259C CNB2008100172303A CN200810017230A CN100530259C CN 100530259 C CN100530259 C CN 100530259C CN B2008100172303 A CNB2008100172303 A CN B2008100172303A CN 200810017230 A CN200810017230 A CN 200810017230A CN 100530259 C CN100530259 C CN 100530259C
- Authority
- CN
- China
- Prior art keywords
- data
- module
- clock
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses an electric power system data transmission device, which comprises a transmission network including a master communication portion and a plurality of slave communication portions with the same structure. The master communication portion includes a synchrodata transmission module and a DSP processor connected with a two-channel signal thereof. The input of the synchrodata transmission module is connected with signal output lines and data lines of a plurality of A/D collectors, and the output thereof is connected with a transmission differential module which is divided into a clock differential transmission circuit and a data differential transmission circuit. The slave communication module includes a synchrodata receiving module and an ARM processor connected with a two-channel signal thereof. The input of the synchrodata receiving module is connected with a receiving differential module which is divided into a clock differential receiving circuit and a data differential receiving circuit. The clock differential receiving circuit is connected with the clock differential transmission circuit via a clock line. The data differential receiving circuit is connected with the data differential transmission circuit via the data lines.
Description
Technical field
The present invention relates to a kind of transmitting device of electric power system control data.
Background technology
At present, digital communication mode is varied, the communication interface that we use always has IIC, SPI, RS-485 etc., wherein the advantage of iic bus is that wiring is few, only just can finish data synchronization with two lines transmits, but being limited by that the bus capacitance maximum allows is the restriction of 400pF, and its maximum transmission line distance is 10ft (1ft=0.3408m), and its transfer rate can reach 3.4Mbit/s under the high speed transfer mode; Though SPI is a kind of high speed (3Mbit/s), full duplex and synchronous communication bus, what it adopted also is single-ended transmission, the weak point of comparing when effective propagation path transmits data with the employing differential mode; Though the mode that RS485 has adopted difference to transmit is transmitted data, anti-film interference performance altogether and noise immunity strengthen greatly, and transfer rate also can reach 10Mbit/s, and maximum transmission distance can reach 3Km; But RS485 belongs to asynchronous data transfer, is that unit transmits with the character, does not have the efficient height of synchronous data transmission; Analyze above-mentioned as can be known communication bus and all have separately deficiency.
In the HVDC (High Voltage Direct Current) transmission system, we adopt reactive power compensator that the idle of system compensated, we have lot of data to need to handle in the implementation process of control strategy, the concrete data that different control units is paid close attention to and the computing method of employing also are not quite similar, if these calculating all use the MCU of same unit to calculate, when calculated amount is bigger, certainly will bring the problem of system data transmission, bring the logic determines of carrying out and the enforcement of control strategy timely and effectively not to carry out thus, be security of system based on result of calculation and each switch input quantity, reliably, economical operation brings hidden danger.
Summary of the invention
The technical problem to be solved in the present invention provide a kind of anti-film interference performance altogether and noise immunity strong, thereby increase effective transmitting range of data, networking simultaneously is power system data transmission device easily.
For reaching above purpose, the present invention takes following technical scheme to be achieved:
A kind of power system data transmission device comprises a transmission network from the communications portion composition that main communications portion is identical with several structures; Described main communications portion comprises a synchrodata sending module and the dsp processor that is connected with its two-way signaling, the input of described synchrodata sending module connects the output line and the data line of a plurality of A/D collectors, the input connection mode analog signal of A/D collector; The output of synchrodata sending module is connected to the transmission difference block, sends difference block and is divided into clock difference transtation mission circuit and data difference transtation mission circuit; Describedly comprise a synchrodata receiver module and the arm processor that is connected with its two-way signaling from communications portion, the input of described synchrodata receiver module connects the reception difference block, receives difference block and is divided into clock differential received circuit and data difference receiving circuit; Clock differential received circuit connects the clock difference transtation mission circuit of main communications portion by clock line; The data difference receiving circuit connects the data difference transtation mission circuit of main communications portion by data line.
In the such scheme, send the clock difference transtation mission circuit of difference block and the output of data difference transtation mission circuit and all can be provided with the first resistors match circuit; Receive the clock differential received circuit of difference block and the input of data difference receiving circuit and all can be correspondingly provided with the second resistors match circuit; Clock difference transtation mission circuit and clock differential received circuit are to be coupled together by clock line by the first resistors match circuit and the second resistors match circuit; Data difference transtation mission circuit and data difference receiving circuit also are to be coupled together by data line by the first resistors match circuit and the second resistors match circuit.
Described synchrodata sending module comprises the clock phase-locked loop that is connected to the output of crystal oscillator clock, and its output connects A/D timing management module respectively and the bus transfer rate is selected module; The bus transfer rate selects the output of module to connect the synchronous sequence sending module; A/D timing management module is connected with a plurality of A/D collector two-way signalings; The output of A/D timing management module is connected with the input in the first data buffering pond and the second data buffering pond; The first data buffering pond is connected with each A/D collector by BDB Bi-directional Data Bus with the second data buffering pond, and the first data buffering pond is connected with the dsp processor two-way signaling simultaneously; The output in the second data buffering pond sends the start detection module by one and connects the synchronous sequence sending module, and the output of synchronous sequence sending module connects clock difference transtation mission circuit, parallel serial conversion module, the transmission detection of end reseting module that sends difference block respectively; Parallel serial conversion module is connected with the second data buffering pond two-way signaling, and the output of parallel serial conversion module is connected to the data difference transtation mission circuit that sends difference block; The output that sends the detection of end reseting module connects second data buffering pond and the parallel serial conversion module.
Described synchrodata receiver module comprises and receives receiving management module and the synchronous sequence detection module that difference block output is connected, the output of synchronous sequence detection module connects the receiving management module, and the output that connects the receiving management module connects a string also modular converter, a reception detection of end reseting module respectively; String and modular converter are connected with one the 3rd data buffering pond two-way signaling; The output in the 3rd data buffering pond connects the receiving management module; The output that receives the detection of end reseting module connects synchronous sequence detection module, string and modular converter and the 3rd data buffering pond; Wherein the receiving management module is connected with arm processor by bidirectional signal line with the 3rd data buffering pond.
It is that the first resistors match circuit that sends the difference block output terminal is in order to carry out impedance matching with the impedance of circuit self that the input that the present invention sends the output of difference block and receives difference block is provided with technique effect that the resistors match circuit brought; And the second resistors match circuit that receives the difference block input end receives the needed voltage signal of difference block input end except producing, and can also increase the noise margin of circuit.
Synchrodata sending module of the present invention and synchrodata receiver module can adopt FPGA to realize, can give full play to the strong characteristics of FPGA parallel data processing power, guarantee the quick transmission of data.The Clock management of synchrodata sending module has the phaselocked loop of FPGA self to realize, the clock of accurate and optional different rates can be provided for system works.The data buffering pond adopts the FPGA internal RAM to realize, the degree of depth and bit wide are adjusted very convenient.Each main modular is integrated in the FPGA, and system works stability and anti-interference have remarkable enhancing.
The present invention compares the mode of difference transmission in conjunction with synchronous communication that adopted with the available data transmitting device, make both advantages, and communication protocol is succinct, so just can guarantee communications efficient height, and transfer rate is fast, it is anti-that the film interference performance is strong altogether, noise immunity is good, and transmitting range is far away, and system power dissipation is low, networking is convenient, flexible configuration.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Fig. 2 is the networking synoptic diagram of apparatus of the present invention.
Fig. 3 is the theory diagram of the synchrodata sending module among Fig. 1.
Fig. 4 is the theory diagram of the synchrodata receiver module among Fig. 1.
Fig. 5 is the realization schematic diagram of synchronous sequence sending module among Fig. 3.
Fig. 6 is the realization schematic diagram of synchronous sequence detection module among Fig. 4.
Fig. 7 is the position transmission time sequence figure of clock and data line synchronous communication in apparatus of the present invention.Wherein Fig. 7 a is a position transmission time constraint rule sequential chart; Fig. 7 b is that position transmission initial sum stops sequential requirement figure.
Embodiment
Below in conjunction with drawings and Examples the present invention is described in further detail.
As shown in Figure 1 and Figure 2, a kind of power system data transmission device comprises a transmission network from the communications portion composition that main communications portion is identical with several structures; Main communications portion comprises a synchrodata sending module and the dsp processor that is connected with its two-way signaling, the input of synchrodata sending module connects three A/D collectors (can expand to N, N＞3) output line and data line,, the input connection mode analog signal of each A/D collector; The output of synchrodata sending module is connected to the transmission difference block, sends difference block and is divided into clock difference transtation mission circuit CLK_Driver and data difference transtation mission circuit DATA_Driver.
Comprise a synchrodata receiver module and the arm processor that is connected with its two-way signaling from communications portion, the input of synchrodata receiver module connects the reception difference block, receives difference block and is divided into clock differential received circuit CLK_Receiver and data difference receiving circuit DATA_Receiver; The input of CLK_Receiver connects the CLK_Driver output of main communications portion by clock line; The input of DATA_Receiver connects the DATA_Driver output of main communications portion by data line.Wherein, send the clock difference transtation mission circuit CLK_Driver of difference block and the output of data difference transtation mission circuit DATA_Driver and be provided with the first resistors match circuit; Receive the clock differential received circuit CLK_Receiver of difference block and the input of data difference receiving circuit DATA_Receiver and be provided with the second resistors match circuit.Clock difference transtation mission circuit and clock differential received circuit are to be coupled together by clock line by the first resistors match circuit and the second resistors match circuit; Data difference transtation mission circuit and data difference receiving circuit also are to be coupled together by data line by the first resistors match circuit and the second resistors match circuit.
The data flow of above-mentioned data communication equipment (DCE) is: synchrodata sending module control A/D carries out timing and starts, and image data, data acquisition finishes and gives the DSP of main communications portion after packing is got well, the data that another is packed pass out to synchrodata receiver module from communications portion in the synchronous mode of difference simultaneously, find that Data Receiving is errorless then give ARM from communications portion data if the synchrodata receiver module receives verification.
As shown in Figure 3, be about the theory diagram of synchrodata sending module among Fig. 1, each several part is: clock phase-locked loop, and the bus transfer rate is selected module, A/D timing management module, the first data buffering pond, the second data buffering pond sends the start detection module, the synchronous sequence sending module, parallel serial conversion module sends the detection of end reseting module.
The input of clock phase-locked loop is connected to the clock output of source crystal oscillator, and it is output as the synchronous clock of various different frequencies, connects the input of A/D timing management module and bus transfer rate respectively and selects being input as it separately work clock being provided of module; Output clock and Bus Speed that the bus transfer rate selects the input of module to connect clock phase-locked loop are selected wire jumper, the bus transfer rate selects the output of module to connect the input of synchronous sequence sending module, can select the clock of corresponding frequencies to give the synchronous sequence sending module by wire jumper, thereby change the speed of synchronous data transmission; The clock input of A/D timing management module connects the clock output of clock phase-locked loop, it links to each other with the A/D collector with an incoming line by four output lines, article four, two in the output line are used for controlling respectively resetting of A/D, start, article one, whether incoming line is used for detecting A/D collector data-switching and finishes, after data-switching is finished condition and is satisfied, thereby four the two other in the output line is used to send the data that sheet choosing and read request change the A/D collector and delivers to the first data buffering pond and the second data buffering pond, A/D timing management module also has one tunnel output signal to be connected with the input in the first data buffering pond and the second data buffering pond simultaneously, thus the data that are used for cooperating the sequential that sends to the A/D collector that the A/D collector is changed correct deliver to the first data buffering pond and the second data buffering pond; The first data buffering pond is connected with the A/D collector by 16 BDB Bi-directional Data Bus, its input timing is from the output timing of A/D timing management module, under the control of the output timing of A/D timing management module, receive the data of changing from the A/D collector by bidirectional data line, after finishing Data Receiving, notify the DSP of main communications portion that data are read away in the mode of interrupting, after the DSP reading of data finished, the first data buffering pond was again that the collection of data next time is ready; The input in the second data buffering pond has from the output timing of A/D timing management module and the output timing of parallel serial conversion module, the data bus that is connected to the second data buffering pond has two groups, be respectively to be connected with the A/D collector with output data bus and be connected with the data input bus (DIB) of parallel serial conversion module by BDB Bi-directional Data Bus, the function that this module is finished is that the data of under the control of the output timing of A/D timing management module the A/D collector being changed write, under the control of parallel serial conversion module output timing, parallel data is delivered to simultaneously the input end of parallel serial conversion module, certainly the read-write here is not to carry out simultaneously, but timesharing is carried out under the control of clock; The input that sends the start detection module is connected with the output in the second data buffering pond, its output is connected with the input of synchronous sequence sending module, the function that this module is finished is, satisfy to send when requiring when detecting input timing, give one of synchronous sequence sending module and start the signal that synchronous sequence takes place; Module and the output that sends the start detection module are selected in the input of synchronous sequence sending module connecting bus transfer rate respectively, the output of this module is imported with the serial clock of parallel serial conversion module respectively, the reset condition that sends the detection of end reseting module detects input end, the data input pin that sends difference block links to each other, the function that the synchronous sequence sending module is mainly finished is: produce two-way after sending the enabling signal that the start detection module sends here synchronously with clock frequently when detecting, one the tunnel delivers to the input end of clock that sends difference block, be used to produce the synchronous clock of data sync transmission, one road clock is given parallel serial conversion module and is used for realizing the conversion of parallel data to serial data; The input end that sends the detection of end reseting module detects and produces a reset signal behind the signal that transmission that the output terminal of synchronous sequence sending module sends here finishes and give the second data buffering pond, synchrodata sending module, parallel serial conversion module respectively it is resetted, for next time data acquisition with to produce synchronous sequence ready; The input end of clock that sends difference block links to each other with the synchronous sequence output terminal of synchronous sequence sending module, data input pin links to each other with the serial data output terminal of parallel serial conversion module, wherein clock and data keep the synchronous of strictness in design, and input clock and data-signal pass out to from the clock difference of communications portion reception difference block, the input end of data difference circuit after difference block is converted to differential signal by sending.
As shown in Figure 4, be among Fig. 1 about the theory diagram of synchrodata receiver module, the each several part of composition is: the synchronous sequence detection module, string and modular converter, the 3rd data buffering pond, the receiving management module receives the detection of end reseting module.
After the input end that receives difference block receives the differential clocks and data-signal that sends from main communications portion, by clock be connected with the input end of synchronous sequence detection module after data sink is converted to single-ended data with differential signal; The input end of synchronous sequence detection module detects synchronous clock and data input signal, after finding that data are effectively transmitted, produce a startup received signal and link to each other, when data transmission finishes, produce a termination signal and link to each other with the input end of receiving management module by the input end of output terminal with the receiving management module; Two input ends of receiving management module also are connected with data output end with the clock of differential received module simultaneously, start transmission and will deliver to string and modular converter with data-signal by the output terminal that is connected with string and two input ends of modular converter from the clock that the differential received module is brought when effective when the input end that is connected with the synchronous sequence detection module detects, we see that an input end of this module is connected with an output terminal in the 3rd data buffering pond, be used to detect the 3rd data buffering pond and whether write completely and read sky, when detect data write full after then by reading data in the 3rd data buffering pond with being connected of ARM with interrupt mode notice ARM, when the data in detecting the 3rd data buffering pond are read sky, then send one and reset useful signal to receiving the detection of end reseting module by the data line that is connected with the input end that receives the detection of end reseting module; The input end of string and modular converter is connected with data output end with the clock of receiving management module, pass out to data output end after being used for after start receiving data under the control at synchronous clock the serial synchrodata is converted to parallel data, its data output end is connected with the data input pin in the 3rd data buffering pond, and the output terminal of the clock of writing the 3rd data buffering pond of this module is connected with the input end of clock of writing in the 3rd data buffering pond; The 3rd data buffering pond under the control of writing clock input, will go here and there and parallel data that modular converter is brought writes Buffer Pool, when finding to write full or ARM then notifies the receiving management module by the output terminal that is connected with the receiving management module input when reading sky; The input end that receives the detection of end reseting module is connected with the useful signal output terminal that resets of receiving management module, reset effectively when detecting that the back produces synchronous sequence detection module, string and modular converter, the 3rd data buffering pond that a reset pulse is used for resetting and is connected with its output terminal, for reception is next time got ready.
As shown in Figure 5, be the realization schematic diagram of synchronous sequence sending module among Fig. 3, this functions of modules realizes with VHDL programming, and this figure be the schematic diagram that obtains after comprehensively through Quartus II compiler.Wherein import the reset terminal that the corresponding transmission of RESET detection of end reseting module outputs to the synchronous sequence sending module, the corresponding line that sends output of start detection module and synchronous sequence module of WRFULL, be used for starting the generation synchronous sequence signal when satisfying condition, the corresponding synchronous sequence sending module of LVDS_ST_CLK outputs to the line that sends the difference block input end of clock, the corresponding synchronous sequence sending module of T_SP_CLK outputs to the line of the serial clock input end of parallel serial conversion module, the corresponding synchronous sequence sending module of END_RESET outputs to the line that sends detection of end reseting module input end, and wherein CLK128M and CLK16M are the system works clock.The principle of work of synchronous sequence sending module correspondence is illustrated when setting forth the principle of work of synchrodata sending module.
Fig. 6 is the realization schematic diagram of synchronous sequence detection module among Fig. 4.This functions of modules realizes with VHDL programming, and this figure be the schematic diagram that obtains after comprehensively through Quartus II compiler.The wherein clock and the data input pin of the corresponding respectively synchronous sequence detection module that is connected with reception difference block output terminal of LVDS_RS_CLK and LVDS_RS_DATA, the corresponding synchronous sequence detection module of START_EN outputs to the output terminal of receiving management module, is used for sending one to the receiving management module and receives enabling signal; The corresponding synchronous sequence detection module of END_EN outputs to the output terminal of receiving management module, is used for sending the transmission that a transmission ending signal stops data to the receiving management module.The principle of work of synchronous sequence detection module is illustrated when setting forth the principle of work of synchrodata receiver module.
Figure 7 shows that the position transmission time sequence figure of clock and data line synchronous communication in apparatus of the present invention.Need to prove that what sequential chart was represented is through before the transmission difference block and through the clock after the reception difference block and the transmission time sequence figure of the Transistor-Transistor Logic level standard signal on the data line.Wherein Fig. 7 a is a position transmission time constraint rule sequential chart, the basic demand in the transport process be data term of validity T2 greater than the positive term of validity T1 of clock, the conversion period T3 of data should be less than the negative term of validity T4 of clock.Like this each rising edge of clock or negative edge all certainly data correctly gather; Fig. 7 b is that the sequential that position transmission initial sum stops requires figure, from figure we can draw when the clock signal be between high period, if produce a negative edge on the data line, then think to send and start, if clock signal is between high period, fall the edge on producing one on the data line, then think to send to stop.
Claims (4)
1. a power system data transmission device is characterized in that, comprises a transmission network from the communications portion composition that main communications portion is identical with several structures; Described main communications portion comprises a synchrodata sending module and the dsp processor that is connected with its two-way signaling, the input of described synchrodata sending module connects the output line and the data line of a plurality of A/D collectors, the input connection mode analog signal of A/D collector, the output of synchrodata sending module is connected to the transmission difference block, sends difference block and is divided into clock difference transtation mission circuit and data difference transtation mission circuit; Describedly comprise a synchrodata receiver module and the arm processor that is connected with its two-way signaling from communications portion, the input of described synchrodata receiver module connects the reception difference block, receives difference block and is divided into clock differential received circuit and data difference receiving circuit; Clock differential received circuit connects the clock difference transtation mission circuit of main communications portion by clock line; The data difference receiving circuit connects the data difference transtation mission circuit of main communications portion by data line.
2. described power system data transmission device according to claim 1 is characterized in that, the clock difference transtation mission circuit of described transmission difference block and the output of data difference transtation mission circuit are provided with the first resistors match circuit; Receive the clock differential received circuit of difference block and the input of data difference receiving circuit and be provided with the second resistors match circuit; Clock difference transtation mission circuit and clock differential received circuit are to be coupled together by clock line by the first resistors match circuit and the second resistors match circuit; Data difference transtation mission circuit and data difference receiving circuit also are to be coupled together by data line by the first resistors match circuit and the second resistors match circuit.
3. described power system data transmission device according to claim 1 and 2, it is characterized in that, described synchrodata sending module comprises the clock phase-locked loop that is connected to the output of crystal oscillator clock, and its output connects A/D timing management module respectively and the bus transfer rate is selected module; The bus transfer rate selects the output of module to connect the synchronous sequence sending module; A/D timing management module is connected with a plurality of A/D collector two-way signalings; The output of A/D timing management module is connected with the input in the first data buffering pond and the second data buffering pond; The first data buffering pond is connected with each A/D collector by BDB Bi-directional Data Bus with the second data buffering pond, and the first data buffering pond is connected with the dsp processor two-way signaling simultaneously; The output in the second data buffering pond sends the start detection module by one and connects the synchronous sequence sending module, and the output of synchronous sequence sending module connects clock difference transtation mission circuit, parallel serial conversion module, the transmission detection of end reseting module that sends difference block respectively; Parallel serial conversion module is connected with the second data buffering pond two-way signaling, and the output of parallel serial conversion module is connected to the data difference transtation mission circuit that sends difference block; The output that sends the detection of end reseting module connects the second data buffering pond, synchronous sequence sending module and parallel serial conversion module.
4. described power system data transmission device according to claim 1 and 2, it is characterized in that, described synchrodata receiver module comprises and receives receiving management module and the synchronous sequence detection module that difference block output is connected, the output of synchronous sequence detection module connects the receiving management module, and the output that connects the receiving management module connects a string also modular converter, a reception detection of end reseting module respectively; String and modular converter are connected with one the 3rd data buffering pond two-way signaling; The output in the 3rd data buffering pond connects the receiving management module; The output that receives the detection of end reseting module connects synchronous sequence detection module, string and modular converter and the 3rd data buffering pond; Wherein the receiving management module is connected with arm processor by bidirectional signal line with the 3rd data buffering pond.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2008100172303A CN100530259C (en) | 2008-01-04 | 2008-01-04 | Power system data transmission device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2008100172303A CN100530259C (en) | 2008-01-04 | 2008-01-04 | Power system data transmission device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101216992A CN101216992A (en) | 2008-07-09 |
| CN100530259C true CN100530259C (en) | 2009-08-19 |
Family
ID=39623421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2008100172303A Expired - Fee Related CN100530259C (en) | 2008-01-04 | 2008-01-04 | Power system data transmission device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100530259C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101404521B (en) * | 2008-11-07 | 2013-03-06 | 北京铱钵隆芯科技有限责任公司 | Master-slave mode direct current carrier communication system and its control flow |
| WO2010051767A1 (en) * | 2008-11-07 | 2010-05-14 | 北京铱钵隆芯科技有限责任公司 | Communication system of master-slave mode direct current carrier |
| CN108616282A (en) * | 2018-03-30 | 2018-10-02 | 四川斐讯信息技术有限公司 | A kind of anti-interference equipment |
| US10470264B1 (en) * | 2018-08-24 | 2019-11-05 | Monolithic Power Systems, Inc. | Smart communication interface for LED matrix control |
| DE102019213982A1 (en) * | 2019-09-13 | 2021-03-18 | Dr. Johannes Heidenhain Gmbh | Device and method for synchronous serial data transmission |
| CN113055050B (en) * | 2021-03-25 | 2022-03-15 | 深圳市东昕科技有限公司 | Wired communication circuit and wired communication system |
| CN114527693B (en) * | 2022-01-27 | 2023-03-07 | 珠海昇生微电子有限责任公司 | Differential bidirectional communication circuit and method capable of customizing sending and receiving communication formats |
| CN115168272A (en) * | 2022-07-18 | 2022-10-11 | 江苏科技大学 | Long-distance serial line debugging interface circuit and signal transmission method |
-
2008
- 2008-01-04 CN CNB2008100172303A patent/CN100530259C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101216992A (en) | 2008-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100530259C (en) | Power system data transmission device | |
| CN102057417B (en) | Display driving system using transmission of single-level signal embedded with clock signal | |
| CN104113740B (en) | A kind of mixed format signal transmission by optical fiber device | |
| CN104484306B (en) | Master-slave synchronisation serial communication bus and its implementation based on differential signal | |
| CN102868584B (en) | Synchronization time-division multiplexing bus communication method adopting serial communication interface | |
| CN101312302B (en) | Parallel signal transmission method of uninterrupted power source | |
| CN203120211U (en) | Data conversion device of flexible LED driver and dimming system | |
| CN104991880B (en) | A kind of FC AE ASM Communication Cards based on PCI E interfaces | |
| CN102393531A (en) | Data transmission system for seismic exploration | |
| CN108494433B (en) | Single-wire communication method and circuit implementation thereof | |
| CN102692642B (en) | Transmission of seismic data device based on ethernet PHY transceiver | |
| CN205038640U (en) | Solve SPI bus communication delayed SPI equipment | |
| CN101916543B (en) | Data communication method of LED display system | |
| CN102546033A (en) | Multimachine communication device achieved by adopting pulse modulation combined with serial port mode | |
| CN102075397A (en) | Direct interfacing method for ARINC429 bus and high-speed intelligent unified bus | |
| CN106066838A (en) | Extension module based on FPGA multichannel UART and extended method | |
| CN201378851Y (en) | CCD image data collecting device | |
| CN103970692A (en) | RapidIO serial data processing method | |
| CN101887635B (en) | High-resolution multi-channel seismic exploration data transmission system at shallow layer of deepwater | |
| CN213457702U (en) | 32-channel AD data acquisition control panel based on HSC serial bus interface | |
| CN206363300U (en) | A kind of battery management chip daisy chain communication system | |
| CN103078667A (en) | Low voltage differential signaling (LVDS) high-speed data transmission method based on cat-5 | |
| CN101547054B (en) | Data receiving device of parallel optical inter-connected system based on programmable device and method thereof | |
| CN103888211A (en) | Method and device for data transmission between crossed chips | |
| CN1964245B (en) | RS485 character-oriented anti-interference device against idle synchronous serial communication bus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: WEST CHINA ELECTRIC POWER CO. Free format text: FORMER OWNER: XI'AN ELECTRIC MANUFACTURING CORP. Effective date: 20080905 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20080905 Address after: Shaanxi province Xi'an City West High Tang Hing Road No. 7 post encoding: 710075 Applicant after: China XD Electronic Corporation Address before: No. 29 North Road, Shaanxi post encoding Fengdeng city in Xi'an Province: 710077 Applicant before: Xi'an Electric Manufacturing Corp. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Xi'an XD Automated Control System Co., Ltd. Assignor: China XD Electronic Corporation Contract record no.: 2011610000095 Denomination of invention: Power system data transmission device Granted publication date: 20090819 License type: Exclusive License Open date: 20080709 Record date: 20110712 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090819 Termination date: 20190104 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |