CN220775798U

CN220775798U - Capacitive switch circuit, feedback control circuit, frequency locking loop circuit, chip and electronic equipment

Info

Publication number: CN220775798U
Application number: CN202321423049.9U
Authority: CN
Inventors: 朱守佳; 蔡炎
Original assignee: Hefei Chipsea Electronics Technology Co Ltd
Current assignee: Hefei Chipsea Electronics Technology Co Ltd
Priority date: 2023-06-05
Filing date: 2023-06-05
Publication date: 2024-04-12
Anticipated expiration: 2033-06-05

Abstract

The application relates to the technical field of integrated circuits, in particular to a capacitance switch circuit, a feedback control circuit, a frequency locking loop circuit, a chip and electronic equipment, which comprises a filter capacitance unit and an auxiliary capacitance switch circuit, wherein a first end of the filter capacitance unit is used for receiving a first power supply voltage, and a second end of the filter capacitance unit is used for outputting a control voltage; the auxiliary capacitance switching circuit comprises an auxiliary capacitance unit and a switching unit, wherein a first end of the auxiliary capacitance unit is used for receiving a first power supply voltage, and the switching unit is used for connecting a second end of the auxiliary capacitance unit with a second end or a grounding end of the filter capacitance unit; by the mode, at the moment of completing power-on, the charges of the filter capacitor unit and the auxiliary capacitor unit are shared, the control voltage is instantaneously pulled down from the first power supply voltage at the moment of completing power-on, the establishment speed of the target control voltage is accelerated, and the improvement of working efficiency is facilitated.

Description

Capacitive switch circuit, feedback control circuit, frequency locking loop circuit, chip and electronic equipment

Technical Field

The application relates to the technical field of integrated circuits, in particular to a capacitive switch circuit, a feedback control circuit, a frequency locking loop circuit, a chip and electronic equipment.

Background

In the feedback control circuit, a control signal generating circuit generates a control signal according to the received control voltage, and the target parameter of the control signal is controlled to fluctuate in a small range through dynamic feedback adjustment. After power-up, a preset control voltage corresponding to a preset target parameter needs to be provided for the control signal generation circuit. The feedback control circuit mainly comprises a phase-locked loop circuit, a frequency-locked loop circuit, an automatic gain control circuit and the like, and the target parameters can be signal amplitude, signal frequency or signal phase and the like. For example, in the frequency-locked loop circuit, the voltage-controlled oscillation circuit generates a frequency-locked loop output signal according to the received control voltage, and the frequency-locked loop output signal is controlled to a preset frequency through dynamic feedback adjustment. After power-up, a preset control voltage corresponding to a preset frequency needs to be provided for the voltage-controlled oscillation circuit.

In the background art, after power is applied, the control voltage provided to the control signal generating circuit is an initial voltage, the initial target parameter output by the control signal generating circuit is 0, the control voltage provided to the control signal generating circuit gradually decreases as the feedback control circuit starts to work, the target parameter output by the control signal generating circuit gradually increases from 0, and when the control voltage provided to the control signal generating circuit decreases to a preset control voltage, the target parameter of the control signal output by the control signal generating circuit is a preset target parameter. In the above establishment process of the preset target parameter, the control voltage needs to be reduced from the initial voltage to the preset control voltage for a first time, and the feedback control circuit needs to wait for the first time to start effective work after being electrified, so that the establishment speed of the preset target parameter is slower, and the improvement of the working efficiency is not facilitated.

Disclosure of Invention

In view of the above problems, embodiments of the present application provide a capacitive switch circuit, a feedback control circuit, a frequency locking loop circuit, a chip, and an electronic device, so as to solve the above technical problems.

In a first aspect, an embodiment of the present application provides a capacitive switching circuit, including:

the first end of the filter capacitor unit is used for receiving a first power supply voltage, and the second end of the filter capacitor unit is used for outputting a control voltage;

the auxiliary capacitance switch circuit comprises an auxiliary capacitance unit and a switch unit, wherein a first end of the auxiliary capacitance unit is used for receiving the first power supply voltage, and the switch unit is used for connecting a second end of the auxiliary capacitance unit with a second end or a grounding end of the filter capacitance unit.

In a second aspect, embodiments of the present application provide a feedback control circuit, including:

the control signal generation circuit comprises an input end for receiving control voltage and an output end for outputting control signals;

the second end of the filter capacitor unit and the second end of the auxiliary capacitor unit are respectively connected with the input end of the control signal generating circuit.

In a third aspect, an embodiment of the present application provides a frequency locked loop circuit, including:

the voltage-controlled oscillation circuit comprises an input end for receiving control voltage and an output end for outputting a frequency-locking loop output signal;

the second end of the filter capacitor unit and the second end of the auxiliary capacitor unit are respectively connected with the input end of the voltage-controlled oscillation circuit.

In a fourth aspect, embodiments of the present application provide a chip, where the chip includes the switched capacitor circuit, the feedback control circuit, or the frequency locked loop circuit.

In a fifth aspect, an embodiment of the present application provides an electronic device, where the electronic device includes the chip described above.

The capacitive switch circuit, the feedback control circuit, the frequency locking loop circuit, the chip and the device provided by the embodiment of the application comprise a filter capacitor unit and an auxiliary capacitor switch circuit, wherein a first end of the filter capacitor unit is used for receiving a first power supply voltage, and a second end of the filter capacitor unit is used for outputting a control voltage; the auxiliary capacitance switching circuit comprises an auxiliary capacitance unit and a switching unit, wherein a first end of the auxiliary capacitance unit is used for receiving a first power supply voltage, and the switching unit is used for connecting a second end of the auxiliary capacitance unit with a second end or a grounding end of the filter capacitance unit; by the mode, at the moment of completing power-on, the charges of the filter capacitor unit and the auxiliary capacitor unit are shared, the control voltage is instantaneously pulled down from the first power supply voltage at the moment of completing power-on, the establishment speed of the target control voltage is accelerated, and the improvement of working efficiency is facilitated.

These and other aspects of the present application will be more readily apparent from the following description of the embodiments.

Drawings

Fig. 1 shows an application scenario diagram of a switched capacitor circuit provided in an embodiment of the present application.

Fig. 2 shows a schematic structural diagram of a switched capacitor circuit according to an embodiment of the present application.

Fig. 3 is a schematic diagram showing a process of establishing a control voltage when the auxiliary capacitance switching circuit is not provided in the embodiment of the present application.

Fig. 4 is a schematic diagram showing a process of establishing a control voltage in the embodiment of the present application in which the auxiliary capacitance switching circuit is provided.

Fig. 5 is a schematic diagram showing a process of establishing a control voltage in the embodiment of the present application in which the auxiliary capacitance switching circuit is provided.

Fig. 6 shows a schematic structural diagram of a switched capacitor circuit according to an embodiment of the present application.

Fig. 7 shows a schematic structural diagram of a feedback control circuit according to an embodiment of the present application.

Fig. 8 shows a schematic structural diagram of a feedback control circuit according to an embodiment of the present application.

Fig. 9 shows a schematic structural diagram of a frequency locked loop circuit according to an embodiment of the present application.

Fig. 10 shows a schematic structural diagram of a frequency locked loop circuit according to an embodiment of the present application.

Fig. 11 shows a schematic diagram of the frequency-voltage conversion circuit in the embodiment of the present application.

Fig. 12 shows a schematic diagram of the frequency-voltage conversion circuit in the embodiment of the present application.

Fig. 13 shows a schematic diagram of the frequency-voltage conversion circuit in the embodiment of the present application.

Fig. 14 shows a schematic diagram of the structure of the frequency-voltage conversion circuit in the embodiment of the present application.

Fig. 15 shows a schematic structural diagram of the frequency-voltage conversion circuit in the embodiment of the present application.

Fig. 16 shows a schematic diagram of the structure of the frequency-voltage conversion circuit in the embodiment of the present application.

Fig. 17 shows a schematic structural diagram of a chip provided in an embodiment of the present application.

Fig. 18 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In order to better understand the solution of the present application, the following description will make clear and complete descriptions of the technical solution of the embodiment of the present application with reference to the accompanying drawings in the embodiment of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the description of embodiments of the present application, words such as "example" or "such as" are used to indicate exemplary, illustrative, or descriptive matter. Any embodiment or design described herein as "example" or "such as" is not necessarily to be construed as preferred or advantageous over another embodiment or design. The use of words such as "example" or "such as" is intended to present relative concepts in a clear manner.

In addition, the term "plurality" in the embodiments of the present application means two or more, and in view of this, the term "plurality" may be understood as "at least two" in the embodiments of the present application. "at least one" may be understood as one or more, for example as one, two or more. For example, including at least one means including one, two or more, and not limiting what is included, e.g., including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A and B and C, may be included.

It should be noted that, in the embodiment of the present application, "and/or" describe the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may be represented: a exists alone, A and B exist together, and B exists alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship.

The capacitive switch circuit 100 provided in this application may be applied to a frequency-locked loop circuit 200a shown in fig. 1, where the frequency-locked loop circuit 200a includes the capacitive switch circuit 100, an error amplifying circuit 201a and a voltage-controlled oscillating circuit 202a, an output end of the error amplifying circuit 201a is connected to an input end of the voltage-controlled oscillating circuit 202a, an input end of the voltage-controlled oscillating circuit 202a of the capacitive switch circuit 100, the error amplifying circuit 201a is configured to output a control voltage according to a comparison reference voltage and a first voltage corresponding to a frequency-locked loop output signal, the voltage-controlled oscillating circuit 202a is configured to output the frequency-locked loop output signal with a corresponding frequency according to the control voltage, the frequency-locked loop output signal is a stable clock signal, and the capacitive switch circuit 100 is configured to quickly establish a preset frequency of the voltage-controlled oscillating circuit 202a after power-up.

An embodiment of the present application provides a capacitive switch circuit 100, referring to fig. 2, the capacitive switch circuit 100 includes a filter capacitor unit 34 and an auxiliary capacitor switch circuit 35.

Wherein the first end of the filter capacitor unit 34 is used for receiving the first supply voltage V _DD2 The second end of the filter capacitor unit 34 is used for outputting the control voltage V _CTRL 。

Wherein the auxiliary capacitance switching circuit 35 includes an auxiliary capacitance unit 353 and a switching unit 350, the first end of the auxiliary capacitance unit 353 is used for receiving the first power supply voltage V _DD2 The switching unit 350 is configured to connect the second terminal of the auxiliary capacitance unit 353 to the second terminal of the filter capacitance unit 34 or the ground GND.

In the present embodiment, the voltage V is controlled _CTRL Is set to K ₃ V _DD2 Wherein K is ₃ A coefficient greater than 0 and less than 1.

Referring to fig. 3, in the case where the auxiliary capacitance switching circuit 35 is not provided, the power-on is completed at the first time t ₀ The control voltage V output from the second terminal of the filter capacitor unit 34 _CTRL The initial value is V _DD2 The method comprises the steps of carrying out a first treatment on the surface of the Subsequently, the filter capacitor unit 34 starts to discharge,the control voltage V output by the second end of the filter capacitor unit 34 _CTRL Gradually decrease when the control voltage V _CTRL Down to K ₃ V _DD2 When the establishment is completed. As can be seen from fig. 3, in the case where the auxiliary capacitance switching circuit 35 is not provided, the voltage V is controlled _CTRL From V _DD2 Down to K ₃ V _DD2 The first time T1 needs to elapse.

In the present embodiment, referring to fig. 4, the switch unit 350 connects the second terminal of the auxiliary capacitor unit 353 to the ground GND during the power-up process, so that the voltage V of the second terminal of the auxiliary capacitor unit 353 during the power-up process _CAP Is 0.

At the first moment t when the power-on of the power supply is completed ₀ The switch unit 350 connects the second end of the auxiliary capacitor unit 353 with the second end of the filter capacitor unit 34, charges of the filter capacitor unit 34 and the auxiliary capacitor unit 353 are shared, and the second end of the filter capacitor unit 34 outputs the control voltage V _CTRL Is instantaneously pulled down to a first initial voltage V ₁ I.e. at the first time t ₀ Control voltage V _CTRL Down to V ₁ Wherein V is ₁ ＜V _DD2 . Subsequently, the filter capacitor unit 34 discharges, controlling the voltage V _CTRL From V ₁ Gradually decrease to K ₃ V _DD2 Control voltage V _CTRL From V ₁ Down to K ₃ V _DD2 The second time T2 is required to pass, the second time T2 is smaller than the first time T1, the establishment speed of the control voltage target value is increased, and the improvement of the working efficiency is facilitated.

As one embodiment, the ratio of the capacitance value of the filter capacitance unit 34 to the capacitance value of the auxiliary capacitance unit 353 is a ratio of a first coefficient and a second coefficient, the first coefficient and the second coefficient are respectively smaller than 1, the sum of the first coefficient and the second coefficient is 1, and the first coefficient is a ratio K of the target control voltage of the capacitance switching circuit 100 to the first power supply voltage ₃ 。

In the present embodiment, K is used as ₃ The capacitance values of the filter capacitance unit 34 and the auxiliary capacitance unit 353 are set so that the first initial voltage V ₁ Control with targetVoltage K ₃ V _DD2 Equal. Referring to FIG. 5, according to the principle of conservation of charge, V _DD2 *C _B ＝(V _DD2 -V _CTRL )(C _A +C _B ) Wherein C _A C is the capacitance value of the wave capacitance unit 34 _B As the capacitance value of the auxiliary capacitance unit 353,v at the time of _CTRL ＝K ₃ V _DD2 . That is, when->At the first time t when the power-on of the target control voltage is completed ₀ And establishing instantaneously.

In some embodiments, the first coefficient K ₃ 0.3 to 0.7. For example, when K ₃ When=0.5, C _B ＝C _A 。

As an embodiment, referring to fig. 6, the switch unit 350 includes a first transistor unit 351 and a second transistor unit 352, wherein a second end of the auxiliary capacitor unit 353 is connected to a first end of the first transistor unit 351 and a first end of the second transistor unit 352, respectively, a second end of the first transistor unit 351 is connected to a second end of the filter capacitor unit 34, and a second end of the second transistor unit 352 is connected to the ground GND.

In this embodiment, the control terminal of the first transistor unit 351 is configured to receive a first control signal, and the control terminal of the second transistor unit 352 is configured to receive a second control signal, where the second control signal is an inverse signal of the first control signal.

In some embodiments, the first control signal and the second control signal may be respectively transmitted by a main control module of the chip.

During the power-on process, namely at the first time t ₀ The first control signal ENP is an off control signal, the second control signal ENN is an on control signal, the first transistor unit 351 is turned off, and the second transistor unit 352 is turned on, for example, the first control signal ENP may be a low level signal, and the second control signal ENN may be a high level signalNumber (x).

At the first moment t of power-on completion ₀ The first control signal ENP is an on control signal, the second control signal ENN is an off control signal, the first transistor unit 351 is turned on, and the second transistor unit 352 is turned off, for example, the first control signal ENP is a high level signal, and the second control signal ENN is a low level signal.

In some embodiments, the filter capacitor unit 34 may include a fifth capacitor C5, and the fifth capacitor C5 has a capacitance value C _A 。

In some embodiments, the auxiliary capacitance unit 353 may include a sixth capacitance C6, the sixth capacitance C6 having a capacitance value C _B 。

In some embodiments, the first transistor unit 351 may include a seventh MOS transistor NM6. In some embodiments, the second transistor unit 352 may include an eighth MOS transistor NM7.

An embodiment of the present application provides a feedback control circuit 200, referring to fig. 7, the feedback control circuit 200 includes: a control signal generation circuit 201 and a capacitance switching circuit 100, wherein the control signal generation circuit 201 includes an input terminal for receiving a control voltage and an output terminal for outputting a control signal;

the second terminal of the filter capacitor unit 34 and the second terminal of the auxiliary capacitor unit 353 in the capacitor switching circuit 100 are connected to the input terminal of the control signal generating circuit 201, respectively.

In the present embodiment, the capacitive switch circuit 100 establishes the target control voltage of the control signal generating circuit 201 after power-up. The setup process is described in the embodiment of the capacitive switch circuit 100, and is not described in detail herein.

As an embodiment, referring to fig. 8, the feedback control circuit 200 further includes: a signal feedback circuit 202 and an error amplifying circuit 203, wherein the signal feedback circuit 202 is configured to output a corresponding feedback signal according to the control signal output by the control signal generating circuit 201; the error amplifying circuit 203 is configured to output a control voltage for characterizing an error between the comparison reference signal and the feedback signal according to the comparison reference signal and the feedback signal.

As an embodiment, the feedback control circuit 200 may be a phase-locked loop circuit, and in this case, the control signal generating circuit 201 is a voltage-controlled oscillation circuit.

As an embodiment, the feedback control circuit 200 may be a frequency locked loop circuit, and in this case, the control signal generating circuit 201 is a voltage controlled oscillation circuit.

As an embodiment, the feedback control circuit 200 may be an automatic gain control circuit, and the control signal generating circuit 201 is configured to output a control signal with a corresponding amplitude according to the control voltage.

An embodiment of the present application provides a frequency-locked loop circuit 300, referring to fig. 8, the frequency-locked loop circuit 300 includes a voltage-controlled oscillating circuit 32 and a capacitance switch circuit 100, wherein the capacitance switch circuit 100 includes a filter capacitance unit 34 and an auxiliary capacitance switch circuit 35.

The voltage-controlled oscillation circuit 32 includes an input 321 for receiving a control voltage and an output 322 for outputting a frequency-locked loop output signal. The voltage-controlled oscillating circuit 32 is configured to generate a corresponding frequency-locked loop output signal according to the control voltage, where the frequency of the frequency-locked loop output signal is a clock signal with stable frequency, for example, the frequency of the frequency-locked loop output signal is stabilized at a preset frequency in an operation stage of the frequency-locked loop circuit 300.

The first end of the filter capacitor unit 34 is configured to receive the first supply voltage, and the second end of the filter capacitor unit 34 is connected to the input end 321 of the voltage-controlled oscillating circuit 32.

As an embodiment, referring to fig. 9, the switching unit 350 includes a first transistor unit 351 and a second transistor unit 352, wherein a first terminal of the auxiliary capacitor unit 353 is configured to receive a first supply voltage V _DD2 Auxiliary capacitance unit 3The second end of 53 is connected to the first end of the first transistor unit 351 and the first end of the second transistor unit 352, respectively, the second end of the first transistor unit 351 is connected to the input end 321 of the voltage-controlled oscillating circuit 32, the second end of the second transistor unit 352 is connected to the ground end GND, the control end of the first transistor unit 351 is configured to receive a first control signal, and the control end of the second transistor unit 352 is configured to receive a second control signal, where the second control signal is an inverse signal of the first control signal.

After the filter capacitor unit 34 and the auxiliary capacitor switch circuit 35 are powered on, a control voltage V corresponding to a preset frequency is established _CTRL 。

The control voltage V at the preset frequency is taken into consideration in the frequency modulation range of the voltage-controlled oscillation circuit 32 _CTRL Set to K ₃ V _DD2 Wherein k is ₃ A coefficient greater than 0 and less than 1.

Referring to fig. 3, in the case where the auxiliary capacitance switching circuit 35 is not provided, the power-on is completed at the first time t ₀ Control voltage V _CTRL The initial value is V _DD2 The initial output frequency of the voltage-controlled oscillation circuit 32 is 0; as the frequency-locked loop circuit 300 starts to operate, the filter capacitor unit 34 starts to discharge, and the voltage V is controlled _CTRL Gradually decreasing, the output frequency of the voltage-controlled oscillating circuit 32 gradually increases from 0, when the control voltage V _CTRL Down to K ₃ V _DD2 When the output frequency of the voltage-controlled oscillating circuit 32 is a preset frequency. As can be seen from fig. 3, in the case where the auxiliary capacitance switching circuit 35 is not provided, the voltage V is controlled _CTRL From V _DD2 Down to K ₃ V _DD2 The first time T1 needs to elapse.

Referring to fig. 9 and 4, during power-up, at a first time t ₀ The first control signal ENP is an off control signal, the second control signal ENN is an on control signal, the first transistor unit 351 is turned off, and the second transistor unit 352 is turned on, for example, the first control signal ENP may be a low level signal, and the second control signal ENN may be a high level signal.

After the power supply is powered upFirst time t of formation ₀ Control voltage V _CTRL The initial value is V _DD2 The voltage control oscillation circuit 32 has an output frequency of 0 and a voltage V at point A during power-up _CAP Always 0.

At a first time t ₀ The frequency-locked loop circuit 300 starts to operate, the first control signal ENP is an on control signal, the second control signal ENN is an off control signal, the first transistor unit 351 is turned on, the second transistor unit 352 is turned off, for example, the first control signal ENP is a high level signal, the second control signal ENN is a low level signal, at this time, charges of the filter capacitor unit 34 and the auxiliary capacitor unit 353 are shared, and the control voltage V is _CTRL Is instantaneously pulled down to a first initial voltage V ₁ I.e. at the first time t ₀ Control voltage V _CTRL Down to V ₁ Wherein V is ₁ ＜V _DD2 The method comprises the steps of carrying out a first treatment on the surface of the The output frequency of the frequency-locked loop circuit 300 is at the first time t when power-up is completed ₀ Rising from 0 to a first frequency, wherein the first frequency is a first initial voltage V ₁ Corresponding frequencies. Subsequently, the filter capacitor unit 34 discharges, controlling the voltage V _CTRL From V ₁ Gradually decrease to K ₃ V _DD2 The output frequency of the frequency-locked loop circuit 300 gradually increases from the first frequency to a preset frequency, and the voltage V is controlled _CTRL From V ₁ Down to K ₃ V _DD2 The second time T2 is required to pass, the second time T2 is smaller than the first time T1, and the establishment speed of the frequency is preset, so that the improvement of the working efficiency is facilitated.

In this embodiment, by setting the auxiliary capacitance switching circuit, the charges of the filter capacitance unit and the auxiliary capacitance unit are shared, the control voltage is instantaneously pulled down from the first power supply voltage at the time of completion of power-up, and the output frequency of the frequency locking loop circuit is instantaneously raised from 0 at the time of completion of power-up, so that the establishment speed of the preset frequency is accelerated, and the improvement of the working efficiency is facilitated.

As an embodiment, the method can be realized by K ₃ The capacitance values of the filter capacitance unit 34 and the auxiliary capacitance unit 353 are set so that the first initial voltage V ₁ With a target control voltage K ₃ V _DD2 Equal.

Referring to fig. 9 and 5, at a first time t ₀ The first control signal ENP is an off control signal, the second control signal ENN is an on control signal, the first transistor unit 351 is turned off, and the second transistor unit 352 is turned on.

At the first moment t when the power-on of the power supply is completed ₀ Control voltage V _CTRL The initial value is V _DD2 The voltage control oscillation circuit 32 has an output frequency of 0 and a voltage V at point A during power-up _CAP Always 0.

At a first time t ₀ The frequency-locked loop circuit 300 starts to operate, the first control signal ENP is an on control signal, the second control signal ENN is an off control signal, the first transistor unit 351 is turned on, the second transistor unit 352 is turned off, at this time, charges of the filter capacitor unit 34 and the auxiliary capacitor unit 353 are shared, and the voltage V is controlled _CTRL Is instantaneously pulled down to K ₃ V _DD2 I.e. at the first time t ₀ Control voltage V _CTRL Down to K ₃ V _DD2 At the same time, the output frequency of the frequency locked loop circuit 300 instantaneously rises to a preset frequency. In this embodiment, the preset frequency is established at the moment of power-on, which is beneficial to improving the working efficiency.

According to the principle of conservation of charge, V _DD2 *C _B ＝(V _DD2 -V _CTRL )(C _A +C _B ) Wherein C _A C is the capacitance value of the wave capacitance unit 34 _B As the capacitance value of the auxiliary capacitance unit 353,v at the time of _CTRL ＝K ₃ V _DD2 . That is, whenWhen the power-on is on, the preset frequency is established. For example, when K ₃ When=0.5, C _B ＝C _A 。

In the present embodiment, by setting the capacitance values of the auxiliary capacitance switching circuit 35 and the control filter capacitance unit 34 and the auxiliary capacitance unit 353, the control voltage of the voltage-controlled oscillation circuit 32 can be instantaneously brought to a voltage corresponding to a predetermined frequency after power-up, and the frequency-locked loop circuit can rapidly output a clock signal of the predetermined frequency.

In some embodiments, the first transistor unit 351 may include a seventh MOS transistor NM6.

In some embodiments, the second transistor unit 352 may include an eighth MOS transistor NM7.

In some embodiments, the seventh MOS transistor NM6 and the eighth MOS transistor NM7 may be N-type MOS transistors, respectively, and in the seventh MOS transistor NM6 and the eighth MOS transistor NM7, the first terminal is a drain, the second terminal is a source, and the control terminal is a gate.

As an embodiment, referring to fig. 10, the frequency-locked loop circuit 300 further includes: a frequency-voltage conversion circuit 30a, an error amplification circuit 31, and a non-overlapping clock circuit 33.

The non-overlapping clock circuit 33 is configured to generate a first clock signal and a second clock signal with complementary phases according to the frequency-locked loop output signal output by the voltage-controlled oscillation circuit 32. The frequencies of the first clock signal and the second clock signal are respectively the same as the frequency of the frequency locking loop output signal.

The frequency-to-voltage conversion circuit 30a is configured to receive the first clock signal and the second clock signal with complementary phases to generate a first voltage.

The error amplifying circuit 31 is configured to output a control voltage based on the comparison reference voltage and the first voltage output from the frequency-voltage converting circuit 30 a.

The frequency-voltage conversion circuit 30a converts the frequencies of the first clock signal and the second clock signal into corresponding feedback voltages, the error amplification circuit 31 compares the comparison reference voltage with the first voltage and outputs a control voltage for characterizing an error between the comparison reference voltage and the first voltage, and the voltage-controlled oscillation circuit 32 outputs a frequency-locked loop output signal of a preset frequency, which is a stable clock signal, according to the control voltage.

In the present embodiment, when the actual frequency output by the voltage-controlled oscillation circuit 32 is higher than the preset frequency, the first voltage V _FB Increase, control voltage V _CTRL The actual frequency of the output is reduced to a preset frequency by the voltage controlled oscillation circuit 32. When the actual frequency output by the voltage-controlled oscillation circuit 32 is lower than the preset frequency, the first voltage V _FB Reducing the control voltage V _CTRL The actual frequency of the output is increased to a preset frequency by the voltage controlled oscillation circuit 32. The frequency locking loop circuit of the embodiment generates a stable clock signal through negative feedback, and compared with an open loop clock circuit, the frequency locking loop circuit has better frequency stability.

As an embodiment, the error amplifying circuit 31 includes a second operational amplifier having a first input 311 for receiving the comparison reference voltage V _REF2 The second input 312 of the second operational amplifier is for receiving the first voltage V _FB The output end 313 of the second operational amplifier is used for outputting the control voltage V _CTRL . The second operational amplifier adopts a differential amplification mode to compare the reference voltage V _REF2 With a first voltage V _FB The error between them is amplified by K2 times, V _CTRL ＝K ₂ (V _FB -V _REF2 )。

As an implementation manner, referring to fig. 10, the frequency-locked loop circuit 300 of the present embodiment further includes a frequency divider 36, configured to divide the frequency-locked loop output signal output by the voltage-controlled oscillating circuit 32, and output a divided signal; the non-overlapping clock circuit 33 is configured to generate a first clock signal and a second clock signal with complementary phases according to the frequency division signal corresponding to the frequency-locked loop output signal.

As an embodiment, referring to fig. 11, the frequency-voltage conversion circuit 30a includes a switched capacitor resistor circuit 10, a current generation circuit 20, and an output circuit 30.

The switched capacitor resistor circuit 10 includes a first switched capacitor circuit 11 and a second switched capacitor circuit 12, wherein the first switched capacitor circuit 11 receives a first clock signal and a second clock signal with complementary phases to generate a first equivalent resistance, the second switched capacitor circuit 12 receives the first clock signal and the second clock signal with complementary phases to generate a second equivalent resistance, and the current polarity of the first switched capacitor circuit 11 is opposite to the current polarity of the second switched capacitor circuit 12.

The current generating circuit 20 includes a first input terminal 211 and a second input terminal 212, the first input terminal 211 of the current generating circuit 20 is connected to the output terminal 10a of the switched capacitor resistor circuit 10, the second input terminal 212 of the current generating circuit 20 is used for inputting a first reference voltage, and the current generating circuit 20 is used for generating a first current according to the first equivalent resistor, the second equivalent resistor and the first reference voltage.

Wherein, the output circuit 30 outputs a corresponding first voltage according to the first current.

In this embodiment, the first switched capacitor circuit 11 and the second switched capacitor circuit 12 are connected in parallel, a pair of clock signals with complementary phases are respectively applied to the first switched capacitor circuit 11 and the second switched capacitor circuit 12, so that the first switched capacitor circuit 11 and the second switched capacitor circuit 12 can be respectively equivalent to a first equivalent resistor and a second equivalent resistor, the switched capacitor resistor circuit 10 is equivalent to a resistor, the current generating circuit 20 generates a first current according to the equivalent resistor of the switched capacitor resistor circuit 10 and a first reference voltage, and the output circuit 30 outputs a corresponding first voltage according to the first current, thereby realizing the frequency conversion of the first clock signal and the second clock signal into the first voltage.

In the present embodiment, the current of the first switched capacitor circuit 11 and the current of the second switched capacitor circuit 12 are opposite in polarity, the second switched capacitor circuit 12 is discharged when the first switched capacitor circuit 11 is charged, the second switched capacitor circuit 12 is charged when the first switched capacitor circuit 11 is discharged, the second switched capacitor circuit 12 is switched from discharge to charge at the moment when the first switched capacitor circuit 11 is switched from charge to discharge, and the voltage rise occurring in the first switched capacitor circuit 11 and the voltage drop occurring in the second switched capacitor circuit 12 cancel each other out; at the moment when the first switched-capacitor circuit 11 switches from discharging to charging, the second switched-capacitor circuit 12 switches from charging to discharging, the voltage drop occurring across the first switched-capacitor circuit 11 and the voltage rise occurring across the second switched-capacitor circuit 12 cancel each other out.

In this embodiment, the current of the first switched capacitor circuit and the current of the second switched capacitor circuit have opposite polarities, and the voltage ripple generated by the first switched capacitor circuit and the voltage ripple generated by the second switched capacitor circuit have opposite polarities, so that at least part of the two voltage ripples with opposite polarities are offset, which is beneficial to reducing the fluctuation of the first voltage output by the frequency-voltage conversion circuit.

As an embodiment, referring to fig. 12, the first switched capacitor circuit 11 includes a first switch unit 111, a second switch unit 112, and a first capacitor unit 113, wherein a first end of the first switch unit 111 is connected to the output end 10a of the switched capacitor resistor circuit 10, a second end of the first switch unit 111 is connected to a first end of the second switch unit 112, a second end of the second switch unit 112 is connected to ground, a first end of the first capacitor unit 113 is connected to a second end of the first switch unit 111 and a first end of the second switch unit 112, a second end of the first capacitor unit 113 is connected to a second end of the second switch unit 112, the first switch unit 111 is used for receiving a first clock signal, the second switch unit 112 is used for receiving a second clock signal, the first clock signal and the second clock signal are complementary in phase, and the first switch unit 111 and the second switch unit 112 are controlled to be turned on in turn to charge and discharge the first capacitor unit 113 to generate a resistance valueIs equal to the first equivalent resistance R of _eff-1 Wherein C ₁ Is the capacitance value of the first capacitance unit 113, F _sw Is the frequency of the first clock signal and the second clock signal.

The second switched capacitor circuit 12 includes a third switch unit 121, a fourth switch unit 122 and a second capacitor unit 123, wherein a first end of the third switch unit 121 is connected to the output end 10a of the switched capacitor resistor circuit 10 A second end of the third switch unit 121 is connected to a first end of the fourth switch unit 122, a second end of the fourth switch unit 122 is grounded, a first end of the second capacitor unit 123 is connected to a second end of the third switch unit 121 and a first end of the fourth switch unit 122, a second end of the second capacitor unit 123 is connected to a second end of the fourth switch unit 122, the third switch unit 121 is used for receiving a second clock signal, the fourth switch unit 122 is used for receiving a first clock signal, the phases of the first clock signal and the second clock signal are complementary, the third switch unit 121 and the fourth switch unit 122 are controlled to be sequentially turned on to charge and discharge the second capacitor unit 123, and a resistance value is generatedSecond equivalent resistance R of (2) _eff-2 Wherein C ₂ Is the capacitance value of the second capacitance unit 123, F _sw Is the frequency of the first clock signal and the second clock signal.

In the present embodiment, the voltage at the output terminal 10a of the switched capacitor resistor circuit 10 is V _FVC At the moment when the first capacitance unit 113 switches from discharging to charging, V is caused _FVC A drop occurs, at which time the second capacitance unit 123 switches from charging to discharging, resulting in V _FVC Rising occurs, and two voltage ripples with opposite polarities are mutually counteracted; at the moment when the first capacitance unit 113 switches from charging to discharging, V is caused _FVC A rise occurs, at which time the second capacitance unit 123 switches from discharging to charging, resulting in V _FVC A drop occurs and two voltage ripples of opposite polarity cancel each other out.

In the present embodiment, the current generating circuit 20 generates the first reference voltage V _REF First equivalent resistance R _eff-1 Second equivalent resistance R _eff-2 Generating a first current I ₁ ，I ₁ ＝K(V _REF C ₁ F _sw +V _REF C ₂ F _sw ) Wherein K is a preset amplification factor. The output circuit 30 generates a first voltage V according to the first current _FB ，V _FB ＝K(V _REF C ₁ F _sw +V _REF C ₂ F _sw ) R, wherein R is a preset resistance value in the output circuit 30. Then, in the present embodiment, the generated first voltage V _FB Following the frequency F of the first clock signal and the second clock signal _sw 。

As an embodiment, the first switch unit 111, the second switch unit 112, the third switch unit 121, and the fourth switch unit 122 are respectively transistor switch units, and the transistor switch units may be bipolar junction transistors (bipolar junction transistor, BJTs), bipolar transistors for short, BJT transistors, or triodes.

As an embodiment, the first, second, third and fourth switching units 111, 112, 121 and 122 may include one or more BJT transistors, respectively.

As an embodiment, the first switch unit 111, the second switch unit 112, the third switch unit 121, and the fourth switch unit 122 may be metal oxide semiconductor field effect transistors (metal oxide semiconductor field effect transistor, MOSFETs), abbreviated as MOS transistors or FET transistors, respectively.

As an embodiment, the first, second, third and fourth switching units 111, 112, 121 and 122 may include one or more MOS transistors, respectively.

In some embodiments, referring to fig. 13, the first switch unit 111 includes a first MOS transistor NM1, the second switch unit 112 includes a second MOS transistor NM2, a control terminal of the first MOS transistor NM1 receives the first clock signal SW, and a control terminal of the second MOS transistor NM2 receives the second clock signal SWB; the third switching unit 121 includes a third MOS transistor NM3, the fourth switching unit 122 includes a fourth MOS transistor NM4, a control terminal of the third MOS transistor NM3 receives the second clock signal SWB, and a control terminal of the fourth MOS transistor NM4 receives the first clock signal SW.

In some embodiments, among the first, second, third, and fourth MOS transistors NM1, NM2, NM3, and NM4, the control terminal may be a gate, the first terminal may be a source or a drain, and the second terminal may be a drain or a source.

In some embodiments, the first, second, third and fourth MOS transistors NM1, NM2, NM3 and NM4 may be N-type MOS transistors, respectively, with a first terminal being a drain, a second terminal being a source, and a control terminal being a gate.

As an embodiment, at least one of the first, second, third and fourth switching units 111, 112, 121 and 122 is provided with a complementary switching unit, wherein the complementary switching unit is connected in parallel with the switching unit, and the polarity of the complementary switching unit is opposite to the polarity of the switching unit. In this embodiment, by providing at least one switching cell with a complementary switching cell, clock feedthrough and channel injection effects are advantageously reduced.

In some embodiments, referring to fig. 14, a complementary switch unit may be provided for a portion of the switch units, the first switch capacitor circuit 11 further includes a first complementary switch unit 114 for receiving the second clock signal SWB, a second end of the first complementary switch unit 114 is connected to a first end of the first switch unit 111, a first end of the first complementary switch unit 114 is connected to a second end of the first switch unit 111, polarities of the first complementary switch unit 114 and the first switch unit 111 are opposite, the first complementary switch unit 114 and the first switch unit 111 are turned on or off simultaneously, and if the first switch unit 111 includes an N-type MOS transistor, the first complementary switch unit 114 includes a P-type MOS transistor; if the first switching unit 111 includes a P-type MOS transistor, the first complementary switching unit 114 includes an N-type MOS transistor. The second switched capacitor circuit 12 further comprises a third complementary switching unit 124 for receiving the first clock signal SW, wherein a second end of the third complementary switching unit 124 is connected to a first end of the third switching unit 121, a first end of the third complementary switching unit 124 is connected to a second end of the third switching unit 121, polarities of the third complementary switching unit 124 and the third switching unit 121 are opposite, and the third complementary switching unit 124 and the third switching unit 121 are simultaneously turned on or off; if the third switching unit 121 includes an N-type MOS transistor, the third complementary switching unit 124 includes a P-type MOS transistor; if the third switching unit 121 includes a P-type MOS transistor, the third complementary switching unit 124 includes an N-type MOS transistor.

In some embodiments, referring to fig. 15, complementary switch units may be provided for all switch units, and on the basis of the embodiment shown in fig. 14, the first switched capacitor circuit 11 further includes a second complementary switch unit 115 for receiving the first clock signal SW, a second end of the second complementary switch unit 115 is connected to a first end of the second switch unit 112, a first end of the second complementary switch unit 115 is connected to a second end of the second switch unit 112, polarities of the second complementary switch unit 115 and the second switch unit 112 are opposite, and the second complementary switch unit 115 and the second switch unit 112 are turned on or off simultaneously; if the second switching unit 112 includes an N-type MOS transistor, the second complementary switching unit 115 includes a P-type MOS transistor; if the second switching unit 112 includes a P-type MOS transistor, the second complementary switching unit 115 includes an N-type MOS transistor. The second switched capacitor circuit 12 further includes a fourth complementary switch unit 125 for receiving the second clock signal SWB, a second end of the fourth complementary switch unit 125 is connected to the first end of the fourth switch unit 122, a first end of the fourth complementary switch unit 125 is connected to the second end of the fourth switch unit 122, polarities of the fourth complementary switch unit 125 and the fourth switch unit 122 are opposite, and the fourth complementary switch unit 125 and the fourth switch unit 122 are turned on or off simultaneously; if the fourth switching unit 122 includes an N-type MOS transistor, the fourth complementary switching unit 125 includes a P-type MOS transistor; if the fourth switching unit 122 includes a P-type MOS transistor, the fourth complementary switching unit 125 includes an N-type MOS transistor.

In some embodiments, the first capacitance unit 113 includes a first capacitance C1, and the second capacitance unit 123 includes a second capacitance C2.

In some embodiments, the first complementary switching unit 114 may include a first complementary MOS transistor PM1, and the third complementary switching unit 124 may include a third complementary MOS transistor PM3.

In some embodiments, the second complementary switching unit 115 may include a second complementary MOS transistor PM2, and the fourth complementary switching unit 125 may include a fourth complementary MOS transistor PM4.

In some embodiments, the first complementary MOS transistor PM1 and the third complementary MOS transistor PM3 may be P-type MOS transistors, respectively, and in the first complementary MOS transistor PM1 and the third complementary MOS transistor PM3, the first terminal is a drain, the second terminal is a source, and the control terminal is a gate.

In some embodiments, the second complementary MOS transistor PM2 and the fourth complementary MOS transistor PM4 may be P-type MOS transistors, respectively, and in the second complementary MOS transistor PM2 and the fourth complementary MOS transistor PM4, the first terminal is a drain, the second terminal is a source, and the control terminal is a gate.

As an embodiment, referring to fig. 13 to 16, the switched capacitor resistor circuit 10 further includes a bypass capacitor unit 13, wherein a first end of the bypass capacitor unit 13 is connected to the first end 11a of the first switched capacitor circuit 11 and the first end 12a of the second switched capacitor circuit 12, and a second end of the bypass capacitor unit 13 is connected to the second end 11b of the first switched capacitor circuit 11 and the second end 12b of the second switched capacitor circuit 12. In the present embodiment, the bypass capacitor unit 13 is used to stabilize the voltage at the output terminal 10a of the switched capacitor resistor circuit 10 to be V _FVC 。

In some embodiments, the bypass capacitance unit 13 includes a third capacitance C3.

As an embodiment, referring to fig. 13 to 15, the current generating circuit 20 includes: a first operational amplifier 21, an output transistor unit 22 and a current mirror unit 23.

The first operational amplifier includes a first input 211, a second input 212, and an output 213; the first input terminal 211 is connected to the output terminal 10a of the switched capacitor resistor circuit 10, and the second input terminal 212 is used for inputting the first reference voltage V _REF According to the virtual short characteristic of the operational amplifier, the voltage V of the output end 10a of the switched capacitor resistor circuit 10 _FVC With a first reference voltage V _REF Equal, the current I at the output 10a of the switched capacitor resistor circuit 10 ₂ Is V (V) _REF C ₁ F _sw +V _REF C ₂ F _sw 。

The control terminal of the output transistor unit 22 is connected to the output terminal 213 of the first operational amplifier 21, and the second terminal of the output transistor unit 22 is connected to the first input terminal 211 and the output terminal 10a of the switched capacitor resistor circuit 10. The current flowing through the output transistor cell 22 is I ₂ ＝F _REF C ₁ F _sw +V _REF C ₂ F _sw 。

Wherein a first end of the current mirror unit 23 is connected to a first end of the output transistor unit 22, and a second end of the current mirror unit 23 is used for outputting a first current I ₁ . The magnification of the current mirror unit 23 is K.

In the present embodiment, the current of the output terminal 10a of the switched capacitor resistor circuit 10 is amplified by K times by the current mirror unit 23 to obtain the first current.

In some embodiments, the first input 211 of the first operational amplifier is an inverting input and the second input 212 is a non-inverting input.

In some embodiments, the output transistor unit 22 may include an output transistor NM5.

In some embodiments, the output transistor NM5 may be an N-type MOS transistor, where the first terminal of the output transistor NM5 is a drain, the second terminal is a source, and the control terminal is a gate.

In some embodiments, the current mirror unit 23 includes a fifth MOS transistor PM5 and a sixth MOS transistor PM6, where a first end of the fifth MOS transistor PM5 is an input end of the current mirror unit 23, a first end of the sixth MOS transistor PM6 is an output end of the current mirror unit 23, a second end of the fifth MOS transistor PM5 is connected to a second end of the output transistor NM5, a control end of the fifth MOS transistor PM5 is connected to a control end of the sixth MOS transistor PM6, a second end of the fifth MOS transistor PM5 is connected to a second end of the sixth MOS transistor PM6, a second end of the fifth MOS transistor PM5 is connected to a control end of the fifth MOS transistor PM5 and a control end of the sixth MOS transistor PM6, respectively, and the second end of the fifth MOS transistor PM5 and the second end of the sixth MOS transistor PM6 are commonly connected to the first power supply VDD 1.

In some embodiments, the fifth MOS transistor PM5 and the sixth MOS transistor PM6 may be P-type MOS transistors, respectively, and in the fifth MOS transistor PM5 and the sixth MOS transistor PM6, the first terminal is a drain, the second terminal is a source, and the control terminal is a gate.

As an embodiment, referring to fig. 13, the output circuit 30 includes a resistor unit 31, and the resistor unit 31 is configured to generate a first voltage according to a first current.

In some embodiments, the resistor unit 31 includes a first resistor R1, one end of the first resistor R1 is connected to the output end of the current generating circuit 20, the other end is grounded, and the connection node between the first resistor R1 and the output end of the current generating circuit 20 is a first voltage V _FB Is provided.

As an embodiment, referring to fig. 14 and 15, the output circuit further includes a filtering unit 32 for filtering the first voltage.

In some embodiments, the filtering unit 32 is connected in parallel with the resistor unit 31, one end of the filtering unit 32 is connected to the output end of the current generating circuit 20, the other end is grounded, the filtering unit 32 includes a second resistor R2 and a fourth capacitor C4 which are connected to each other, and a connection node between the second resistor R2 and the fourth capacitor C4 is a first voltage V _FB Is provided.

An embodiment of the present application provides a chip, which includes the capacitive switch circuit 100 described above. The Chip (Integrated Circuit, IC) is also referred to as a Chip, which may be, but is not limited to, a SOC (System on Chip) Chip, SIP (System in package ) Chip.

The chip of this embodiment, through the setting of auxiliary capacitance switch circuit, the charge sharing of filter capacitor unit and auxiliary capacitance unit, control voltage is pulled down from first power supply voltage in the twinkling of an eye at the last electricity completion moment, and control voltage rises from 0 in the twinkling of an eye at the last electricity completion moment, has accelerated the establishment speed of target control voltage, is favorable to work efficiency's improvement.

An embodiment of the present application provides a chip that includes the feedback control circuit 200 described above. The Chip (Integrated Circuit, IC) is also referred to as a Chip, which may be, but is not limited to, a SOC (System on Chip) Chip, a SIP (System in package) Chip.

An embodiment of the present application provides a chip 400, referring to fig. 17, the chip 400 includes the frequency-locked loop circuit 300 described above. The Chip (Integrated Circuit, IC) is also referred to as a Chip, which may be, but is not limited to, a SOC (System on Chip) Chip, a SIP (System in package) Chip.

The chip of this embodiment, through the setting of auxiliary capacitance switch circuit, the charge sharing of filter capacitor unit and auxiliary capacitance unit, control voltage is pulled down from first power supply voltage in the twinkling of an eye at last electricity completion moment, and the output frequency of lock frequency loop circuit is risen from 0 in the twinkling of an eye at last electricity completion moment, has accelerated the establishment speed of preset frequency, is favorable to work efficiency's improvement.

The embodiment of the application also provides an electronic device, which comprises a device main body and the chip arranged in the device main body, wherein the chip comprises the capacitive switch circuit 100.

According to the electronic equipment, through the arrangement of the auxiliary capacitance switch circuit, the charges of the filter capacitance unit and the auxiliary capacitance unit are shared, the control voltage is instantaneously pulled down from the first power supply voltage at the moment of power-on completion, and the control voltage is instantaneously increased from 0 at the moment of power-on completion, so that the establishment speed of the target control voltage is accelerated, and the improvement of the working efficiency is facilitated.

The embodiment of the application also provides an electronic device, which includes a device main body and the chip set in the device main body, wherein the chip includes the feedback control circuit 200.

An embodiment of the present application further provides an electronic device 500, referring to fig. 18, where the electronic device 500 includes a device body and the chip 400 described above disposed in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutritional scale, a pulse oximeter, a body composition analyzer, a display, a USB (Universal Serial Bus ) docking station, an automobile, a smart wearable device, a mobile terminal, a smart home device. The intelligent wearing equipment comprises, but is not limited to, an intelligent watch, an intelligent bracelet and a cervical vertebra massage instrument. Mobile terminals include, but are not limited to, smartphones, notebook computers, tablet computers, POS (point of sales terminal, point of sale terminal) machines. The intelligent household equipment comprises, but is not limited to, an intelligent socket, an intelligent electric cooker, an intelligent sweeper and an intelligent lamp.

According to the electronic equipment, through the arrangement of the auxiliary capacitance switch circuit, the charges of the filter capacitance unit and the auxiliary capacitance unit are shared, the control voltage is instantaneously pulled down from the first power supply voltage at the moment of power-on completion, the output frequency of the frequency locking loop circuit is instantaneously increased from 0 at the moment of power-on completion, the establishment speed of the preset frequency is accelerated, and the improvement of the working efficiency is facilitated.

The foregoing is merely exemplary of the present application and it should be noted herein that modifications may be made by those skilled in the art without departing from the inventive concept herein, which fall within the scope of the present application.

Claims

1. A capacitive switching circuit, comprising:

2. The capacitive switching circuit of claim 1, wherein the switching unit comprises a first transistor unit and a second transistor unit, the second terminal of the auxiliary capacitive unit is connected to the first terminal of the first transistor unit and the first terminal of the second transistor unit, respectively, the second terminal of the first transistor unit is connected to the second terminal of the filter capacitive unit, and the second terminal of the second transistor unit is connected to the ground terminal.

3. The capacitive switching circuit according to claim 1 or 2, wherein a ratio of a capacitance value of the filter capacitance unit to a capacitance value of the auxiliary capacitance unit is a ratio of a first coefficient to a second coefficient, the first coefficient and the second coefficient being respectively smaller than 1, a sum of the first coefficient and the second coefficient being 1, the first coefficient being a ratio of a target control voltage of the capacitive switching circuit to the first supply voltage.

4. A capacitive switching circuit according to claim 3, wherein the first coefficient is in the range 0.3 to 0.7.

5. A feedback control circuit, comprising:

The capacitance switching circuit according to any one of claims 1 to 4, wherein the second terminal of the filter capacitance unit and the second terminal of the auxiliary capacitance unit are connected to the input terminal of the control signal generating circuit, respectively.

6. The feedback control circuit of claim 5, wherein the feedback control circuit further comprises:

the signal feedback circuit is used for outputting a corresponding feedback signal according to the control signal output by the control signal generation circuit;

and the error amplifying circuit is used for outputting the control voltage for representing the error between the comparison reference signal and the feedback signal according to the comparison reference signal and the feedback signal.

7. A feedback control circuit according to claim 5 or 6, characterized in that the feedback control circuit is a phase locked loop circuit or an automatic gain control circuit.

8. A frequency locked loop circuit, comprising:

the capacitive switching circuit according to any one of claims 1 to 4, wherein the second terminal of the filter capacitor unit and the second terminal of the auxiliary capacitor unit are connected to the input terminal of the voltage-controlled oscillation circuit, respectively.

9. The frequency locked loop circuit of claim 8, wherein the frequency locked loop circuit further comprises:

a non-overlapping clock circuit for generating a first clock signal and a second clock signal with complementary phases according to the frequency locking loop output signal;

a frequency-to-voltage conversion circuit for receiving the first clock signal and the second clock signal with complementary phases to generate a first voltage;

and the error amplifying circuit is used for outputting the control voltage according to the comparison reference voltage and the first voltage.

10. The frequency locked loop circuit of claim 9, wherein the frequency locked loop circuit further comprises:

the frequency divider is used for dividing the frequency of the frequency locking ring output signal and outputting a frequency division signal;

the non-overlapping clock circuit is used for generating the first clock signal and the second clock signal with complementary phases according to the frequency division signal.

11. The frequency locked loop circuit of claim 9 wherein the frequency to voltage conversion circuit comprises:

the switch capacitor resistor circuit comprises a first switch capacitor circuit and a second switch capacitor circuit, wherein the first switch capacitor circuit receives the first clock signal and the second clock signal with complementary phases to generate a first equivalent resistor, the second switch capacitor circuit receives the first clock signal and the second clock signal to generate a second equivalent resistor, and the current polarity of the first switch capacitor circuit is opposite to the current polarity of the second switch capacitor circuit;

The current generation circuit comprises a first input end and a second input end, wherein the first input end of the current generation circuit is connected with the output end of the switched capacitor resistance circuit, the second input end of the current generation circuit is used for inputting a first reference voltage, and the current generation circuit is used for generating a first current according to the first equivalent resistor, the second equivalent resistor and the first reference voltage;

and the output circuit is used for outputting a corresponding first voltage according to the first current.

12. The frequency locked loop circuit of claim 11 wherein the switched capacitor resistor circuit further comprises a bypass capacitor unit, a first end of the bypass capacitor unit being connected to the first end of the first switched capacitor circuit and the first end of the second switched capacitor circuit, respectively, a second end of the bypass capacitor unit being connected to the second end of the first switched capacitor circuit and the second end of the second switched capacitor circuit, respectively, the first end of the first switched capacitor circuit and the first end of the second switched capacitor circuit being connected to the output of the switched capacitor resistor circuit, respectively.

13. The frequency locked loop circuit of claim 11 wherein the first switched capacitor circuit comprises a first switch unit for receiving the first clock signal, a second switch unit for receiving the second clock signal, and a first capacitor unit, a first end of the first switch unit being connected to the output of the switched capacitor resistor circuit, a second end of the first switch unit being connected to a first end of the second switch unit, the second end of the second switch unit being for ground, a first end of the first capacitor unit being connected to the second end of the first switch unit and the first end of the second switch unit, respectively, a second end of the first capacitor unit being connected to the second end of the second switch unit;

The second switch capacitor circuit comprises a third switch unit for receiving the second clock signal, a fourth switch unit for receiving the first clock signal and a second capacitor unit, wherein the first end of the third switch unit is connected with the output end of the switch capacitor resistor circuit, the second end of the third switch unit is connected with the first end of the fourth switch unit, the second end of the fourth switch unit is used for being grounded, the first end of the second capacitor unit is connected with the second end of the third switch unit and the first end of the fourth switch unit respectively, and the second end of the second capacitor unit is connected with the second end of the fourth switch unit.

14. The frequency locked loop circuit of claim 13 wherein the first switched capacitor circuit further comprises a first complementary switching cell for receiving the second clock signal, the second terminal of the first complementary switching cell being connected to the first terminal of the first switching cell, the first terminal of the first complementary switching cell being connected to the second terminal of the first switching cell, the first complementary switching cell being of opposite polarity to the first switching cell;

The second switched capacitor circuit further comprises a third complementary switching unit for receiving the first clock signal, a second end of the third complementary switching unit is connected with a first end of the third switching unit, a first end of the third complementary switching unit is connected with a second end of the third switching unit, and the polarity of the third complementary switching unit is opposite to that of the third switching unit.

15. The frequency locked loop circuit of claim 14 wherein the first switched capacitor circuit further comprises a second complementary switching unit for receiving the first clock signal, a second end of the second complementary switching unit being connected to a first end of the second switching unit, the first end of the second complementary switching unit being connected to a second end of the second switching unit, the second complementary switching unit being of opposite polarity to the second switching unit;

the second switched capacitor circuit further comprises a fourth complementary switching unit for receiving the second clock signal, wherein a second end of the fourth complementary switching unit is connected with a first end of the fourth switching unit, a first end of the fourth complementary switching unit is connected with a second end of the fourth switching unit, and the polarity of the fourth complementary switching unit is opposite to that of the fourth switching unit.

16. The frequency locked loop circuit according to any one of claims 12 to 15, wherein the current generation circuit includes:

a first operational amplifier including the first input terminal, the second input terminal, and an output terminal;

the control end of the output transistor unit is connected with the output end of the first operational amplifier, and the second end of the output transistor unit is connected with the first input end and the output end of the switched capacitor resistor circuit;

and the input end of the current mirror unit is connected with the first end of the output transistor unit, and the output end of the current mirror unit is used for outputting the first current.

17. The frequency locked loop circuit of any one of claims 12-15 wherein the output circuit comprises a resistive element for generating the first voltage from the first current.

18. The frequency locked loop circuit of claim 17 wherein the output circuit further comprises a filtering unit for filtering the first voltage.

19. A chip comprising a capacitive switching circuit according to any one of claims 1 to 4 or a feedback control circuit according to any one of claims 5 to 7 or a frequency locked loop circuit according to any one of claims 8 to 18.

20. An electronic device comprising the chip of claim 19.