CN220732925U

CN220732925U - Image sensor pixel unit, signal processing circuit and electronic device

Info

Publication number: CN220732925U
Application number: CN202321718306.1U
Authority: CN
Inventors: 郭同辉
Original assignee: Pulse Vision Beijing Technology Co ltd
Current assignee: Pulse Vision Beijing Technology Co ltd
Priority date: 2023-06-30
Filing date: 2023-06-30
Publication date: 2024-04-05
Anticipated expiration: 2033-06-30

Abstract

The embodiment of the disclosure discloses an image sensor pixel unit, a signal processing circuit and an electronic device, wherein the image sensor pixel unit comprises: a photodiode, a reset transistor, a reset control circuit, and an auxiliary circuit; the anode of the photodiode is grounded, and the cathode of the photodiode is connected with the drain electrode of the reset transistor and the auxiliary circuit; the output end of the reset control circuit is connected with the grid electrode of the reset transistor; the source electrode of the reset transistor is connected with the power supply module, the drain electrode of the reset transistor is connected with the cathode of the photodiode, and the grid electrode of the reset transistor is connected with the output end of the reset control circuit; the input end of the auxiliary circuit is connected with the cathode of the photodiode, and the output end of the auxiliary circuit is used as the output end of the pixel unit of the image sensor; the embodiment of the disclosure reduces the area of the pixel unit of the image sensor and improves the resolution of the sensor using the pixel unit of the image sensor.

Description

Image sensor pixel unit, signal processing circuit and electronic device

Technical Field

The disclosure relates to the technical field of image sensors, in particular to an image sensor pixel unit, a signal processing circuit and electronic equipment.

Background

Image sensors have been widely used in the fields of digital cameras, mobile phones, medical treatment, automobiles, unmanned aerial vehicles, machine recognition, etc., and particularly, the rapid development of the technology for manufacturing complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensors has led to higher demands on the quality of the output images of the image sensors. CMOS image sensors can be classified into two categories according to the signal acquisition mode: one way is to set the exposure time length for the pixels and then measure the voltage signal variation; the second method is a method of setting a voltage change amount for a pixel and measuring an exposure time period, and such an image sensor is called a pulse train type image sensor.

Disclosure of Invention

According to an aspect of the embodiments of the present disclosure, there is provided an image sensor pixel unit including: a photodiode, a reset control circuit, a reset transistor, and an auxiliary circuit;

the anode of the photodiode is grounded, and the cathode of the photodiode is connected with the drain electrode of the reset transistor and the auxiliary circuit;

the output end of the reset control circuit is connected with the grid electrode of the reset transistor;

The source electrode of the reset transistor is connected with the power supply module, the drain electrode of the reset transistor is connected with the cathode of the photodiode, and the grid electrode of the reset transistor is connected with the output end of the reset control circuit;

and the input end of the auxiliary circuit is connected with the cathode of the photodiode, and the output end of the auxiliary circuit is used as the output end of the pixel unit of the image sensor.

Optionally, the reset control circuit includes an inverter device;

the output end of the inverter device is connected with the grid electrode of the reset transistor, the first input end of the inverter device is connected with the power supply module, and the second input end of the inverter device is grounded.

Optionally, the inverter device includes a first transistor and a second transistor; wherein the first transistor and the second transistor are not turned on at the same time;

the source electrode of the first transistor is connected with the drain electrode of the second transistor and is used as the output end of the inverter device; the grid electrode is connected with the grid electrode of the second transistor and is used as a third input end of the inverter device; the drain electrode is grounded as a second input end of the inverter device;

the source electrode of the second transistor is used as a first input end of the inverter device and is connected with the power supply module; the drain electrode is connected with the source electrode of the first transistor and is used as the output end of the inverter device; a gate is connected to the gate of the first transistor and serves as an input to the inverter device.

Optionally, the reset control circuit further comprises an edge circuit;

the first input end of the edge circuit is used for receiving the time sequence control signal, the second input end of the edge circuit is connected with the output end of the column processor, and the output end of the edge circuit is connected with the third input end of the inverter device.

Optionally, the edge circuit includes a third transistor and a fourth transistor; wherein the third transistor and the fourth transistor are not turned on at the same time;

the source of the third transistor is connected with the drain of the fourth transistor, and the output end serving as the edge circuit is connected with the third input end of the inverter device; the grid electrode is connected with the grid electrode of the fourth transistor and used as a first input end of the edge circuit to receive the time sequence control signal; the drain electrode is used as a second input end of the edge circuit and is connected with the output end of the column processor;

the source electrode of the fourth transistor is connected with the power supply module; a gate connected with the gate of the third transistor as a first input end of the edge circuit for receiving the time sequence control signal; the drain is connected to the source of the third transistor and the output terminal as the edge circuit is connected to the third input terminal of the inverter device.

Optionally, the auxiliary circuit includes a source follower transistor and a pixel select transistor;

the grid electrode of the source following transistor is connected with the photodiode, the source electrode of the source following transistor is connected with the power supply module, and the drain electrode of the source following transistor is connected with the pixel selection transistor;

the source electrode of the pixel selection transistor is connected with the drain electrode of the source following transistor, the drain electrode is a signal output end of the pixel unit of the image sensor, and the grid electrode is connected with an external control signal.

According to another aspect of the embodiments of the present disclosure, there is provided a signal processing circuit including: a pixel array comprising m rows by n columns of the image sensor pixel unit of any one of the embodiments above, and n column processors; wherein each column processor corresponds to m image sensor pixel units in a column; m and n are integers greater than or equal to 1 respectively;

the output ends of the m image sensor pixel units included in each column of the pixel array are respectively connected with the input ends of the corresponding column processors, and the input ends of the m image sensor pixel units included in each column are respectively connected with the output ends of the corresponding column processors.

Optionally, the column processor includes: a comparator and a D flip-flop; the comparator comprises a positive output end and a negative output end;

The negative input end of the comparator is connected with the pixel unit of the image sensor; the positive input end is connected with the preset threshold signal; the positive output end is used as the output end of the column processor, and the negative output end is connected with the D end of the D trigger;

and the end D of the trigger D is connected with the negative output end of the comparator, and the end Q is connected with the pixel unit of the image sensor.

Optionally, the column processor includes a comparator, a D flip-flop, and an inverter;

the negative input end of the comparator is connected with the pixel unit of the image sensor; the positive input end is connected with the preset threshold signal; the output end is used as the output end of the column processor and is connected with the input end of the phase inverter;

the input end of the inverter is connected with the output end of the comparator, and the output end of the inverter is connected with the D end of the D trigger;

and the end D of the D trigger is connected with the output end of the phase inverter, and the end Q of the D trigger is connected with the pixel unit of the image sensor.

the positive input end of the comparator is connected with the pixel unit of the image sensor; the negative input end is connected with the preset threshold signal; the output end is connected with the D end of the D trigger;

The input end of the inverter is connected with the output end of the comparator, and the output end is used as the output end of the column processor;

and the end D of the trigger D is connected with the output end of the comparator, and the end Q is connected with the pixel unit of the image sensor.

According to still another aspect of the embodiments of the present disclosure, there is provided an electronic device including: a processor, and a memory communicatively coupled to the processor, further comprising an image sensor as in any of the embodiments above;

the memory stores computer-executable instructions;

the processor executes computer-executable instructions stored by the memory to control the image sensor.

Optionally, the electronic device is incorporated into any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.

The image sensor pixel unit, the signal processing circuit and the electronic device provided based on the above embodiments of the present disclosure include: a photodiode, a reset transistor, a reset control circuit, and an auxiliary circuit; the anode of the photodiode is grounded, and the cathode of the photodiode is connected with the drain electrode of the reset transistor and the auxiliary circuit; the output end of the reset control circuit is connected with the grid electrode of the reset transistor; the source electrode of the reset transistor is connected with the power supply module, the drain electrode of the reset transistor is connected with the cathode of the photodiode, and the grid electrode of the reset transistor is connected with the output end of the reset control circuit; the input end of the auxiliary circuit is connected with the cathode of the photodiode, and the output end of the auxiliary circuit is used as the output end of the pixel unit of the image sensor; the image sensor pixel unit provided in the embodiment has fewer components, reduces the area of the image sensor pixel unit, and improves the resolution of a sensor using the image sensor pixel unit; and the noise of the switch component for controlling the reset of the reset transistor is isolated by the reset control circuit, so that the index of the sensor applying the pixel unit of the image sensor is optimized.

The technical scheme of the present disclosure is described in further detail below through the accompanying drawings and examples.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic circuit diagram of an image sensor pixel unit according to an exemplary embodiment of the present disclosure;

fig. 2-1 is a schematic circuit diagram of an image sensor pixel unit according to another exemplary embodiment of the present disclosure;

fig. 2-2 are schematic circuit structures of an image sensor pixel unit according to still another exemplary embodiment of the present disclosure;

FIG. 3 is a simplified frame diagram of an image sensor pixel cell provided by an exemplary embodiment of the present disclosure;

fig. 4 is a schematic circuit diagram of a signal processing circuit according to an exemplary embodiment of the present disclosure;

FIG. 5-1 is a schematic diagram of a circuit configuration of a column processor in a signal processing circuit according to an exemplary embodiment of the present disclosure;

FIG. 5-2 is a simplified block diagram of a column processor in the signal processing circuit shown in FIG. 5-1;

fig. 5-3 are schematic circuit diagrams of a column processor in a signal processing circuit according to another exemplary embodiment of the present disclosure;

FIG. 6 is a timing diagram of various signals involved in the signal processing circuit disclosed in FIG. 4;

fig. 7 illustrates a block diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present disclosure and not all of the embodiments of the present disclosure, and that the present disclosure is not limited by the example embodiments described herein.

It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.

It will be appreciated by those of skill in the art that the terms "first," "second," etc. in embodiments of the present disclosure are used merely to distinguish between different steps, devices or modules, etc., and do not represent any particular technical meaning nor necessarily logical order between them.

It should also be understood that in embodiments of the present disclosure, "plurality" may refer to two or more, and "at least one" may refer to one, two or more.

It should also be appreciated that any component, data, or structure referred to in the presently disclosed embodiments may be generally understood as one or more without explicit limitation or the contrary in the context.

In addition, the term "and/or" in this disclosure is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the front and rear association objects are an or relationship. The data referred to in this disclosure may include unstructured data, such as text, images, video, and the like, as well as structured data.

It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and that the same or similar features may be referred to each other, and for brevity, will not be described in detail.

Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In an embodiment of the present application, the principle of capturing an image signal by the pulse sequence image sensor is that a photodiode of a photosensitive module in a pixel unit (corresponding to the pixel unit of the image sensor) captures a photoelectric signal by photosensitive, a quantization circuit module quantizes the photoelectric signal, and the quantization circuit module includes an evaluation function circuit according to a quantization value, and then feeds back the quantized signal to the pixel photosensitive module. If the quantized value does not meet the requirement of the preset value, the quantized circuit module feeds back a control signal to the photosensitive module, and the photodiode continues to be exposed; if the quantized value meets the preset value requirement, the quantization circuit module feeds back a control signal to the photosensitive module to reset the photodiode.

According to different pixel functions of the pulse sequence type image sensor, two architectures can be included, wherein the first architecture is that a pixel photosensitive module and a quantization circuit module are arranged in a pixel unit, the second architecture is that only the pixel photosensitive module is arranged in the pixel unit, and a circuit of the quantization circuit module function is arranged outside the pixel unit, for example, at the top or the bottom of a row of pixel units. The first architecture method has the disadvantage that the pixel area is larger, for example 17um X17 um, so that the process is limited, and the sensor resolution of the pixel unit should be generally lower, for example, lower than 100 ten thousand pixels; in the pixel unit of the second architecture mode, the quantization circuit module is arranged outside the pixel unit to reduce the area of the pixel unit and improve the resolution ratio, a feedback control signal in the quantization circuit module is connected into the pixel unit by adopting a metal wire to achieve the aim of controlling the reset or continuous exposure of the photodiode in the pixel unit, and because each pixel unit in a column of pixel units is connected into the quantization signal functional circuit by being provided with a transistor switch to realize communication, the threshold voltage of the transistor switch is changed due to the fluctuation of process manufacturing or the temperature change of a chip, so that the reset voltage level of the photodiode is changed, and noise is introduced between the pixel units or between chips. The pixel cell noise reduces the image quality, especially in dark environments.

For the advantages and disadvantages of the pixel units of the two architectures, the pixel unit of the first architecture cannot be suitable for the high-resolution sensor product, so that the high-resolution product is more prone to adopting the pixel unit of the second architecture to reduce the area of the pixel unit, for example, the pixel unit can be lower than 3um X3 um; the noise problem of the switching transistor in the pixel cell is urgently required to be solved.

Fig. 1 is a schematic circuit diagram of an image sensor pixel unit according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the pixel unit of the image sensor (hereinafter referred to as a pixel unit) provided in this embodiment includes: a photodiode 110, a reset control circuit 120, a reset transistor 130, and an auxiliary circuit 140.

The anode of the photodiode 110 is grounded, and the cathode is connected to the drain of the reset transistor 130 and the auxiliary circuit 140, for receiving an optical signal to generate photoelectric charges during the exposure period and performing a reset operation according to the on condition of the reset transistor 120.

A photodiode is a photodetector capable of converting light into a current or voltage signal depending on the manner of use. The die often uses a PN junction with photosensitive characteristics, is very sensitive to light changes, has unidirectional conductivity, and changes electrical characteristics when different light intensities are used, so that the intensity of the light can be used to change the voltage or current in the circuit.

The output end of the reset control circuit 120 is connected with the gate of the reset transistor 130, and is used for controlling the conduction condition of the reset transistor 130 according to the time sequence control signal;

in this embodiment, the reset control circuit 120 receives a feedback control signal provided by a quantization circuit module disposed outside the pixel unit, and transmits the feedback control signal to the reset transistor 130 according to the control of the timing control signal, so as to control the reset transistor 130 to be turned on or turned off; the timing of the timing control signal is generated by an external logic control circuit, and is not limited by the pixel unit provided by the embodiment of the disclosure.

The source of the reset transistor 130 is connected to the power module Vdd, the drain is connected to the cathode of the photodiode 110, and the gate is connected to the output terminal of the reset control circuit 120, for controlling the reset of the photodiode 110 according to the conduction condition.

In this embodiment, whether the photodiode 110 is reset is controlled by turning on or off the reset transistor, alternatively, the source of the reset transistor 130 is connected to the power module Vdd, the drain is connected to one end of the photodiode 110, the signal received by the gate is turned on or off, and when the reset transistor 130 is turned on, the photodiode 110 is connected to the power module Vdd, so as to realize the reset of the photodiode 110.

An input terminal of the auxiliary circuit 140 is connected to a cathode of the photodiode 110, and an output terminal is used as an output terminal of the image sensor pixel unit for outputting a target signal according to a potential change of the photodiode 110.

Alternatively, the target signal may comprise at least one of the following signals: pulse signals, potential signals, values with limits, etc.

The image sensor pixel unit provided based on the above embodiment of the present disclosure includes: a photodiode, a reset transistor, a reset control circuit, and an auxiliary circuit; the anode of the photodiode is grounded, and the cathode of the photodiode is connected with the drain electrode of the reset transistor and the auxiliary circuit; the output end of the reset control circuit is connected with the grid electrode of the reset transistor; the source electrode of the reset transistor is connected with the power supply module, the drain electrode of the reset transistor is connected with the cathode of the photodiode, and the grid electrode of the reset transistor is connected with the output end of the reset control circuit; the input end of the auxiliary circuit is connected with the cathode of the photodiode, and the output end of the auxiliary circuit is used as the output end of the pixel unit of the image sensor; the image sensor pixel unit provided in the embodiment has fewer components, reduces the area of the image sensor pixel unit, and improves the resolution of a sensor using the image sensor pixel unit; and the noise of the switch component for controlling the reset of the reset transistor is isolated by the reset control circuit, so that the index of the sensor applying the pixel unit of the image sensor is optimized.

Fig. 2-1 is a schematic circuit diagram of an image sensor pixel unit according to another exemplary embodiment of the present disclosure. As shown in fig. 2-1, the reset control circuit 120 includes an inverter device 122;

the output terminal of the inverter device 122 is connected to the gate of the reset transistor 130, the first input terminal is connected to the power module Vdd, and the second input terminal is grounded, so as to control the on state of the reset transistor 130 according to the on state of the first input terminal or the on state of the second input terminal.

In this embodiment, other circuits are isolated from the reset transistor 130 by the inverter device 122, the output end of the inverter device 122 is connected to the power module Vdd or ground, and the output end of the inverter device 122 is connected to the gate of the reset transistor 130, that is, the gate of the reset transistor 130 is connected to the power module Vdd or ground by the inverter device 122, the power module Vdd or ground is used to control the on state of the reset transistor 130, so that the influence of other circuits on the reset transistor 130 is completely isolated, noise isolation is realized, and the image quality collected by the sensor corresponding to the pixel unit is improved.

Referring to fig. 2-1, the reset control circuit 120 further includes an edge circuit 121.

A first input terminal of the edge circuit 121 is configured to receive the timing control signal, a second input terminal of the edge circuit 121 is connected to an output terminal of the column processor, and an output terminal of the edge circuit is connected to a third input terminal of the inverter device 122, so as to turn on the first input terminal or the second input terminal of the inverter device 122 according to control of the timing control signal.

In this embodiment, the edge circuit 121 transmits the signal output by the column processor to the third input terminal of the inverter device 122 according to the control of the timing control signal, and controls the first input terminal or the second input terminal of the inverter device 122 to be turned on; that is, the edge circuit 121 performs the function of a switching device, and the inverter device 122 is connected to a signal; at this time, noise is introduced into the edge circuit 121, in order to isolate the noise introduced by the edge circuit, the embodiment isolates the edge circuit 121 from the reset transistor 130 through the inverter device 122, connects the output end of the inverter device 122 with the power module Vdd or ground, and connects the output end of the inverter device 122 with the gate of the reset transistor 130, that is, realizes that the gate of the reset transistor 130 is connected with the power module Vdd or ground through the inverter device 122, controls the on condition of the reset transistor 130 with the power module Vdd or ground, completely isolates the influence of the edge circuit 121 on the reset transistor 130, realizes noise isolation, and improves the quality of the image collected by the sensor corresponding to the pixel unit.

Fig. 2-2 are schematic circuit structures of an image sensor pixel unit according to still another exemplary embodiment of the present disclosure. As shown in fig. 2-2, the inverter device 122 includes a first transistor 123 and a second transistor 124; wherein the first transistor 123 and the second transistor 124 are not turned on at the same time;

a source of the first transistor 123 is connected to a drain of the second transistor 124 and serves as an output terminal of the inverter device 122; the gate is connected to the gate of the second transistor 124 and serves as a third input of the inverter device 122; the drain is grounded as a second input of the inverter device 122;

a source of the second transistor 124 is connected to the power supply module Vdd as a first input terminal of the inverter device 122; the drain is connected to the source of the first transistor 123 and serves as the output of the inverter device 122; the gate is connected to the gate of the first transistor 123 and serves as an input to the inverter device 122.

Optionally, the first transistor 123 is an N-type transistor, the second transistor 124 is a P-type transistor, and the corresponding reset transistor 130 is an N-type transistor; it is possible to realize that the first transistor 123 and the second transistor 124 are not turned on at the same time; grounding the gate of the reset transistor 130 through the conduction of the first transistor 123, turning off the reset transistor 130, and ending the reset of the photodiode 110; connecting the gate of the reset transistor 130 with the power supply module Vdd is achieved by the conduction of the second transistor 124, so that the photodiode 110 starts to reset; the reset control of the photodiode 110 is controlled through the power supply module Vdd and the ground, and the influence of noise generated by components of an edge circuit on the reset transistor 130 is avoided.

As shown in fig. 2-2, the edge circuit 121 includes a third transistor 125 and a fourth transistor 126; wherein the third transistor 125 and the fourth transistor 126 are not turned on at the same time;

a source of the third transistor 125 is connected to a drain of the fourth transistor 126, and an output terminal of the edge circuit 121 is connected to a third input terminal of the inverter device 122; the gate connection of the gate and the fourth transistor 126 receives a timing control signal as a first input terminal of the edge circuit 121; the drain is connected as a second input of the edge circuit 121 to the output of the column processor;

the source of the fourth transistor 126 is connected to the power supply module Vdd; the gate connection of the gate and the third transistor 125 receives a timing control signal as a first input terminal of the edge circuit 121; the drain is connected to the source of the third transistor 125, and the output terminal of the edge circuit 121 is connected to the third input terminal of the inverter device 122.

Optionally, the third transistor 125 is an N-type transistor, the fourth transistor 126 is a P-type transistor, and the corresponding first transistor 123 is an N-type transistor, the second transistor 124 is a P-type transistor, and the reset transistor 130 is an N-type transistor; the gate of the third transistor 125 receives the timing control signal, and is turned on or off according to the control of the timing control signal, and when turned on, the signal output by the column processor with the connected drain is input into the inverter device 122 to control the first transistor 123 or the second transistor 124 in the inverter device to be turned on; and the gate of the fourth transistor receives the timing control signal, and is turned on or off according to the control of the timing control signal, and when turned on, the power module Vdd connected with the source is connected to the inverter device 122, so as to control the first transistor 123 or the second transistor 124 in the inverter device to be turned on, thereby realizing the conduction control of the reset transistor 130.

Optionally, as shown in fig. 2-2, the auxiliary circuit 140 includes a source follower transistor 141 and a pixel select transistor 142;

the source follower transistor 141 has a gate connected to the photodiode 110, a source connected to the power supply module Vdd, and a drain connected to the pixel selection transistor 142; for detecting and following the potential change of the photodiode 110, determining a target signal;

the source of the pixel selection transistor 142 is connected to the drain of the source follower transistor 141, the drain is a signal output terminal of the pixel unit of the image sensor, the gate is connected to an external control signal, and whether to output a target signal is determined according to the control of the external control signal.

In this embodiment, the gate terminal of the source follower transistor 141 is connected to the photodiode 110, and follows the potential change of the photodiode 110 to obtain a potential signal, and the pixel select transistor 142 selects whether to output a target signal according to the control of the external control signal v_sel, which may be an external clock signal or an external pulse signal, or the like; the pixel selection transistor 142 is controlled to output a target signal based on a timing transmission signal of an external clock circuit, and the target signal may be any one or more of a pulse signal, a potential signal, a value with a limit, and the like.

The image sensor pixel unit is a signal acquisition device in the image sensor, and the wiring mode and the device node schematic diagram of the device are shown in fig. 3. In fig. 3, each element of the pixel unit (abbreviated as a pixel unit in the drawing) of the image sensor is omitted to reserve only a part of nodes, the timing control signal r_sel is located at the top and is a horizontal direction trace, the external control signal v_sel is located below and is a horizontal direction trace, the signal RD trace transmitted by the column processor is located at the left and is a vertical direction trace, and the target signal Vpix is located at the right and is a vertical direction trace.

Fig. 4 is a schematic circuit diagram of a signal processing circuit according to an exemplary embodiment of the present disclosure. As shown in fig. 4, the signal processing circuit provided in this embodiment includes: a pixel array 410 consisting of m rows by n columns of image sensor pixel cells 411, and n columns of processors 420; wherein each column processor 420 corresponds to m image sensor pixel units 411 in a column; m and n are integers greater than or equal to 1 (in this embodiment, m is 4 and n is 4, the first row includes pixel unit 11, pixel unit 12, pixel unit 13 and pixel unit 14, the second row includes pixel unit 21, pixel unit 22, pixel unit 23 and pixel unit 24, the third row includes pixel unit 31, pixel unit 32, pixel unit 33 and pixel unit 34, the fourth row includes pixel unit 41, pixel unit 42, pixel unit 43 and pixel unit 44, and the corresponding column processor 1, column processor 2, column processor 3 and column processor 4) are only used to illustrate the structure of pixel array 410 and the connection relationship between pixel array 410 and column processor 420, and are not used to limit the number of image sensor pixel units 411 included in pixel array 410, and those skilled in the art will understand that the size of pixel array 410 can be enlarged or reduced to a corresponding size according to the needs of the image sensor, no matter how many image sensor pixel units 411 are included in pixel array 410, and each column processor 420 corresponds to one column processor 420.

The output ends of m image sensor pixel units 411 included in each column of the pixel array 410 are respectively connected with the input ends of the corresponding column processors 420, and the input ends of m image sensor pixel units 411 included in each column are respectively connected with the output ends of the corresponding column processors 420, so that each row of image sensor pixel units 411 can carry out quantization of pixel signals row by row according to the control of an external control signal v_sel, and n target signals are output and respectively sent to the n column processors 420;

the column processor 420 is configured to determine an encoded signal corresponding to the image sensor pixel unit 411 according to the received target signal, and output a trigger signal opposite to the encoded signal, and control a reset operation of the image sensor pixel unit 411 through the trigger signal.

In this embodiment, by setting the reset control circuit inside the pixel unit 411 of the image sensor (hereinafter referred to as pixel unit), the noise generated by the switching device controlled by the trigger signal output by the column processor 420 is isolated, so that the conduction of the reset transistor and the reset condition of the photodiode are not affected, and the quality of the collected image is improved; in addition, in this embodiment, the column processor 420 outputs the encoded signal, and controls the reset operation of the pixel unit by using the trigger signal based on the inverse signal of the encoded signal as the trigger signal, so that the input of external signals is reduced, and the reset efficiency of the pixel unit is improved; and the number of components in the pixel unit is reduced, the size of the pixel unit is reduced, and the resolution of an image acquired by a sensor adopting the pixel unit is improved.

In some alternative embodiments, column processor 420 includes at least: a comparator and a D flip-flop;

the comparator is used for receiving a target signal output by the pixel unit of the image sensor in the pixel group, comparing the target signal with a preset threshold value signal, determining coding data based on a comparison result, and controlling the trigger D trigger to output a trigger signal based on the comparison result;

and the D trigger is used for outputting a trigger signal according to the comparison result of the comparator.

In this embodiment, the comparator is configured to compare the target signal with the preset threshold signal Vref, and determine the encoded data (e.g., 0 or 1) based on the comparison result, which should be described as follows: the preset threshold signal Vref may be a preset threshold voltage (a specific voltage value may be set according to an actual application scenario); the method has the advantages that irregular signals (such as different voltages of target signals output each time) output by the pixel units are integrated into specific coded data through the comparator, so that the output of the pixel units is more in line with expectations; optionally, the reset of the photodiode in the pixel unit is realized based on the inverse direction of the comparison result (which is equivalent to the inverse direction of the encoded data), the reset control of the pixel unit is realized through a simple column processor structure, and the exposure efficiency of the pixel unit is improved.

Optionally, the comparator comprises a positive output and a negative output; the comparison result comprises a first comparison result and a second comparison result;

the negative input end of the comparator is connected with the pixel unit 411 of the image sensor and is connected with a target signal; the positive input end is connected with a preset threshold signal; the positive output end is used as the output end of the column processor, and the negative output end is connected with the D end of the D trigger; the encoded data is determined through a first comparison result output by the positive output end, and a second comparison result output by the negative output end is used for controlling the trigger D trigger to output a trigger signal according to the clock signal CK.

The D end of the D trigger is connected with the negative output end of the comparator, and the Q end of the D trigger is connected with the pixel unit of the image sensor.

Optionally, the comparator provided in this embodiment includes a positive input terminal and a negative input terminal, and a positive output terminal and a negative output terminal corresponding thereto, for example, when the signal voltage of the positive input terminal is greater than the signal voltage of the negative input terminal, the positive output terminal outputs high-level encoded data (for example, 1), the negative output terminal corresponding thereto outputs low-level encoded data (for example, 0), and corresponding thereto, indicates that the pixel unit is exposed to light, outputs encoded data 1, and controls the pixel unit to start to perform reset by a trigger signal (low level); when the signal voltage of the positive input terminal is smaller than that of the negative input terminal, the positive output terminal outputs low-level coded data (for example, 0), the corresponding negative output terminal outputs high-level coded data (for example, 1), corresponding to the situation, which indicates that the pixel unit is not exposed to light, the coded data 0 is output, and the pixel unit is controlled not to execute reset or stop reset through a trigger signal (high level); in addition, the present embodiment only provides a structure of a column processor, where the column processor may also compare the target signal and the preset threshold signal Vref by two common comparators (only including a forward output end), for example, one comparator has a positive input end connected to the preset threshold signal Vref, a negative input end connected to the target signal, and outputs encoded data through an output end; the positive input end of the other comparator is connected with the target signal, the negative input end of the other comparator is connected with a preset threshold signal Vref, and a trigger signal is output through the output end.

Fig. 5-1 is a schematic circuit diagram of a column processor in a signal processing circuit according to an exemplary embodiment of the present disclosure. As shown in fig. 5-1, the column processor 420 in the signal processing circuit provided in this embodiment includes: comparator 421, inverter 422, and D flip-flop 423;

the negative input end of the comparator 421 is connected with the pixel unit 411 of the image sensor, and is connected with a target signal; the positive input end is connected with a preset threshold signal; the output end is used as the output end of the column processor 420 to output the coded data, the output end is connected with the input end of the inverter 422, and the comparison result is input into the D end of the D trigger 423 through the inverter 422;

the input end of the inverter 422 is connected with the output end of the comparator 421, and the output end is connected with the D end of the D trigger 423; the comparator 421 is used for reversely processing the comparison result output by the comparator, and the obtained reverse signal is input into the D end of the D trigger 423;

the D end of the D flip-flop 423 is connected to the output end of the inverter 421, and is configured to receive the reverse signal, latch the signal of the D end to the Q end according to the control of the clock signal, and the Q end of the D flip-flop 423 is connected to the image sensor pixel unit 411; the trigger signal is output according to the clock signal CK through the Q terminal.

In the column processor provided in this embodiment, the inverter 422 is used to invert the encoded data output by the comparator 421, so that the trigger signal output by the D-flip-flop is matched with the circuit of the reset control module in the pixel unit 411, and the trigger signal inverted to the encoded data is used to reset the pixel unit when the pixel unit completes exposure; and the column processor corresponds to a plurality of pixel units in a column, so that a circuit structure is saved, the space occupied by a sensor circuit is reduced, and the efficiency and resolution of the sensor for collecting images are improved.

In addition, for convenience and clarity in describing the implementation of the present disclosure, a simplified frame diagram of the column processor circuit shown in fig. 5-1 may be shown in fig. 5-2, only a portion of the ports in the column processor circuit are shown in fig. 5-2, and the column processor described based on fig. 5-2 is more convenient to construct an image sensor together with the image sensor pixel cell shown in fig. 3.

Fig. 5-3 are schematic circuit diagrams of a column processor in a signal processing circuit according to another exemplary embodiment of the present disclosure. As shown in fig. 5-3, the column processor 420 in the signal processing circuit provided in this embodiment includes: comparator 421, inverter 422, and D flip-flop 423;

the positive input end of the comparator 421 is connected with the pixel unit 411 of the image sensor, and is connected with a target signal; the negative input end is accessed to a preset threshold signal; the output end is connected with the D end of the D trigger 423, and the comparison result is input into the D end of the D trigger 423;

the input end of the inverter 422 is connected with the output end of the comparator 421, and is used for reversely processing the comparison result output by the comparator 421, determining the encoded data based on the reverse signal obtained by the reverse processing, and the output end is used as the output end of the column processor 420;

The D end of the D trigger 423 is connected to the output end of the comparator 421, and is configured to receive the comparison result, latch the signal of the D end to the Q end according to the control of the clock signal, and the Q end of the D trigger 423 is connected to the image sensor pixel unit 411; the trigger signal is output according to the clock signal CK through the Q terminal.

The column processor 420 in the signal processing circuit provided in this embodiment includes the same components as those in the circuit provided in fig. 5-1 described above: comparator 421, inverter 422, and D flip-flop 423; in the case of the same electronic components, the difference is only that the connection modes are different, so that the structure of the column processor provided in the embodiments of the disclosure may include multiple types, and the above two embodiments are only for facilitating understanding of the schemes by those skilled in the art, and are not used to limit the specific circuit structure of the column processor in the embodiments of the disclosure. In the embodiment, a target signal is accessed through a positive input end of a comparator, a preset threshold signal Vref is accessed through a negative input end of the comparator, a trigger signal is determined through a comparison result output by an output end, and the comparison result is inverted through an inverter and then is output as encoded data; the aim of reversing the coded data and the trigger signal is also achieved, and the problem that when the pixel unit finishes exposure (outputting the coded data as 1) in the embodiment of the disclosure, the pixel unit is exposed through a low-level signal (the reverse direction corresponding to the coded data is 0) is solved.

As shown in fig. 4, the pixel array 410 is 4 rows and 4 columns, and the pixel cell positions of the rows from top to bottom are marked as a first row, a second row, a third row, and a fourth row, and the pixel cell positions of the columns from left to right are marked as a first column, a second column, a third column, and a fourth column. As shown in fig. 4, a group of column processors 420, a first column processing flag column processor 1, a second column processing flag column processor 2, a third column processing flag column processor 3, and a fourth column processing flag column processor 4 are respectively provided at the bottom (in this embodiment, provided as the bottom, or provided at the top, and the connection relationship is the same) of each column of pixel units. The timing control signal r_sel lines of the first, second, third and fourth row pixel units 410, 410 are respectively denoted as r_sel1, r_sel2, r_sel3, r_sel4, and the external control signal v_sel lines of the first, second, third and fourth row pixel units 410, 410 are respectively denoted as v_sel1, v_sel2, v_sel3, v_sel4; the target signal Vpix output by the signal output end of the first column pixel unit is connected with the negative input end of the column processor 1, the target signal Vpix output by the signal output end of the second column pixel unit is connected with the negative input end of the column processor 2, and the target signal Vpix output by the signal output end of the third column pixel is connected with the negative input end of the column processor 3; the reset control signals RD of the first row of pixel units 410, the second row of pixel units 410, the third row of pixel units 410 and the fourth row of pixel units 410 are respectively connected with the output ends of the column processors 420 of the columns; the OUT terminals of column processors 1, 2, 3, 4 are labeled OUT1, OUT2, OUT3, OUT4, respectively.

For the purpose of more clarity in describing the present disclosure, the following will further describe the timing sequence shown in FIG. 6 (the circuit configuration shown as column processor 5-1 in this embodiment). Fig. 6 shows the timing of v_selm, r_selm of the pixel array of fig. 4, where m=1, 2,3,4; also shown is the timing of the clock signal CK in the column processor 420, with the time reversal of OUT1, OUT 2, OUT 3, OUT 4 characterizing the encoded data streams output by the column processors 1,2,3, 4. Fig. 6 shows a frame data quantization operation, and the following describes the sequence in detail.

As shown in fig. 6, the operation timings of the pixels in the same row are kept in synchronization, and the timings of the pixels in all rows are alternately performed in a rolling manner, first the pixel signals in the first row are quantized, then the pixel signals in the second row are quantized, …, then the pixel signals in the fourth row are quantized, and the first row are quantized, …. The first row pixel cell timing method in the pixel array is described below.

First, the pixel selection transistor of the first row of pixel units is turned on, and a high level potential is given to the external control signal v_sel1.

Next, the CK high-level pulse signal is given, and the comparator 1, the comparator 2, the comparator 3 and the comparator 4 respectively compare the corresponding pixel output target signal Vpix with a preset reference voltage Vref, and respectively output comparison result values; the comparison result value is GND, that is, 0V when Vpix is greater than Vref, and Vdd, that is, the power supply voltage when Vpix is less than Vref. The output voltage potential of the comparator is reversely processed by the inverter and then is output to the D end of the D trigger; d flip-flop 1, D flip-flop 2, D flip-flop 3, D flip-flop 4 receive the output potential of the inverter at respective D terminals. The output voltages of the D flip-flops 1,2,3, and 4 are respectively transmitted to the RD terminals of the corresponding pixel units in the first row. Meanwhile, the OUT1/2/3/4 time sequence is reversed, and quantized data is output. Then, the pixel selection transistor of the pixel unit of the first row is turned off, and the external control signal v_sel1 is given a low level potential.

Next, the switching transistors of each pixel cell of the first row are turned on, i.e., the timing control signal r_sel1 is set from a low level to a high level, according to the output voltage value 0V or Vdd of the D flip-flop, wherein 0V is encoded to 0, vdd is encoded to 1, the corresponding pixel photodiode is reset or not (specifically, as will be understood in conjunction with the pixel cell circuit diagram shown in fig. 2-2, when the timing control signal r_sel1 is at a high level, the third transistor is turned on, the fourth transistor is turned off, the third transistor inputs the trigger signal to the input terminal of the inverter device, when the trigger signal is at a low level, the second transistor in the inverter device is turned on, the first transistor is turned off, the second transistor inputs the voltage of the power supply module to the reset transistor, the reset transistor is turned on, and the reset of the photodiode is realized, and when the trigger signal is at a high level, the second transistor in the inverter device is turned off, the first transistor inputs the voltage of the ground GND to the reset transistor, and the reset transistor is turned off.

Next, before the reset time of the pixel unit of the current row (only this is illustrated in the figure) or before the external control signal corresponding to the pixel unit of the next row starts to change to the high level after the pixel unit of the current row is reset, the reset signal RST of the comparator in the column processor circuit corresponding to each pixel unit of the first row is pulsed high, that is, the output terminal of the comparator 1/2/3 is set to GND potential, but the encoded data of the output terminal OUT terminal of the pixel unit is not affected in the phase of resetting the comparator.

Next, a high-level pulse operation is given to the clock signal CK to electrically place the trigger signal RD at a high level, and then the switching transistors of the pixel units of the first row are turned off, i.e., the timing control signal r_sel1 is set from a high level to a low level.

Next, the second row of pixel signals in the pixel array shown in fig. 4 are collected and quantized.

Next, the third row and fourth row of pixel signals in the pixel array shown in fig. 4 are collected and quantized, and one frame of pixel collection and quantization is finished.

And then the pixel signal acquisition and quantization work of the next frame are carried out.

The embodiment of the disclosure also provides an electronic device, including: the processor, and the memory communicatively connected with the processor, further including the signal processing circuit provided by any of the above embodiments;

the memory stores computer-executable instructions;

the processor executes computer-executable instructions stored by the memory to control the signal processing circuitry.

The electronic device provided by the present disclosure may be incorporated as any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.

The electronic device provided by the present disclosure may be applied to any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.

Next, an electronic device according to an embodiment of the present disclosure is described with reference to fig. 7. The electronic device may be either or both of the first device and the second device, or a stand-alone device independent thereof, which may communicate with the first device and the second device to receive the acquired input signals therefrom.

As shown in fig. 7, the electronic device includes one or more processors and memory.

The processor may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device to perform the desired functions.

The memory may store one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program products may be stored on the computer readable storage medium that can be run by a processor to implement the signal processing circuitry and/or other desired functions of the various embodiments of the present disclosure as described above.

In one example, the electronic device may further include: input devices and output devices, which are interconnected by a bus system and/or other forms of connection mechanisms (not shown).

In addition, the input device may include, for example, a keyboard, a mouse, and the like.

The output device may output various information including the determined distance information, direction information, etc., to the outside. The output device may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, etc.

Of course, only some of the components of the electronic device relevant to the present disclosure are shown in fig. 7 for simplicity, components such as buses, input/output interfaces, and the like being omitted. In addition, the electronic device may include any other suitable components depending on the particular application.

The basic principles of the present disclosure have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present disclosure. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, since the disclosure is not necessarily limited to practice with the specific details described.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, so that the same or similar parts between the embodiments are mutually referred to. For system embodiments, the description is relatively simple as it essentially corresponds to method embodiments, and reference should be made to the description of method embodiments for relevant points.

The block diagrams of the devices, apparatuses, devices, systems referred to in this disclosure are merely illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the disclosure to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims

1. An image sensor pixel cell, comprising: a photodiode, a reset control circuit, a reset transistor, and an auxiliary circuit;

2. The pixel cell of claim 1, wherein the reset control circuit comprises an inverter device;

3. The pixel cell of claim 2, wherein the inverter device comprises a first transistor and a second transistor; wherein the first transistor and the second transistor are not turned on at the same time;

4. The pixel cell of claim 2, wherein the reset control circuit further comprises an edge circuit;

the first input end of the edge circuit is used for receiving a time sequence control signal, the second input end of the edge circuit is connected with the output end of the column processor, and the output end of the edge circuit is connected with the third input end of the inverter device.

5. The pixel cell of claim 4, wherein the edge circuit comprises a third transistor and a fourth transistor; wherein the third transistor and the fourth transistor are not turned on at the same time;

6. A pixel cell according to any one of claims 1-5, wherein the auxiliary circuit comprises a source follower transistor and a pixel select transistor;

7. A signal processing circuit, comprising: a pixel array of m rows by n columns of image sensor pixel cells according to any one of claims 1-5, and n column processors; wherein each column processor corresponds to m image sensor pixel units in a column; m and n are integers greater than or equal to 1 respectively;

8. The signal processing circuit of claim 7, wherein the column processor comprises: a comparator and a D flip-flop; the comparator comprises a positive output end and a negative output end;

the negative input end of the comparator is connected with the pixel unit of the image sensor; the positive input end is connected with a preset threshold signal; the positive output end is used as the output end of the column processor, and the negative output end is connected with the D end of the D trigger;

9. The signal processing circuit of claim 8, wherein the column processor comprises a comparator, a D flip-flop, and an inverter;

10. The signal processing circuit of claim 8, wherein the column processor comprises a comparator, a D flip-flop, and an inverter;

11. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor, further comprising the signal processing circuit of any of claims 7-10;

the memory stores computer-executable instructions;

12. The electronic device of claim 11, wherein the electronic device is incorporated as any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.