CN117641141A - Image sensor pixel unit, signal processing circuit and electronic device - Google Patents
Image sensor pixel unit, signal processing circuit and electronic device Download PDFInfo
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Abstract
The embodiment of the disclosure discloses an image sensor pixel unit, a signal processing circuit and an electronic device, wherein the image sensor pixel unit comprises: a photodiode for receiving an optical signal for an exposure period to generate a photoelectric charge and performing a reset operation according to a turn-on condition of the reset transistor; a reset transistor for controlling the reset of the photodiode according to the conduction condition; an auxiliary circuit for outputting a target signal according to a potential change of the photodiode; and the reset output circuit is used for storing a reset signal obtained after the photodiode performs a reset operation and outputting the reset signal when the auxiliary circuit outputs the target signal. According to the embodiment, the target signal and the reset signal are output at the same time, so that the electronic noise caused by pixel reset operation is reduced, and the signal-to-noise ratio of the obtained image is effectively improved.
Description
Technical Field
The disclosure relates to the technical field of image sensors, in particular to an image sensor pixel unit, a signal processing circuit and electronic equipment.
Background
Image sensors have been widely used in the fields of digital cameras, mobile phones, medical treatment, automobiles, unmanned aerial vehicles, machine recognition, etc., and particularly, the rapid development of the technology for manufacturing complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensors has led to higher demands on the quality of the output images of the image sensors. CMOS image sensors can be classified into two categories according to the signal acquisition mode: one way is to set the exposure time length for the pixels and then measure the voltage signal variation; the second method is a method of setting a voltage change amount for a pixel and measuring an exposure time period, and such an image sensor is called a pulse train type image sensor. The pulse sequence type image sensor in the prior art has the defect of high noise.
Disclosure of Invention
According to an aspect of the embodiments of the present disclosure, there is provided an image sensor pixel unit including: a photodiode, a reset transistor, an auxiliary circuit, and a reset output circuit;
the photodiode is used for receiving an optical signal in the exposure time period to generate photoelectric charges and executing reset operation according to the conduction condition of the reset transistor;
The reset transistor is used for controlling the reset of the photodiode according to the conduction condition;
the auxiliary circuit is used for outputting a target signal according to the potential change of the photodiode;
the reset output circuit is used for storing a reset signal obtained after the photodiode performs a reset operation and outputting the reset signal when the auxiliary circuit outputs the target signal.
Optionally, the reset output circuit includes: the switching transistor, the signal storage module and the signal output module;
the switch transistor is used for conducting the auxiliary circuit and the signal storage module;
the signal storage module is used for responding to the conduction of the switching transistor and storing a reset signal generated by the photodiode;
the signal output module is used for outputting the reset signal stored in the signal storage module according to the control of an external control signal.
Optionally, the signal storage module includes at least one of the following components: capacitance, diode, MOS transistor capacitance.
Optionally, the auxiliary circuit includes a first source follower transistor and a first select transistor;
The grid end of the first source following transistor is connected with the photodiode, the drain end of the first source following transistor is connected with a power supply signal, and the source end of the first source following transistor is connected with the drain end of the first pixel selection transistor; for detecting and following a change in the potential of the photodiode, determining the target signal;
the drain terminal of the first selection transistor is connected with the source terminal of the first source following transistor, the source terminal is a first output terminal of the image sensor pixel unit, the gate terminal is connected with an external control signal, and whether the target signal is output is determined according to control of the external control signal.
Optionally, the source terminal of the first source follower transistor is further connected to the drain terminal of the switching transistor, and the drain terminal is connected to the signal storage module and the signal output module;
one end of the signal storage module is connected with the switching transistor and the signal output module, and the other end of the signal storage module is grounded;
one end of the signal output module is connected with the switching transistor and the signal storage module, and the other end of the signal output module is a second output end of the image sensor pixel unit and is used for outputting the reset signal.
Optionally, the signal output module includes a second source follower transistor and a second select transistor;
The gate end of the second source following transistor is connected with the switching transistor and the signal storage module, the drain end of the second source following transistor is connected with a power supply signal, and the source end of the second source following transistor is connected with the drain end of the second selection transistor;
the drain terminal of the second selection transistor is connected with the source terminal of the second source following transistor, the source terminal is a second output terminal of the image sensor pixel unit, the gate terminal is connected with an external control signal, and whether the reset signal is output is determined according to the control of the external control signal.
According to another aspect of the embodiments of the present disclosure, there is provided a signal processing circuit including: a plurality of image sensor pixel units and at least one signal reading circuit as in any one of the embodiments above; wherein each signal reading circuit corresponds to at least one image sensor pixel unit;
the image sensor pixel unit is used for quantifying pixel signals and sending the obtained target signals and reset signals to the corresponding signal reading circuits according to the control of external control signals;
the signal reading circuit is used for performing quantization operation on the target signal and the reset signal and determining an encoding signal corresponding to the pixel unit of the image sensor.
Optionally, the signal reading circuit includes: a comparator;
and the positive input end of the comparator receives the reset signal, the negative input end of the comparator receives the target signal, and the output end of the comparator outputs the encoded signal.
Optionally, the signal reading circuit further includes: the first capacitor, the second capacitor, the first switch and the second switch;
one end of the first capacitor is connected with the negative input end of the comparator, and the other end of the first capacitor receives the target signal through the first switch;
one end of the second capacitor is connected with the positive input end of the comparator, and the other end of the second capacitor receives the reset signal and is connected with the first switch through the second switch.
Optionally, the signal reading circuit further includes: a third capacitor, a third switch and a fourth switch;
one end of the third capacitor is connected with the positive input end of the comparator, and the other end of the third capacitor is connected with a reference signal;
the third switch is communicated with a common mode voltage and a negative input end of the comparator;
the fourth switch is communicated with the negative input end of the comparator and the output end of the comparator.
Optionally, the signal reading circuit performs an initialization process on the comparator by simultaneously turning on the second switch, the third switch, and the fourth switch before receiving the reset signal and the target signal.
According to still another aspect of the embodiments of the present disclosure, there is provided an electronic device including: the image sensor comprises a processor, a memory in communication connection with the processor, and further comprises the image sensor pixel unit according to any one of the embodiments or the signal processing circuit according to any one of the embodiments;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored by the memory to control the image sensor pixel unit or signal processing circuitry.
Optionally, the electronic device is incorporated as any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.
The image sensor pixel unit, the signal processing circuit and the electronic device provided based on the above embodiments of the present disclosure include: a photodiode for receiving an optical signal for an exposure period to generate a photoelectric charge and performing a reset operation according to a turn-on condition of the reset transistor; a reset transistor for controlling the reset of the photodiode according to the conduction condition; an auxiliary circuit for outputting a target signal according to a potential change of the photodiode; and the reset output circuit is used for storing a reset signal obtained after the photodiode performs a reset operation and outputting the reset signal when the auxiliary circuit outputs the target signal. By simultaneously outputting the target signal and the reset signal, the electronic noise (for example, johnson KTC noise) caused by pixel reset operation is reduced, the pixel quantization bit data stream noise caused by production process fluctuation is optimized, the image quality output by an image sensor applying the image sensor pixel unit, especially the image quality in a dark light environment is improved, and the signal to noise ratio of the obtained image is effectively improved.
The technical scheme of the present disclosure is described in further detail below through the accompanying drawings and examples.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic circuit diagram of an image sensor pixel unit according to an exemplary embodiment of the present disclosure;
fig. 2 is a schematic circuit diagram of a reset output circuit in a pixel unit of an image sensor according to an exemplary embodiment of the present disclosure;
fig. 3 is a schematic circuit diagram of an image sensor pixel unit according to another exemplary embodiment of the present disclosure;
fig. 4a is a schematic circuit diagram of an image sensor pixel unit according to another exemplary embodiment of the present disclosure;
fig. 4b is a schematic circuit diagram of an image sensor pixel unit according to still another exemplary embodiment of the present disclosure;
fig. 4c is a schematic circuit diagram of an image sensor pixel unit according to still another exemplary embodiment of the present disclosure;
fig. 5 is a schematic circuit diagram of a signal processing circuit according to an exemplary embodiment of the present disclosure;
Fig. 6 is a schematic circuit diagram of a signal reading circuit in a signal processing circuit according to an exemplary embodiment of the present disclosure;
FIG. 7 is a timing control schematic of an alternative example of a signal processing circuit provided by an exemplary embodiment of the present disclosure;
fig. 8 illustrates a block diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present disclosure and not all of the embodiments of the present disclosure, and that the present disclosure is not limited by the example embodiments described herein.
It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.
It will be appreciated by those of skill in the art that the terms "first," "second," etc. in embodiments of the present disclosure are used merely to distinguish between different steps, devices or modules, etc., and do not represent any particular technical meaning nor necessarily logical order between them.
It should also be understood that in embodiments of the present disclosure, "plurality" may refer to two or more, and "at least one" may refer to one, two or more.
It should also be appreciated that any component, data, or structure referred to in the presently disclosed embodiments may be generally understood as one or more without explicit limitation or the contrary in the context.
In addition, the term "and/or" in this disclosure is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the front and rear association objects are an or relationship. The data referred to in this disclosure may include unstructured data, such as text, images, video, and the like, as well as structured data.
It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and that the same or similar features may be referred to each other, and for brevity, will not be described in detail.
Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
In carrying out the present disclosure, the inventors have found that, in a pulse sequence image sensor of the related art, a reset operation of a photodiode by a reset transistor may introduce johnson (KTC) noise; in addition, in the image sensor production and manufacturing process, process fluctuation exists between different wafers (wafer), between wafers, or between different chips of the same wafer, even in the same chip, the reset voltage of the photodiode of different pixels after the reset operation has different conditions, so that bit (bit) stream data quantized by a comparator is influenced, and quantization noise is further introduced; in particular, in a pulse sequence image sensor operating in a dark light environment, the reference voltage is relatively close to the reset signal voltage output by the photodiode, for example, the reference voltage is only 10mV lower than the reset signal voltage of the photodiode, the fluctuation of the reset signal voltage output by pixels between different wafers or different chips of the same wafer may exceed 5mV, and thus the quantized pulse bit stream error of the pixel may exceed 50%. Therefore, the disadvantage of high noise of the pulse sequence image sensor in the prior art needs to be optimally solved.
Fig. 1 is a schematic circuit diagram of an image sensor pixel unit according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the pixel unit of the image sensor (hereinafter referred to as a pixel unit) provided in this embodiment includes: a photodiode 110, a reset transistor 120, an auxiliary circuit 130, and a reset output circuit 140;
the photodiode 110 receives an optical signal for an exposure period to generate photoelectric charges, and performs a reset operation according to the on condition of the reset transistor 120.
A photodiode is a photodetector capable of converting light into a current or voltage signal depending on the manner of use. The die often uses a PN junction with photosensitive characteristics, is very sensitive to light changes, has unidirectional conductivity, and changes electrical characteristics when different light intensities are used, so that the intensity of the light can be used to change the voltage or current in the circuit. In this embodiment, the anode of the photodiode 110 is grounded GND, and the cathode is connected to the drain terminal of the reset transistor 120 and the auxiliary circuit 130.
A reset transistor 120 for controlling the reset of the photodiode 110 according to the conduction condition.
In this embodiment, whether the photodiode 110 is reset is controlled by turning on or off the reset transistor, alternatively, the source terminal of the reset transistor 120 is connected to the power signal Vdd, the drain terminal is connected to the cathode of the photodiode 110, and the photodiode 110 is connected to the power signal Vdd when the reset transistor 120 is turned on by controlling the reset signal Vrst received by the gate terminal.
Alternatively, the reset transistor 120 is turned on or off according to the control of the reset signal Vrst, and normally the reset transistor 120 is turned on when the reset signal Vrst is at a high level, and the reset transistor 120 is turned off when the reset signal Vrst is at a low level.
An auxiliary circuit 130 for outputting a target signal vpix_sig according to a potential change of the photodiode 110.
Alternatively, the target signal may comprise at least one of the following signals: pulse signals, potential signals, limited values, etc.
The reset output circuit 140 stores a reset signal obtained after the photodiode 110 performs a reset operation, and outputs a reset signal vpix_rst when the auxiliary circuit 130 outputs a target signal.
In this embodiment, the reset signal has the same property as the target signal, and may also include at least one of the following signals: pulse signals, potential signals, and values with limits, etc.
The pixel unit provided in this embodiment has two output ends, and the target signal and the reset signal are respectively output through the two output ends, where the reset signal is stored through the reset output circuit 140, so that the reset signal and the target signal can be simultaneously output, and the coding signal corresponding to the pixel unit is commonly determined through the simultaneously output target signal and the reset signal, so that KTC noise caused by the reset operation of the photodiode is reduced.
The image sensor pixel unit provided in the above embodiment of the present disclosure includes: a photodiode for receiving an optical signal for an exposure period to generate a photoelectric charge and performing a reset operation according to a turn-on condition of the reset transistor; a reset transistor for controlling the reset of the photodiode according to the conduction condition; an auxiliary circuit for outputting a target signal according to a potential change of the photodiode; and the reset output circuit is used for storing a reset signal obtained after the photodiode performs a reset operation and outputting the reset signal when the auxiliary circuit outputs the target signal. By simultaneously outputting the target signal and the reset signal, the electronic noise (for example, johnson KTC noise) caused by pixel reset operation is reduced, the pixel quantization bit data stream noise caused by production process fluctuation is optimized, the image quality output by an image sensor applying the image sensor pixel unit, especially the image quality in a dark light environment is improved, and the signal to noise ratio of the obtained image is effectively improved.
Fig. 2 is a schematic circuit diagram of a reset output circuit in a pixel unit of an image sensor according to an exemplary embodiment of the present disclosure. As shown in fig. 2, the reset output circuit 140 provided in this embodiment includes: a switching transistor 141, a signal storage module 142, and a signal output module 143;
The switch transistor 141 is used for conducting the auxiliary circuit 130 and the signal storage module 142.
Alternatively, the switching transistor 141 may be a field effect transistor, and the gate terminal of the switching transistor 141 is connected to the switching control signal Vtx through the source terminal and the drain terminal connected to the auxiliary circuit 130 and the signal storage module 142, respectively. Alternatively, the switching transistor 141 is turned on or off according to the control of the switching control signal Vtx, and in the case that the switching control signal Vtx is at a high level, the switching transistor 141 is turned on to connect the auxiliary circuit 130 to the signal storage module 142; in the case where the switching control signal Vtx is low level, the switching transistor 141 is turned off; that is, when the switching transistor 141 is turned on, the signal storage module 142 receives a reset signal generated in the photodiode 110 through the auxiliary circuit 130, and the signal storage module stores the reset signal.
The signal storage module 142 is used for storing a reset signal generated by the photodiode 110 in response to the switching transistor 141 being turned on.
In this embodiment, the signal storage module 142 can store the reset signal in the form of electric charges, and by storing the reset signal, the reset signal of the photodiode 110 is not output immediately after being generated, so that the output time difference between the reset signal and the target signal in the prior art and the signal difference caused by the time difference are avoided, the influence of different pixels due to different changes of the reset signal of the photodiode after the reset operation on bit stream data quantized by a comparator is overcome, and the quantization noise introduced is reduced.
The signal output module 143 is configured to output the reset signal stored in the signal storage module 142 according to the control of the external control signal Vselect.
In this embodiment, the signal output module 143 is used as the second output terminal of the pixel unit, and is used to output the reset signal while the first output terminal outputs the target signal.
Fig. 3 is a schematic circuit configuration diagram of an image sensor pixel unit according to another exemplary embodiment of the present disclosure. As shown in fig. 3, wherein the auxiliary circuit 130 includes a first source follower transistor 131 and a first selection transistor 132;
the gate terminal of the first source follower transistor 131 is connected to the photodiode 110, the drain terminal is connected to the power supply signal Vdd, and the source terminal is connected to the drain terminal of the first pixel selection transistor 131; for detecting and following the potential change of the photodiode 110, a target signal is determined.
The drain terminal of the first selection transistor 132 is connected to the source terminal of the first source follower transistor 131, the source terminal is the first output terminal of the image sensor pixel unit, the gate terminal is connected to the external control signal Vselect, and it is determined whether to output the target signal according to the control of the external control signal Vselect.
Optionally, as shown in fig. 3, the source terminal of the first source follower transistor 131 is further connected to the drain terminal of the switching transistor 141, and the drain terminal is connected to the signal storage module 142 and the signal output module 143.
The signal storage module 142 has one end connected to the switching transistor 141 and the signal output module 143, and the other end grounded to GND.
As shown in fig. 3, the connection between the drain terminal of the switching transistor 141 and the signal storage module 142 and the connection between the signal storage module 143 and the signal output module 143 may be denoted as PD2, so as to indicate the connection relationship between the internal circuits of the reset output circuit 140, the signal storage module 142 conducts and stores the reset signal of the read photodiode 111 through the switching transistor 141, and when the reset signal needs to be output, the stored reset signal is transmitted to the signal output module 143 through the PD2 to realize output.
One end of the signal output module 143 is connected to the switching transistor 141 and the signal storage module 142, and the other end is a second output end of the pixel unit of the image sensor, for outputting a reset signal.
Optionally, the signal output module 143 includes a second source follower transistor 144 and a second select transistor 145.
The second source follower transistor 144 has a gate terminal connected to the switching transistor 141 and the signal storage block 142, a drain terminal connected to the power supply signal Vdd, and a source terminal connected to the drain terminal of the second selection transistor 145.
The drain terminal of the second selection transistor 145 is connected to the source terminal of the second source follower transistor 144, the source terminal is the second output terminal of the image sensor pixel unit, the gate terminal is connected to the external control signal Vselect, and it is determined whether to output the reset signal according to the control of the external control signal Vselect.
The structure of the signal output module 143 in this embodiment is similar to that of the auxiliary circuit 130, and includes a source follower transistor and a select transistor (which are respectively named as a first source follower transistor 131 and a first select transistor 132, and a second source follower transistor 144 and a second select transistor 145, which are substantially all transistors, for convenience of distinction); also, the second selection transistor 145 and the first selection transistor 132 may be connected to the same external control signal Vselect, or two different external control signals having the same timing, optionally, the gate terminals of the second selection transistor 145 and the first selection transistor 132 may be connected for simplifying the circuit structure.
Optionally, the signal storage module 142 includes, but is not limited to, at least one of the following components: capacitance, diode, MOS transistor capacitance, etc. Referring to the embodiment provided in fig. 3, when the signal storage modules are different components, a schematic circuit structure of the pixel unit of the image sensor shown in fig. 4a, 4b and 4c can be obtained.
As shown in fig. 4a, the signal storage module 142 is a capacitor device, one end of which is grounded GND, and the other end of which is connected PD2; the capacitor device may be a metal-metal capacitor (MOM), a metal-insulator-metal capacitor (MIM), or the like.
As shown in fig. 4b, the signal storage module 142 is a diode device, the cathode is connected to the PD2, and the anode is connected to the ground GND; the diode device may be a buried PIN photodiode, a PN diode, or the like.
As shown in fig. 4c, the signal storage module 142 is a MOS transistor capacitor, and has a gate terminal PD2 and a source-drain terminal GND.
Fig. 5 is a schematic circuit diagram of a signal processing circuit according to an exemplary embodiment of the present disclosure. As shown in fig. 5, the signal processing circuit provided in this embodiment includes: a plurality of image sensor pixel units 510 as provided in any one of the above and at least one signal reading circuit 520; wherein each signal reading circuit 520 corresponds to at least one image sensor pixel unit 510.
Alternatively, the plurality of image sensor pixel units 510 may be distributed in an array in the signal processing circuit, for example, a pixel array is formed by m rows by n columns of image sensor pixel units 510; the light intensity signals at the corresponding locations in the image are acquired by the image sensor pixel units 510 at the corresponding locations in the pixel array. Alternatively, each signal reading circuit 520 may correspond to one image sensor pixel unit 510, or each signal reading circuit 520 may correspond to one column of image sensor pixel units 510; for example, taking the above example as an example, when the signal processing circuit includes m rows by n columns of the image sensor pixel units 510, the corresponding signal processing circuit may include n signal reading circuits 520 (each signal reading circuit 520 corresponds to one column of the image sensor pixel units 510), or m by n signal reading circuits 520 (each signal reading circuit 520 corresponds to one image sensor pixel unit 510); in addition, it is also possible that each signal reading circuit 520 corresponds to any number of image sensor pixel units 510, and only each signal reading circuit 520 sequentially reads the corresponding image sensor pixel units 510, the encoded signals corresponding to the image sensor pixel units 510 can be sequentially output.
The image sensor pixel unit 510 is configured to quantize the pixel signal and send the obtained target signal vpix_sig and the reset signal vpix_rst to the corresponding signal reading circuit 520 according to the control of the external control signal Vselect.
The signal reading circuit 520 is configured to perform quantization operation on the target signal vpix_sig and the reset signal vpix_rst, and determine the encoded signal corresponding to the image sensor pixel unit 510.
In this embodiment, by storing the reset signal in the image sensor pixel unit 510, and when the image sensor pixel unit 510 converts the optical signal into the target signal, the target signal and the reset signal are output through the first output end and the second output end of the image sensor pixel unit 510 at the same time, the signal reading circuit 520 performs quantization processing on the target signal and the reset signal output by the image sensor pixel unit 510, so as to obtain the encoded signals corresponding to the target signal and the reset signal, and by processing the target signal and the reset signal which are output at the same time, KTC noise caused by the pixel reset operation is reduced, quality of the output encoded signal is improved, and quality of the image collected under the dim light condition by the signal processing circuit is improved.
Fig. 6 is a schematic circuit diagram of a signal reading circuit in a signal processing circuit according to an exemplary embodiment of the present disclosure. As shown in fig. 6, the signal reading circuit 520 provided in this embodiment includes: a comparator 521;
the comparator 521 receives the reset signal at a positive input terminal, receives the target signal at a negative input terminal, and outputs the encoded signal at an output terminal.
In the present embodiment, the comparator 521 is configured to perform a comparison quantization operation on the target signal vpix_sig and the reset signal vpix_rst output from the image sensor pixel unit 510; comparator 521 shows a positive input Vinp, a negative input Vinn, and an output Dout for outputting a comparison result, where the comparison result output by Dout is in two cases: a high potential (e.g., vdd) and a low potential (e.g., GND) the corresponding encoded signals may be a high potential output encoded signal of 1 and a low potential output encoded signal of 0. The reset signal and the target signal output by the pixel unit 510 of the image sensor are respectively received through two input ends of the comparator 521, the size of the target signal relative to the reset signal is determined through the processing of the comparator, the coding signal is determined based on the comparison result, and the reset signal is pre-stored before the pixel unit generates the target signal, so that the correspondence between the reset signal and the target signal is ensured, the influence of noise signals is reduced, and the signal-to-noise ratio of the image generated based on the coding signal is improved.
As shown in fig. 6, the signal reading circuit 520 further includes: a first capacitor C1, a second capacitor C2, a first switch S1 and a second switch S2;
one end of the first capacitor C1 is connected to the negative input terminal of the comparator 521, and the other end receives the target signal vpix_sig through the first switch S1.
One end of the second capacitor C2 is connected to the positive input terminal of the comparator 521, and the other end receives the reset signal vpix_rst and is connected to the first switch S1 through the second switch S2.
As shown in fig. 6, the signal reading circuit 520 further includes: a third capacitor C3, a third switch S3 and a fourth switch S4;
one end of the third capacitor C3 is connected with the positive input end of the comparator 521, and the other end of the third capacitor C is connected with the reference signal Vramp; the third switch S3 communicates the common mode voltage VCM with the negative input of the comparator 521; the fourth switch S4 connects the negative input of the comparator 521 and the output of the comparator 521.
Alternatively, the signal reading circuit 520 is turned on simultaneously by the second switch S2, the third switch S3, and the fourth switch S4 before receiving the target signal vpix_sig and the reset signal vpix_rst, and performs an initialization process for the comparator 521, by which the signal reading circuit 520 is made more accurate in outputting the encoded signal.
After initializing the comparator 521, when receiving the target signal vpix_sig and the reset signal vpix_rst, the second switch S2, the third switch S3, and the fourth switch S4 are simultaneously turned off, the first switch S1 is turned on, the target signal vpix_sig is received through the first capacitor C1, and the reset signal vpix_rst is received through the second capacitor C2. In this embodiment, the reset signal vpix_rst of the image sensor pixel unit 510 is stored in the second capacitor C2 at the positive input Vinp of the comparator 521, and is marked as the first sampling Vreset of the quantized signal; in the signal quantization operation performed by the signal reading circuit 520, the target signal vpix_sig input at the negative input terminal Vinn of the comparator 521 is marked as the second sampling Vss. Alternatively, the signal difference between the first sample and the second sample may be represented as vsig=vreset-Vss, which is the photo-electric signal collected by the image sensor pixel cell 510. According to the signal processing circuit provided by the embodiment of the application, the image sensor pixel unit 510 has a double sampling function, KTC noise caused by pixel reset operation is effectively reduced through double sampling, and signal quantization fixed noise caused by device attribute change caused by process fluctuation is eliminated, so that the quality of an image output by the image sensor, particularly the quality of the image in a dim light environment, is effectively improved, and the signal to noise ratio of the image is greatly improved.
Fig. 7 is a timing control schematic diagram of an alternative example of a signal processing circuit provided in an exemplary embodiment of the present disclosure. Fig. 7 shows timings of the reset signal Vrst, the external control signal Vselect, the switch control signal Vtx, the reference signal Vramp, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4, in this embodiment, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are transistors, and the corresponding switches can be closed by inputting a high level to the transistors. Wherein a high level in the timing sequence indicates that the transistor state is on and a low level indicates that the transistor state is off.
First, a reset operation is performed on the photodiode 110 in the image sensor pixel unit 510; marked Reset PD1 in the state diagram, starting time point t1, and finishing time point t2; the specific time sequence comprises: at time t1, the reset signal Vrst and the external control signal Vselect are set to a high potential from a low electric position, and at time t2, vrst is set to a low potential and Vselect is still kept to a high potential; during Reset PD1, vtx and S2, S3 and S4 remain low (i.e., the second switch, third switch and fourth switch are off), vramp and S1 remain high (i.e., the first switch is on to avoid C1 levitation).
Next, the switching transistor 141 is turned on to Sample the reset signal of the photodiode 110, labeled Sample reset sig in the state diagram, and the sampled signal is stored in the signal storage block 142; the starting time of the Sample reset sig is t3, and the finishing time is t4; the specific time sequence comprises: vtx is set high from the low electrical position at time t3 and low at time t4, and Vselect is set low from the high electrical position at time t 4.
Next, the photodiode 110 performs an exposure operation, generating an electro-optical signal at a cathode terminal of the photodiode 110; the state diagram is marked as Exposure, the starting time is t4, and the finishing time is t5; the specific time sequence comprises: the signals Vrst, vselect and Vtx remain low, the switches S2, S3 and S4 remain low, the signals Vramp and S1 remain high, and the switch S1 decreases from high to low at time t 5.
Next, the comparator 521 is Reset, and in the state diagram, reset CMP is marked, the starting time is t6, and the finishing time is t7; the specific time sequence comprises: turning on the switch S2, the switch S3, and the switch S4, initializing the potentials of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the positive input terminal Vinp and the negative input terminal Vinn of the comparator 521 to be the common mode voltage VCM; vselects, S2, S3, and S4 are set to high at time t6, and S2, S3, and S4 are set to low at time t 7.
Next, the reset signal stored in the signal storage block 142 is sampled to the positive input Vinp of the comparator 521; the state diagram is marked as Sample Vpix_rst, the starting time is t8, and the finishing time is t9; the specific time sequence comprises: at time t8, vramp is set to low and S1 is set to high, and the signal states do not change at time t 9.
Next, the photo signal of the photodiode 110 in the image sensor pixel unit 510 is sampled to the negative input Vinn of the comparator 521. In the state diagram, the signal is marked as Sample vpix_sig, the starting time is t10, the finishing time is t11, and the signal states in the time are the same as the time t8 to the time t 9. In this embodiment, for ease of understanding, the timings from time t10 to time t11 and from time t8 to time t9 are expressed independently, and in fact, the above-mentioned sampling of the reset signal from time t8 to time t9 and the sampling of the photoelectric signal from time t10 to time t11 may be performed simultaneously, that is, the image sensor pixel unit 510 outputs the target signal and the reset signal to the signal processing circuit simultaneously.
Next, the output operation is performed on the signal of the output terminal Dout of the comparator 521; the state of each signal in the stage is the same as the state from the time t10 to the time t11, namely the state of each signal in the process is unchanged; the signal quantization output signal Dout has two states: 0 and 1,0 indicates that the output signal is low level GND, and 1 indicates that the output signal is high level power supply signal Vdd.
The signal inversion intervals between t2 and t3, between t5 and t6, between t7 and t8, between t9 and t10, and between t11 and t12 are time intervals which are necessarily present in actual signal processing.
The embodiment of the disclosure also provides an electronic device, including: the processor, and the memory communicatively connected with the processor, further including the image sensor pixel unit or the signal processing circuit provided in any of the above embodiments;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored by the memory to control the image sensor pixel unit or signal processing circuitry.
The electronic device provided by the present disclosure may be incorporated as any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.
The electronic device provided by the present disclosure may be applied to any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.
Next, an electronic device according to an embodiment of the present disclosure is described with reference to fig. 8. The electronic device may be either or both of the first device and the second device, or a stand-alone device independent thereof, which may communicate with the first device and the second device to receive the acquired input signals therefrom.
Fig. 8 illustrates a block diagram of an electronic device according to an embodiment of the disclosure.
As shown in fig. 8, the electronic device includes one or more processors and memory.
The processor may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device to perform the desired functions.
The memory may store one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program products may be stored on the computer readable storage medium that can be run by a processor to implement the image sensor pixel units or signal processing circuits and/or other desired functions of the various embodiments of the disclosure described above.
In one example, the electronic device may further include: input devices and output devices, which are interconnected by a bus system and/or other forms of connection mechanisms (not shown).
In addition, the input device may include, for example, a keyboard, a mouse, and the like.
The output device may output various information including the determined distance information, direction information, etc., to the outside. The output device may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, etc.
Of course, only some of the components of the electronic device relevant to the present disclosure are shown in fig. 8, components such as buses, input/output interfaces, and the like are omitted for simplicity. In addition, the electronic device may include any other suitable components depending on the particular application.
In addition to the methods and apparatus described above, embodiments of the present disclosure may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the image sensor pixel units or signal processing circuits according to the various embodiments of the present disclosure described in the above section of the specification.
The computer program product may write program code for performing the operations of embodiments of the present disclosure in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.
Furthermore, embodiments of the present disclosure may also be a computer-readable storage medium, having stored thereon computer program instructions, which when executed by a processor, cause the processor to perform the image sensor pixel units or signal processing circuits according to the various embodiments of the present disclosure described in the above section of the present disclosure.
The computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The basic principles of the present disclosure have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present disclosure. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, since the disclosure is not necessarily limited to practice with the specific details described.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, so that the same or similar parts between the embodiments are mutually referred to. For system embodiments, the description is relatively simple as it essentially corresponds to method embodiments, and reference should be made to the description of method embodiments for relevant points.
The block diagrams of the devices, apparatuses, devices, systems referred to in this disclosure are merely illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.
The methods and apparatus of the present disclosure may be implemented in a number of ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above-described sequence of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the sequence specifically described above unless specifically stated otherwise. Furthermore, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.
It is also noted that in the apparatus, devices and methods of the present disclosure, components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered equivalent to the present disclosure.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the disclosure to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.
Claims (13)
1. An image sensor pixel cell, comprising: a photodiode, a reset transistor, an auxiliary circuit, and a reset output circuit;
the photodiode is used for receiving an optical signal in the exposure time period to generate photoelectric charges and executing reset operation according to the conduction condition of the reset transistor;
the reset transistor is used for controlling the reset of the photodiode according to the conduction condition;
the auxiliary circuit is used for outputting a target signal according to the potential change of the photodiode;
the reset output circuit is used for storing a reset signal obtained after the photodiode performs a reset operation and outputting the reset signal when the auxiliary circuit outputs the target signal.
2. The pixel cell of claim 1, wherein the reset output circuit comprises: the switching transistor, the signal storage module and the signal output module;
The switch transistor is used for conducting the auxiliary circuit and the signal storage module;
the signal storage module is used for responding to the conduction of the switching transistor and storing a reset signal generated by the photodiode;
the signal output module is used for outputting the reset signal stored in the signal storage module according to the control of an external control signal.
3. The pixel cell of claim 2, wherein the signal storage module comprises at least one of the following components: capacitance, diode, MOS transistor capacitance.
4. A pixel cell according to any one of claims 1-3, wherein the auxiliary circuit comprises a first source follower transistor and a first select transistor;
the grid end of the first source following transistor is connected with the photodiode, the drain end of the first source following transistor is connected with a power supply signal, and the source end of the first source following transistor is connected with the drain end of the first pixel selection transistor; for detecting and following a change in the potential of the photodiode, determining the target signal;
the drain terminal of the first selection transistor is connected with the source terminal of the first source following transistor, the source terminal is a first output terminal of the image sensor pixel unit, the gate terminal is connected with an external control signal, and whether the target signal is output is determined according to control of the external control signal.
5. The pixel cell of claim 4, wherein the source terminal of the first source follower transistor is further connected to the drain terminal of the switching transistor, the drain terminal being connected to the signal storage module and the signal output module;
one end of the signal storage module is connected with the switching transistor and the signal output module, and the other end of the signal storage module is grounded;
one end of the signal output module is connected with the switching transistor and the signal storage module, and the other end of the signal output module is a second output end of the image sensor pixel unit and is used for outputting the reset signal.
6. The pixel cell of claim 5, wherein the signal output module comprises a second source follower transistor and a second select transistor;
the gate end of the second source following transistor is connected with the switching transistor and the signal storage module, the drain end of the second source following transistor is connected with a power supply signal, and the source end of the second source following transistor is connected with the drain end of the second selection transistor;
the drain terminal of the second selection transistor is connected with the source terminal of the second source following transistor, the source terminal is a second output terminal of the image sensor pixel unit, the gate terminal is connected with an external control signal, and whether the reset signal is output is determined according to the control of the external control signal.
7. A signal processing circuit, comprising: a plurality of image sensor pixel cells according to any one of claims 1-5 and at least one signal reading circuit; wherein each signal reading circuit corresponds to at least one image sensor pixel unit;
the image sensor pixel unit is used for quantifying pixel signals and sending the obtained target signals and reset signals to the corresponding signal reading circuits according to the control of external control signals;
the signal reading circuit is used for performing quantization operation on the target signal and the reset signal and determining an encoding signal corresponding to the pixel unit of the image sensor.
8. The signal processing circuit of claim 7, wherein the signal reading circuit comprises: a comparator;
and the positive input end of the comparator receives the reset signal, the negative input end of the comparator receives the target signal, and the output end of the comparator outputs the encoded signal.
9. The signal processing circuit of claim 8, wherein the signal reading circuit further comprises: the first capacitor, the second capacitor, the first switch and the second switch;
one end of the first capacitor is connected with the negative input end of the comparator, and the other end of the first capacitor receives the target signal through the first switch;
One end of the second capacitor is connected with the positive input end of the comparator, and the other end of the second capacitor receives the reset signal and is connected with the first switch through the second switch.
10. The signal processing circuit according to claim 8 or 9, wherein the signal reading circuit further comprises: a third capacitor, a third switch and a fourth switch;
one end of the third capacitor is connected with the positive input end of the comparator, and the other end of the third capacitor is connected with a reference signal;
the third switch is communicated with a common mode voltage and a negative input end of the comparator;
the fourth switch is communicated with the negative input end of the comparator and the output end of the comparator.
11. The signal processing circuit according to claim 10, wherein the signal reading circuit performs an initialization process for the comparator by simultaneously turning on the second switch, the third switch, and the fourth switch before receiving the reset signal and the target signal.
12. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor, further comprising the image sensor pixel unit of any one of claims 1-6 or the signal processing circuit of any one of claims 7-11;
The memory stores computer-executable instructions;
the processor executes computer-executable instructions stored by the memory to control the image sensor pixel unit or signal processing circuitry.
13. The electronic device of claim 12, wherein the electronic device is incorporated as any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.
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