CN116112815A - Pixel circuit, CMOS image sensor and control method - Google Patents

Abstract

The invention provides a pixel circuit, comprising: the device comprises a reset module, a gain control module, a photosensitive control module and a reading module; the reading module comprises a high-gain reading unit and a low-gain reading unit which are both connected to the floating diffusion point, wherein the high-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a high-gain transmission mode, and the low-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a low-gain transmission mode; the high-gain reading unit comprises a first capacitor and the low-gain reading unit comprises a second capacitor, wherein the first capacitor is used for acquiring the voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor is used for acquiring the voltage difference between the image signal and the reset signal in the low-gain transmission mode. The pixel circuit provided by the invention solves the problem of low dynamic range of the conventional CMOS image sensor.

Description

Pixel circuit, CMOS image sensor and control method

technical field

The invention relates to the technical field of CMOS image sensors, in particular to a pixel circuit, a CMOS image sensor and a control method.

Background technique

Global shutter technology is an imaging technology that needs to be applied in high-speed photography. All signals are exposed at the same time to generate an image without distortion; the main realization principle is that a storage capacitor is added to each pixel circuit, and all The pixel circuit is exposed at the same time, and then the photoelectric conversion signal is stored in the storage capacitor, waiting for the subsequent circuit to read out.

In some environments with large light differences, the dynamic range is a key indicator that affects the imaging effect; it determines the light intensity distribution range from the darkest shadow part to the brightest highlight part that the CMOS image sensor can accept, that is, it determines The details, levels, and characteristics of the captured images are fully understood. Therefore, how to improve the dynamic range of the CMOS image sensor is a problem to be solved by those skilled in the art.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a pixel circuit, a CMOS image sensor and a control method for solving the problem of low dynamic range of the existing CMOS image sensor.

To achieve the above object and other related objects, the present invention provides a pixel circuit, the pixel circuit includes: a reset module, a gain control module, a photosensitive control module and a reading module, wherein,

The reset module includes a reset transistor, the gate terminal of the reset transistor is connected to a reset control signal, the first connection terminal is connected to a power supply voltage, and the second connection terminal is connected to a floating diffusion point;

The gain control module is connected between the second connection terminal of the reset transistor and the floating diffusion point, and is controlled by a gain control signal, and is used to adjust the equivalent of the floating diffusion point according to the gain control signal. charge storage capacity, enabling the pixel circuit to work in different gain transfer modes;

The photosensitive control module is connected between the floating diffusion point and the first reference voltage, and is controlled by a transmission control signal, for generating exposure charges according to the photoelectric effect, and transferring the exposure charges according to the transmission control signal output;

The reading module includes a high-gain reading unit and a low-gain reading unit, both of which are connected to the floating diffusion point, wherein the high-gain reading unit is used to read the floating diffusion point in the high-gain transmission mode and output the voltage signal; the low-gain reading unit is used to read and output the voltage signal of the floating diffusion point in the low-gain transmission mode; the high-gain reading unit includes a first capacitor, and the low-gain reading unit The acquisition unit includes a second capacitor, the first capacitor is used to obtain the voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor is used to obtain the voltage difference between the image signal and the reset signal in the low-gain transmission mode Voltage difference.

Optionally, the high-gain transmission mode includes a first high-gain transmission mode and a second high-gain transmission mode, and in the first high-gain transmission mode, the left plate of the first capacitor stores a high-gain reset voltage Signal Vrsthcg, the right plate stores the first power supply voltage signal Vdd, in the second high-gain transmission mode, the left plate of the first capacitor stores the high-gain image voltage signal Vsig hcg, and the right plate stores the high-gain output voltage signal Vsig hcg+(Vdd-Vrst hcg); and/or, the low-gain transmission mode includes a first low-gain transmission mode and a second low-gain transmission mode, and in the first low-gain transmission mode, the first low-gain transmission mode The left plate of the second capacitor stores the low-gain reset voltage signal Vrstlcg, the right plate stores the first power supply voltage signal Vdd, and in the second low-gain transmission mode, the left plate of the second capacitor stores the low-gain image voltage Signal Vsig lcg, the right plate stores and outputs a low-gain voltage signal Vsig lcg+(Vdd-Vrst lcg).

Optionally, the high-gain reading unit at least further includes: a first high-gain source-follower transistor, a first high-gain storage control transistor, a second high-gain storage control transistor, a second high-gain source-follower transistor, and a first row select transistor; the gate terminal of the first high-gain source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to the first variable voltage, and the second connection terminal is connected to the first high-gain storage control transistor The first connection terminal; the gate terminal of the first high-gain storage control transistor is connected to the first high-gain storage control signal, and the second connection terminal is connected to the left plate of the first capacitor; the right pole of the first capacitor The board is connected to the second connection terminal of the second high-gain storage control transistor and the gate terminal of the second high-gain source follower transistor; the gate terminal of the second high-gain storage control transistor is connected to the second high-gain storage control transistor signal, the first connection terminal is connected to the first power supply voltage; the first connection terminal of the second high-gain source follower transistor is connected to the second power supply voltage, and the second connection terminal is connected to the first connection of the first row selection transistor terminal; the gate terminal of the first row selection transistor is connected to a high-gain row selection signal, and the second connection terminal is used as the output terminal of the high-gain reading unit;

The low-gain reading unit at least further includes: a first low-gain source follower transistor, a first low-gain storage control transistor, a second low-gain storage control transistor, a second low-gain source follower transistor, and a second row selection transistor; The gate terminal of the first low-gain source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to the second variable voltage, and the second connection terminal is connected to the first connection terminal of the first low-gain storage control transistor ; The gate terminal of the first low-gain storage control transistor is connected to the first low-gain storage control signal, and the second connection terminal is connected to the left plate of the second capacitor; the right plate of the second capacitor is connected to the The second connection terminal of the second low-gain storage control transistor and the gate terminal of the second low-gain source follower transistor; the gate terminal of the second low-gain storage control transistor is connected to the second low-gain storage control signal, the first The connection terminal is connected to the third power supply voltage; the first connection terminal of the second low-gain source follower transistor is connected to the fourth power supply voltage, and the second connection terminal is connected to the first connection terminal of the second row selection transistor; the The gate terminal of the second row selection transistor is connected to the low-gain row selection signal, and the second connection terminal is used as the output terminal of the low-gain reading unit.

Optionally, the first high-gain source-follower transistor and the first low-gain source-follower transistor are the same source-follower transistor, and the shared gate terminal of the source-follower transistor is connected to the floating diffusion point, and the first connection The terminal is connected to a variable voltage, and the second connection terminal is respectively connected to the first connection terminal of the first high-gain storage control transistor and the first connection terminal of the first low-gain storage control transistor.

Optionally, the high-gain reading unit includes a third capacitor connected between the second connection terminal of the first high-gain storage control transistor and the second reference voltage; and/or, the The low-gain reading unit includes a fourth capacitor connected between the second connection terminal of the first low-gain storage control transistor and a third reference voltage.

Optionally, the gain control module includes: a gain control transistor and a gain adjustment capacitor, wherein the gate terminal of the gain control transistor is connected to the gain control signal, and the first connection terminal is connected to the second connection terminal of the reset transistor. terminal, and connected to the fourth reference voltage through the gain adjustment capacitor, and the second connection terminal is connected to the floating diffusion point.

Optionally, the gain adjustment capacitor is a parasitic capacitance between the connection point of the reset transistor and the gain control transistor to ground; or, the gain adjustment capacitor is a device capacitor.

Optionally, the photosensitive control module includes: a photoelectric conversion element and a transfer transistor, wherein the output end of the photoelectric conversion element is connected to the first connection end of the transfer transistor, and the other end is connected to the first reference voltage; The gate terminal of the transmission transistor is connected to the transmission control signal, and the second connection terminal is connected to the floating diffusion point.

Optionally, the high-gain reading unit and the low-gain reading unit correspond to the same or different column lines, so as to implement serial output or parallel output of signals respectively.

The present invention also provides a method for controlling a pixel circuit, including the following steps: providing any one of the above pixel circuits; realizing global exposure based on the pixel circuit, and obtaining an image signal in a high-gain transmission mode through the first capacitor The voltage difference between the image signal and the reset signal is obtained through the second capacitor to obtain the voltage difference between the image signal in the low-gain transmission mode and the reset signal, so that the pixel circuit works in a different-gain transmission mode.

Optionally, the control method includes: in the first high-gain transmission mode, the left plate of the first capacitor stores a high-gain reset voltage signal Vrst hcg, and the right plate stores a first power supply voltage signal Vdd, the The voltage difference between the left and right plates of the first capacitor is Vdd-Vrst hcg, so that in the second high-gain transmission mode, when the left plate of the first capacitor stores the high-gain image voltage signal Vsig hcg, the right pole The plate stores the high-gain output voltage signal Vsig hcg+(Vdd-Vrst hcg); in the first low-gain transmission mode, the left plate of the second capacitor stores the low-gain reset voltage signal Vrst lcg, and the right plate stores the first power supply Voltage signal Vdd, the voltage difference between the left and right plates of the second capacitor is Vdd-Vrst lcg, so that in the second low-gain transmission mode, the left plate of the second capacitor stores a low-gain image When the voltage signal is Vsig lcg, the right plate stores and outputs a low-gain voltage signal Vsig lcg+(Vdd-Vrst lcg).

Optionally, in the process of realizing global exposure based on the pixel circuit, the signal transmission method includes: sequentially performing reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, and high-gain image signal acquisition and low-gain image signal acquisition; or, the signal transmission methods include: reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition while performing image signal reset of the low-gain reading unit, high-gain image signal acquisition At the same time, reset the image signal of the low-gain reading unit and collect the low-gain image signal.

Optionally, the readout process of the pixel circuit includes a first stage and a second stage, in the first stage, the pixel circuit outputs an output voltage signal Vsig+(Vdd-Vrst), in the second stage, The pixel circuit outputs a first power supply voltage signal Vdd.

Optionally, the signal output modes of the high-gain reading unit and the low-gain reading unit include serial output or parallel output.

Optionally, after the reset signal is reset, the reset transistor is set to a first potential, and low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, and high-gain image signal acquisition are performed at the first potential and low-gain image signal acquisition; and/or, when there is a first high-gain source-following transistor and a first low-gain source-following transistor or both are shared, during the reset signal reset process and the image signal reset process, the The first high-gain source follows the same potential of the transistor, and the first low-gain source follows the same potential of the transistor.

The present invention also provides a CMOS image sensor, which includes: the pixel circuit described in any one of the above items.

Optionally, the image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module is located in the first semiconductor substrate, and the reading module is located in the second semiconductor substrate. within the substrate; or, the image sensor includes a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate stacked, the photosensitive control module is located in the first semiconductor substrate, and the reader The acquisition module is located in the second semiconductor substrate, and the image sensor further includes a logic circuit, and the logic circuit is located in the third semiconductor substrate; or, the image sensor includes a stacked first semiconductor substrate and a The second semiconductor substrate, the photosensitive control module and the reading module are located in the first semiconductor substrate, and the image sensor further includes a logic circuit, and the logic circuit is located in the second semiconductor substrate.

As mentioned above, a kind of pixel circuit, CMOS image sensor and control method of the present invention, through the design of described gain control module and described reading module, adopt double conversion gain technology to effectively improve the dynamic range of CMOS image sensor; Use larger capacitors in high-intensity light areas to increase stored charge and reduce gain to improve dynamic range, and use smaller capacitors in low-intensity light areas to increase gain and achieve high sensitivity.

Description of drawings

FIG. 1 is a schematic diagram of a parallel output pixel circuit in Embodiment 1 of the present invention.

FIG. 2 is a schematic diagram of when the pixel circuit shown in FIG. 1 shares a first source follower transistor.

FIG. 3 is a schematic diagram of a serial output pixel circuit in Embodiment 1 of the present invention.

FIG. 4 is a timing diagram of signals in the pixel circuit shown in FIG. 2 .

Component designation description

100 reset module

200 gain control module

300 photosensitive control module

400 read module

401 High Gain Readout Unit

402 Low Gain Readout Unit

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 4. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the shape, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the layout of the components may also be more complicated.

Embodiment one

As shown in FIG. 1 , FIG. 1 is a schematic diagram of a parallel output pixel circuit in Embodiment 1 of the present invention. This embodiment provides a pixel circuit, and the pixel circuit includes: a reset module 100 , a gain control module 200 , a photosensitive control module 300 and a reading module 400 .

As shown in FIG. 1 , the reset module 100 includes a reset transistor M1, the gate terminal of the reset transistor M1 is connected to the reset control signal rst, the first connection terminal is connected to the power supply voltage VDD, and the second connection terminal is connected to the floating diffusion point FD for The voltage of the floating diffusion point FD is reset according to the reset control signal rst, and the reset operation of the photoelectric conversion element (such as the photodiode PD) in the photosensitive control module 300 is completed. Optionally, the reset transistor M1 is an NMOS transistor, the first connection end of which is a drain end, and the second connection end is a source end.

As shown in FIG. 1, the gain control module 200 is connected between the second connection end of the reset transistor M1 and the floating diffusion point FD, and is controlled by the gain control signal dcg, and is used to adjust the floating diffusion point FD according to the gain control signal dcg. The equivalent charge storage capacity makes the pixel circuits work in different gain transfer modes, that is, makes the CMOS image sensor composed of pixel circuits work in different gain transfer modes.

Specifically, as shown in FIG. 1, the gain control module 200 includes: a gain control transistor M2 and a gain adjustment capacitor Cdcg, wherein the gate terminal of the gain control transistor M2 is connected to the gain control signal dcg, and the first connection terminal is connected to the terminal of the reset transistor M1. The second connection terminal is connected to the fourth reference voltage through the gain adjustment capacitor Cdcg, and the second connection terminal is connected to the floating diffusion point FD. Optionally, the gain control transistor M2 is an NMOS transistor, the first connection end of which is the drain end, and the second connection end is the source end; the gain adjustment capacitor Cdcg may be a parasitic capacitance between the connection point of the reset transistor M1 and the gain control transistor M2 to ground , can also be a device capacitance (that is, an external capacitor); optionally, the fourth reference voltage is a ground voltage.

In this embodiment, when the gain control signal dcg is at a high level, the gain control transistor M2 is turned on, and the equivalent charge storage capacity of the floating diffusion point FD is increased through the gain adjustment capacitor Cdcg, so that the final charge storage capacity is equal to that of the floating diffusion point The sum of the charge storage capacity of the FD itself and the charge storage capacity of the gain adjustment capacitor Cdcg, at this time, the CMOS image sensor composed of pixel circuits works in the low-gain transfer mode (LCG); otherwise, when the gain control signal dcg is low-voltage Normally, the gain control transistor M2 is turned off, so that the charge storage capacity of the floating diffusion FD itself is the final charge storage capacity. At this time, the CMOS image sensor composed of pixel circuits works in the high-gain transfer mode (HCG).

As shown in FIG. 1, the photosensitive control module 300 is connected between the floating diffusion point FD and the first reference voltage, and is controlled by the transmission control signal tx, for generating exposure charges according to the photoelectric effect, and exposing the exposure to light according to the transmission control signal tx. Charge transfer output.

Specifically, as shown in FIG. 1 , the photosensitive control module 300 includes: a photoelectric conversion element and a transfer transistor M3, wherein the output end of the photoelectric conversion element is connected to the first connection end of the transfer transistor M3, and the other end is connected to the first reference voltage; The gate terminal of the transistor M3 is connected to the transmission control signal tx, and the second connection terminal is connected to the floating diffusion point FD. Optionally, the photoelectric conversion element is a photodiode PD, the output end of which is the cathode of the photodiode PD, and the other end is the anode of the photodiode PD; the transfer transistor M3 is an NMOS transistor, the first connection end of which is the drain end, and the second connection end is the drain end of the photodiode PD. terminal is the source terminal; in the embodiment of the present invention, optionally, the first reference voltage is the ground voltage.

In this embodiment, the photodiode PD generates exposure charges according to the photoelectric effect in response to incident light, and the transmission transistor M3 is turned on when the transmission control signal tx is at a high level, and transfers and outputs the exposure charges generated by the photodiode PD.

As shown in Figure 1, the reading module 400 includes a high-gain reading unit 401 and a low-gain reading unit 402, both of which are connected to the floating diffusion point FD; wherein, the high-gain reading unit 401 is used to read and output the voltage signal of the floating diffusion point FD; the low gain reading unit 402 is used to read and output the voltage signal of the floating diffusion point FD in the low gain transmission mode; the high gain reading unit 401 includes a first capacitor C1, and the low gain reading unit 401 The acquisition unit 402 includes a second capacitor C2, the first capacitor C1 is used to obtain the voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor C2 is used to obtain the voltage difference between the image signal and the reset signal in the low-gain transmission mode Voltage difference.

Specifically, the high-gain transmission mode includes a first high-gain transmission mode and a second high-gain transmission mode. In the first high-gain transmission mode, the left pole plate of the first capacitor C1 stores the high-gain reset voltage signal Vrsth hcg, and the right pole The plate stores the first power supply voltage signal Vdd, and in the second high-gain transmission mode, the left plate of the first capacitor stores the high-gain image voltage signal Vsig hcg, and the right plate stores the high-gain output voltage signal Vsig hcg+(Vdd-Vrst hcg ), so as to use the first capacitor C1 to obtain the voltage difference between the image signal and the reset signal in the high-gain transmission mode; and/or, the low-gain transmission mode includes a first low-gain transmission mode and a second low-gain transmission mode. In the first low-gain transmission mode, the left plate of the second capacitor stores the low-gain reset voltage signal Vrst lcg, and the right plate stores the first power supply voltage signal Vdd. In the second low-gain transmission mode, the left plate of the second capacitor The low-gain image voltage signal Vsig lcg is stored, and the right plate stores and outputs the low-gain voltage signal Vsig lcg+(Vdd-Vrst lcg), so as to use the second capacitor C2 to obtain the voltage difference between the image signal and the reset signal in the low-gain transmission mode. Optionally, the first power supply voltage Vdd is a power supply voltage VDD of positive potential.

Specifically, as shown in FIG. 1 , the high-gain reading unit 401 at least further includes: a first high-gain source follower transistor M4, a first high-gain storage control transistor M5, a second high-gain storage control transistor M6, a second high-gain The source follower transistor M7 and the first row selection transistor M8; the gate terminal of the first high-gain source follower transistor M4 is connected to the floating diffusion point FD, the first connection terminal is connected to the first variable voltage Vrsf1, and the second connection terminal is connected to the first The first connection terminal of the high-gain storage control transistor M5; the gate terminal of the first high-gain storage control transistor M5 is connected to the first high-gain storage control signal SHCG, and the second connection terminal is connected to the left plate of the first capacitor C1; the first The right plate of the capacitor C1 is connected to the second connection terminal of the second high-gain storage control transistor M6 and the gate terminal of the second high-gain source follower transistor M7; the gate terminal of the second high-gain storage control transistor M6 is connected to the second high-gain The storage control signal rstH, the first connection terminal is connected to the first power supply voltage Vdd1; the first connection terminal of the second high-gain source follower transistor M7 is connected to the second power supply voltage Vdd2, and the second connection terminal is connected to the first row selection transistor M8 The first connection terminal; the gate terminal of the first row selection transistor M8 is connected to the high-gain row selection signal rsH, and the second connection terminal is used as the output terminal of the high-gain reading unit 401 . Optionally, the first high-gain source-follower transistor M4, the first high-gain storage control transistor M5, the second high-gain storage control transistor M6, the second high-gain source-follower transistor M7, and the first row selection transistor M8 are all NMOS transistors , the first connection end is the drain end, and the second connection end is the source end.

The low-gain reading unit 402 further includes at least: a first low-gain source follower transistor M9, a first low-gain storage control transistor M10, a second low-gain storage control transistor M11, a second low-gain source follower transistor M12 and a second row selection Transistor M13; the gate terminal of the first low-gain source follower transistor M9 is connected to the floating diffusion point FD, the first connection terminal is connected to the second variable voltage Vrsf2, and the second connection terminal is connected to the first low-gain storage control transistor M10. Connecting terminal; the gate terminal of the first low-gain storage control transistor M10 is connected to the first low-gain storage control signal SLCH, and the second connecting terminal is connected to the left plate of the second capacitor C2; the right plate of the second capacitor C2 is connected to the second The second connection terminal of the low-gain storage control transistor M11 and the gate terminal of the second low-gain source follower transistor M12; the gate terminal of the second low-gain storage control transistor M11 is connected to the second low-gain storage control signal rstL, and the first connection terminal Access the third power supply voltage Vdd3; the second low-gain source follows the first connection end of the transistor M12 to access the fourth power supply voltage Vdd4, and the second connection end is connected to the first connection end of the second row selection transistor M13; the second row selection The gate terminal of the transistor M13 is connected to the low-gain row selection signal rsL, and the second connection terminal is used as the output terminal of the low-gain reading unit 402 .

Optionally, the first high gain source follower transistor M4, the first high gain storage control transistor M5, the second high gain storage control transistor M6, the second high gain source follower transistor M7, the first row selection transistor M8, the first low The gain source follower transistor M9, the first low-gain storage control transistor M10, the second low-gain storage control transistor M11, the second low-gain source follower transistor M12, and the second row selection transistor M13 are all NMOS transistors, and the first connection end is a drain terminal, and the second connection terminal is the source terminal; optionally, the first variable voltage Vrsf1 and the second variable voltage Vrsf2 are the same variable voltage Vrsf, that is, the first high-gain storage control transistor M5 and the first low-gain The gain source follower transistor M9 is the same source follower transistor, and the drain of this source follower transistor is connected to the variable voltage Vrsf; optionally, the first variable voltage Vrsf1 and the second variable voltage Vrsf2 are different variable voltages, also That is to say, the first high-gain storage control transistor M5 and the first low-gain source-follower transistor M9 are different source-follower transistors, and the drains of the two are respectively connected to the first variable voltage Vrsf1 and the second variable voltage Vrsf2; The power supply voltage Vdd1 , the second power supply voltage Vdd2 , the third power supply voltage Vdd3 and the fourth power supply voltage Vdd4 are all positive power supply voltages VDD.

In this embodiment, for the high-gain reading unit 401: in the first high-gain transmission mode, the variable voltage Vrsf is at a high level, the first high-gain source follower transistor M4, the first high-gain storage control transistor M5 and the first high-gain storage control transistor M5 The second high-gain storage control transistor M6 is turned on, so that the left plate of the first capacitor C1 stores the high-gain reset voltage signal Vrst hcg, and the right plate stores the power supply voltage signal VDD; in the second high-gain transmission mode, the variable voltage Vrsf is high level, the first high-gain source follower transistor M4 and the first high-gain storage control transistor M5 are turned on, and the second high-gain storage control transistor M6 is turned off, so that the left plate of the first capacitor C1 stores the high-gain image voltage Signal Vsigh hcg, in order to maintain the voltage difference between the left and right plates of the first capacitor C1, the right plate of the first capacitor C1 stores a high-gain output voltage signal Vsigh cg+(VDD−Vrst hcg). For the low-gain reading unit 402: in the first low-gain transmission mode, the variable voltage Vrsf is high level, the first low-gain source follows the transistor M9, the first low-gain storage control transistor M10 and the second low-gain storage control The transistor M11 is turned on, so that the left plate of the second capacitor C2 stores the low-gain reset voltage signal Vrst lcg, and the right plate stores the power supply voltage signal VDD; in the second low-gain transmission mode, the variable voltage Vrsf is at a high level, The first low-gain source follower transistor M9 and the first low-gain storage control transistor M10 are turned on, and the second low-gain storage control transistor M11 is turned off, so that the left plate of the second capacitor C2 stores the low-gain image voltage signal Vsig lcg, which is Maintaining the voltage difference between the left and right plates of the second capacitor C2, the right plate of the second capacitor C2 stores and outputs a low-gain voltage signal Vsig lcg+(VDD−Vrst lcg).

Further, as shown in FIG. 1, the high-gain reading unit 401 includes a third capacitor C3, and the third capacitor C3 is connected between the second connection terminal of the first high-gain storage control transistor M5 and the second reference voltage for Absorb the charge at the moment when the first high-gain storage control transistor M5 is turned off; and/or, the low-gain reading unit 402 includes a fourth capacitor C4, and the fourth capacitor C4 is connected to the second connection end of the first low-gain storage control transistor M10 and the third reference voltage for absorbing the charge at the moment when the first low-gain storage control transistor M10 is turned off. It should be noted that, in the reading module 400 of this embodiment, only one of the third capacitor C3 and the fourth capacitor C4 may be included, or both the third capacitor C3 and the fourth capacitor C4 may be included. Optionally, the reading module 400 includes both a third capacitor C3 and a fourth capacitor C4, and both the second reference voltage and the third reference voltage are ground voltages.

In order to simplify the circuit, as shown in FIG. 2 , FIG. 2 is a schematic diagram when the pixel circuit shown in FIG. 1 shares the first source follower transistor. The first high-gain source-follower transistor M4 and the first low-gain source-follower transistor M9 are the same source-follower transistor, and the gate terminal of the shared source-follower transistor is connected to the floating diffusion point FD, and the first connection terminal is connected to the variable voltage Vrsf. The two connection terminals are connected to the first connection terminal of the first high-gain storage control transistor M5 and the first connection terminal of the first low-gain storage control transistor M10 respectively. Specifically, the high-gain reading unit 401 and the low-gain reading unit 402 correspond to the same or different column lines to realize serial output or parallel output of signals respectively; such as the high-gain reading unit 401 and the low-gain reading unit 402 Corresponding to different column lines, in order to realize the parallel output of signal (as shown in Figure 1 and Figure 2); As shown in FIG. 3, FIG. 3 is a schematic diagram of a serial output pixel circuit in Embodiment 1 of the present invention.). In practical applications, parallel output and serial output can be selected according to specific requirements, which has no effect on this embodiment, only need to adjust the turn-on timing of the high-gain row selection signal rsH and the low-gain row selection signal rsL.

Please refer to FIG. 4 below in conjunction with FIG. 2 . FIG. 4 shows a timing diagram of each signal in the pixel circuit shown in FIG. 2 , to describe the specific working process of the pixel circuit in this embodiment in detail.

Before time t0, it is the global reset stage (global reset); in this stage, the transmission transistor M3 is turned on, and at the same time, the reset transistor M1 and the gain control transistor M2 are in the turned-on state, and the floating diffusion point FD is reset through the reset transistor M1 Voltage, to complete the reset operation of the photodiode PD; after the reset operation is completed, the transfer transistor M3 is turned off, and the global exposure starts.

From t1 to t2, it is the reset signal pre-charge (pre-chg rst) stage; in this stage, the reset transistor M1, the gain control transistor M2, the second high-gain storage control transistor M6, and the second low-gain storage control transistor M11 are all In the conduction state, the variable voltage Vrsf changes from a high potential to a low potential. At the same time, the first high-gain storage control transistor M5 and the first low-gain storage control transistor M10 are turned on, and the left plate of the first capacitor C1 and the second The left plate of the second capacitor C2 is set to a low potential, the right plates of the first capacitor C1 and the right plate of the second capacitor C2 are set to VDD. After the setting is completed, the first high-gain storage control transistor M5 and the first low-gain storage control transistor M10 are turned off first, and then the variable voltage Vrsf is set to a high potential.

From t2 to t3, it is the reset voltage sampling stage of the global LCG (global sample LCG rst); in this stage, the reset transistor M1 is first turned off, that is, the reset is over; then the first low-gain storage control transistor M10 is turned on, The low-gain reset voltage signal voltage Vrst_lcg is stored on the left plate of the second capacitor C2 by the first source follower transistor M4, at this moment, the voltage difference of the capacitor plate of the second capacitor C2 is (VDD-Vrst_lcg); After completion, the first low-gain storage control transistor M10 returns to the off state.

The stage from t3 to t4 is the reset voltage sampling stage (global sample HCG rst) of the global HCG; in this stage, first turn off the second low-gain storage control transistor M11, then turn off the gain control transistor M2, and then turn off the first A high-gain storage control transistor M5 is turned on, and the high-gain reset voltage signal Vrst_hcg is stored on the left plate of the first capacitor C1 through the first source follower transistor M4. At this time, the voltage difference between the capacitor plates of the first capacitor C1 is (VDD-Vrst_hcg); after the voltage storage is completed, the first high-gain storage control transistor M5 returns to the off state.

The stage from t4 to t5 is the pixel voltage pre-charging stage (pre-chg sig); in this stage, the variable voltage Vrsf changes from a high potential to a low potential, and at the same time, the first high-gain storage control transistor M5 and the first low-gain The storage control transistor M10 is turned on, setting the left plates of the first capacitor C1 and the left plates of the second capacitor C2 to a low potential.

The stage from t5 to t6 is the HCG image voltage sampling stage (global sample HCG sig); in this stage, the transfer transistor M3 is turned on, and the photodiode PD transfers the exposure charge to the floating diffusion point FD, so that the voltage at this point changes, Then, the first high-gain storage control transistor M5 is turned on, and the source terminal of the first source follower transistor M4 is connected to the left pole of the first capacitor C1, and the high-gain image voltage signal Vsig_hcg is sampled to the left pole of the first capacitor C1 On the board; the second high-gain storage control transistor M6 is in an off state, and the right plate of the first capacitor C1 is in a floating state. At this time, in order to maintain the voltage difference between the left and right plates of the first capacitor C1, the first The voltage of the right plate of the capacitor C1 is Vsig_hcg+(VDD-Vrst_hcg).

The stage from t6 to t7 is the LCG image voltage sampling stage (global sample LCG sig); in this stage, the gain control transistor M2 is first turned on, and then the transfer transistor M3 is turned on, and the photodiode PD transfers the exposure charge to the floating diffusion Point FD and the gain adjustment capacitor Cdcg realize charge redistribution, and finally turn on the first low-gain storage control transistor M10, connect the source terminal of the first source follower transistor M4 to the left plate of the second capacitor C2, and turn the low The gain image voltage signal Vlsig_lcg is sampled to the left plate of the second capacitor C2; the second low-gain storage control transistor M11 is in an off state, and the right plate of the second capacitor C2 is in a floating state. At this time, in order to maintain the second The voltage difference between the left and right plates of the capacitor C2, the voltage of the right plate of the second capacitor C2 is Vsig_lcg+(VDD-Vrst_lcg); after the sampling is completed, the first low-gain storage control transistor M10 returns to the off state, and the reset transistor M1 returns to the conduction state, and controls the subsequent readout operation through the high-gain row selection signal rsH and the low-gain row selection signal rsL (such as t9 to t10 stage).

During the entire process from t2 to t7, the global conversion operation is completed; using the characteristics of capacitor storage charge, the high-gain image voltage signal is stored on the first capacitor C1, and the low-gain image voltage signal is stored on the second capacitor C2 , and then the image voltage will be read out row by row through the high-gain row selection signal rsH and the low-gain row selection signal rsL. In the readout phase, first read the signal on the capacitor plate, and then read a power signal VDD, and make a difference between the two to get the required Vrst-Vsig. It should be noted that az in FIG. 4 represents the clearing signal of the readout circuit, clk represents the clock signal of the readout circuit, and the clock is turned on to indicate readout.

Embodiment two

This embodiment provides a method for controlling a pixel circuit, including the following steps: providing a pixel circuit as in Embodiment 1, realizing global exposure based on the pixel circuit, and obtaining voltages of an image signal and a reset signal in a high-gain transmission mode through a first capacitor The voltage difference between the image signal and the reset signal in the low-gain transmission mode is obtained through the second capacitor, so that the pixel circuit works in a different-gain transmission mode.

Specifically, in the process of implementing global exposure based on the pixel circuit shown in FIG. 1 (the high-gain readout unit 401 and the low-gain readout unit 402 do not share a source follower transistor), the signal transmission method may include: sequentially performing reset signal reset, Low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and low-gain image signal acquisition, may also include: reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition The image signal reset of the low-gain reading unit and the acquisition of the high-gain image signal are performed simultaneously while the image signal reset of the low-gain reading unit and the acquisition of the low-gain image signal are performed.

In practical applications, by connecting the first high-gain source-following transistor M4 and the first low-gain source-following transistor M9 to different high and low variable voltages, such as the first high-gain source-following transistor M4 being connected to a high level can be Variable voltage, the first low-gain source follows the transistor M9 and accesses a low-level variable voltage, so as to realize the reset of the image signal of the low-gain reading unit while the high-gain reset signal is collected, and the first low-gain source follows the transistor M9 is connected to a high-level variable voltage, and the first high-gain source follows the transistor M4 to be connected to a low-level variable voltage, so that the image signal of the high-gain reading unit is reset while the low-gain image signal is collected. . The second signal transmission mode (that is, the signal transmission sequence is: reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition while performing image signal reset of low-gain reading unit, high-gain image signal acquisition Simultaneously reset the image signal of the low-gain reading unit and collect the low-gain image signal) Compared with the first signal transmission method, it saves an image signal reset time, thereby saving the time of the pixel cycle. The two signal transmission modes can be implemented based on circuits that do not share the first source follower transistor.

Reset the transistor M1 to the first potential after the reset signal is reset, and perform low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition at the first potential; When there is a first high-gain source following transistor and a first low-gain source following transistor, in the reset signal reset process and the image signal reset process, the potential of the first high-gain source follow transistor is the same, and the first low-gain source follow transistor The transistors are at the same potential. Optionally, the first potential, the potential of the first high-gain source-follower transistor, and the potential of the first low-gain source-follower transistor are all ground potential or close to ground potential. During the reset signal reset process and the image signal reset process, by setting the potentials of the first high-gain source follower transistor and the first low-gain source follower transistor at sufficiently low levels, it is avoided that the floating diffusion point FD The problem that the back-end source follower transistor cannot be turned on caused by the potential drop (potential drop due to too long exposure time) makes low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and Low-gain image signal acquisition can be performed at the first potential, thereby saving power consumption; moreover, due to the design of the gain control transistor M2, the potential of the floating diffusion point FD will be less affected by the exposure time.

Specifically, in the process of realizing global exposure based on the pixel circuit shown in FIG. 2 (the high-gain readout unit 401 and the low-gain readout unit 402 share a source follower transistor), the signal transmission methods include: sequentially reset the reset signal, low-gain Reset signal acquisition, high gain reset signal acquisition, image signal reset, high gain image signal acquisition and low gain image signal acquisition.

Reset the transistor M1 to the first potential after the reset signal is reset, and perform low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition at the first potential; During the reset signal reset process and the image signal reset process, the common source follower transistor has the same potential. Optionally, both the first potential and the potential of the shared source-follower transistor are ground potential or close to ground potential. During the reset signal reset process and the image signal reset process, by setting the potential of the shared source follower transistor at a sufficiently low level, the potential drop due to the floating diffusion point FD (potential drop due to long exposure time) is avoided. The resulting problem that the back-end source-following transistor cannot be turned on makes low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and low-gain image signal acquisition all possible under the first potential Therefore, power consumption is saved; moreover, due to the design of the gain control transistor M2, the potential of the floating diffusion point FD is less affected by the exposure time.

Specifically, the control method includes: in the first high-gain transmission mode, the left plate of the first capacitor stores the high-gain reset voltage signal Vrst hcg, the right plate stores the first power supply voltage signal Vdd, and the left and right plates of the first capacitor store the high-gain reset voltage signal Vrst hcg. The voltage difference between the plates is Vdd-Vrst hcg, so that in the second high-gain transmission mode, when the left plate of the first capacitor stores the high-gain image voltage signal Vsig hcg, the right plate stores the high-gain output voltage signal Vsig hcg+ (Vdd-Vrst hcg); in the first low-gain transmission mode, the left plate of the second capacitor stores the low-gain reset voltage signal Vrst lcg, the right plate stores the first power supply voltage signal Vdd, and the left and right plates of the second capacitor The voltage difference between the plates is Vdd-Vrst lcg, so that in the second low-gain transmission mode, when the left plate of the second capacitor stores the low-gain image voltage signal Vsig lcg, the right plate stores and outputs the low-gain voltage signal Vsig lcg+ (Vdd-Vrst lcg). It should be noted that the specific control manner can be found in Embodiment 1, and will not be repeated here.

More specifically, the readout process of the pixel circuit includes the first stage and the second stage. In the first stage, the pixel circuit outputs the voltage signal Vsig+(Vdd-Vrst), and in the second stage, the pixel circuit outputs the first power supply voltage signal Vdd . By making a difference between the voltage signals output by the first stage and the second stage, the voltage difference between the image voltage signal and the reset voltage signal in different gain transmission modes, that is, the pixel signal can be obtained.

Specifically, the signal output modes of the high-gain reading unit and the low-gain reading unit include serial output or parallel output. In practical applications, serial output and parallel output can be selected according to specific requirements, which has no effect on this embodiment, only need to adjust the turn-on timing of the high-gain row selection signal rsH and the low-gain row selection signal rsL.

Embodiment three

This embodiment provides a CMOS image sensor, and the CMOS image sensor includes: at least one pixel circuit as in Embodiment 1.

Specifically, the CMOS image sensor includes several pixels, the pixels are arranged in rows and columns to form a pixel array, and the pixels correspond to the pixel circuits. In practical application, there is a one-to-one correspondence between pixels and pixel circuits, that is, each pixel is composed of pixel circuits; of course, multiple pixels can also share the same reading module 400 , which has no influence on this embodiment.

Specifically, in an example, the CMOS image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module 300 is located in the first semiconductor substrate, and the reading module 400 is located in the second semiconductor substrate. In yet another example, the CMOS image sensor includes a first semiconductor substrate and a second semiconductor substrate that are stacked, and the photosensitive control module 300 and the reading module 400 are located in the first semiconductor substrate. The CMOS image sensor also includes a logic circuit, and the logic circuit Circuitry is located within the second semiconductor substrate. In another example, the CMOS image sensor includes a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate stacked, the photosensitive control module 300 is located in the first semiconductor substrate, and the reading module 400 is located in the second semiconductor substrate. In the substrate, the CMOS image sensor also includes a logic circuit, and the logic circuit is located in the third semiconductor substrate. It should be noted that the electrical connection (bonding) between the various substrates can be realized based on the circuit using existing processes, for example, using metal pads and interconnection lines or using TSV vias to realize the electrical connection between transistor devices. sexual connection.

In summary, a pixel circuit, CMOS image sensor and control method of the present invention, through the design of the gain control module and the reading module, adopts the double conversion gain technology to effectively improve the dynamic range of the CMOS image sensor; Larger capacitors increase stored charge, reduce gain to increase dynamic range, and use smaller capacitors for low-intensity light areas to increase gain and achieve high sensitivity. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (17)

1. A pixel circuit, characterized in that the pixel circuit comprises: a reset module, a gain control module, a photosensitive control module and a reading module, wherein, The reset module includes a reset transistor, the gate terminal of the reset transistor is connected to a reset control signal, the first connection terminal is connected to a power supply voltage, and the second connection terminal is connected to a floating diffusion point; The gain control module is connected between the second connection terminal of the reset transistor and the floating diffusion point, and is controlled by a gain control signal, and is used to adjust the equivalent of the floating diffusion point according to the gain control signal. charge storage capacity, enabling the pixel circuit to work in different gain transfer modes; The photosensitive control module is connected between the floating diffusion point and the first reference voltage, and is controlled by a transmission control signal, for generating exposure charges according to the photoelectric effect, and transferring the exposure charges according to the transmission control signal output; The reading module includes a high-gain reading unit and a low-gain reading unit, both of which are connected to the floating diffusion point, wherein the high-gain reading unit is used to read the floating diffusion point in the high-gain transmission mode and output the voltage signal; the low-gain reading unit is used to read and output the voltage signal of the floating diffusion point in the low-gain transmission mode; the high-gain reading unit includes a first capacitor, and the low-gain reading unit The acquisition unit includes a second capacitor, the first capacitor is used to obtain the voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor is used to obtain the voltage difference between the image signal and the reset signal in the low-gain transmission mode Voltage difference. 2. The pixel circuit according to claim 1, wherein the high-gain transmission mode comprises a first high-gain transmission mode and a second high-gain transmission mode, and in the first high-gain transmission mode, the The left plate of the first capacitor stores the high-gain reset voltage signal Vrst hcg, and the right plate stores the first power supply voltage signal Vdd, and in the second high-gain transmission mode, the left plate of the first capacitor stores the high-gain Image voltage signal Vsig hcg, the right plate stores high-gain output voltage signal Vsig hcg+(Vdd-Vrst hcg); and/or, The low-gain transmission mode includes a first low-gain transmission mode and a second low-gain transmission mode, and in the first low-gain transmission mode, the left plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg, The right plate stores the first power supply voltage signal Vdd, and in the second low-gain transmission mode, the left plate of the second capacitor stores the low-gain image voltage signal Vsig lcg, and the right plate stores the output low-gain voltage signal Vsig lcg+(Vdd-Vrst lcg). 3. The pixel circuit according to claim 1, wherein the high-gain reading unit further comprises: a first high-gain source-follower transistor, a first high-gain storage control transistor, a second high-gain storage control transistor , the second high-gain source follower transistor and the first row selection transistor; The gate terminal of the first high-gain source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to the first variable voltage, and the second connection terminal is connected to the first connection of the first high-gain storage control transistor terminal; the gate terminal of the first high-gain storage control transistor is connected to the first high-gain storage control signal, and the second connection terminal is connected to the left plate of the first capacitor; the right plate of the first capacitor is connected to the The second connection terminal of the second high-gain storage control transistor and the gate terminal of the second high-gain source follower transistor; the gate terminal of the second high-gain storage control transistor is connected to the second high-gain storage control signal, the first A connection terminal is connected to the first power supply voltage; the first connection terminal of the second high-gain source follower transistor is connected to the second power supply voltage, and the second connection terminal is connected to the first connection terminal of the first row selection transistor; The gate end of the first row selection transistor is connected to a high-gain row selection signal, and the second connection end is used as the output end of the high-gain reading unit; The low-gain reading unit at least further includes: a first low-gain source follower transistor, a first low-gain storage control transistor, a second low-gain storage control transistor, a second low-gain source follower transistor, and a second row selection transistor; The gate terminal of the first low-gain source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to the second variable voltage, and the second connection terminal is connected to the first connection of the first low-gain storage control transistor terminal; the gate terminal of the first low-gain storage control transistor is connected to the first low-gain storage control signal, and the second connection terminal is connected to the left plate of the second capacitor; the right plate of the second capacitor is connected to the The second connection terminal of the second low-gain storage control transistor and the gate terminal of the second low-gain source follower transistor; the gate terminal of the second low-gain storage control transistor is connected to the second low-gain storage control signal, the first A connection terminal is connected to the third power supply voltage; the first connection terminal of the second low-gain source follower transistor is connected to the fourth power supply voltage, and the second connection terminal is connected to the first connection terminal of the second row selection transistor; The gate terminal of the second row selection transistor is connected to the low-gain row selection signal, and the second connection terminal is used as the output terminal of the low-gain reading unit. 4. The pixel circuit according to claim 3, wherein the first high-gain source-follower transistor and the first low-gain source-follower transistor are the same source-follower transistor, and the gate of the shared source-follower transistor terminal is connected to the floating diffusion point, the first connection terminal is connected to a variable voltage, and the second connection terminal is respectively connected to the first connection terminal of the first high-gain storage control transistor and the first connection terminal of the first low-gain storage control transistor. first connection end. 5. The pixel circuit according to claim 3 or 4, wherein the high-gain reading unit comprises a third capacitor connected to the second connection of the first high-gain storage control transistor terminal and the second reference voltage; and/or, the low-gain reading unit includes a fourth capacitor connected to the second connection terminal of the first low-gain storage control transistor and the third reference voltage between. 6. The pixel circuit according to claim 1, wherein the gain control module comprises: a gain control transistor and a gain adjustment capacitor, wherein the gate terminal of the gain control transistor is connected to the gain control signal, the second A connection terminal is connected to the second connection terminal of the reset transistor and connected to the fourth reference voltage through the gain adjustment capacitor, and the second connection terminal is connected to the floating diffusion point. 7. The pixel circuit according to claim 6, wherein the gain adjustment capacitor is a parasitic capacitance between the connection point of the reset transistor and the gain control transistor to ground; or, the gain adjustment capacitor is a device capacitor . 8. The pixel circuit according to claim 1, wherein the photosensitive control module comprises: a photoelectric conversion element and a transfer transistor, wherein the output end of the photoelectric conversion element is connected to the first connection end of the transfer transistor , the other terminal is connected to the first reference voltage; the gate terminal of the transmission transistor is connected to the transmission control signal, and the second connection terminal is connected to the floating diffusion point. 9. The pixel circuit according to claim 1, wherein the high-gain readout unit and the low-gain readout unit correspond to the same or different column lines, so as to realize serial output or parallel output of signals respectively . 10. A method for controlling a pixel circuit, comprising the following steps: A pixel circuit according to any one of claims 1-9 is provided; global exposure is realized based on the pixel circuit, and the voltage difference between the image signal and the reset signal in the high-gain transmission mode is obtained through the first capacitor, and the voltage difference between the image signal and the reset signal is obtained through the first capacitor. The second capacitor obtains the voltage difference between the image signal and the reset signal in the low-gain transmission mode, so that the pixel circuit works in a different-gain transmission mode. 11. The control method of the pixel circuit according to claim 10, characterized in that the control method comprises: In the first high-gain transmission mode, the left plate of the first capacitor stores the high-gain reset voltage signal Vrsthcg, and the right plate stores the first power supply voltage signal Vdd. Between the left and right plates of the first capacitor The voltage difference is Vdd-Vrsthcg, so that in the second high-gain transmission mode, when the left plate of the first capacitor stores the high-gain image voltage signal Vsighcg, the right plate stores the high-gain output voltage signal Vsighcg+(Vdd-Vrst hcg); In the first low-gain transmission mode, the left plate of the second capacitor stores the low-gain reset voltage signal Vrstlcg, and the right plate stores the first power supply voltage signal Vdd. Between the left and right plates of the second capacitor The voltage difference is Vdd-Vrstlcg, so that in the second low-gain transmission mode, when the left plate of the second capacitor stores the low-gain image voltage signal Vsiglcg, the right plate stores and outputs the low-gain voltage signal Vsig lcg+(Vdd -Vrst lcg). 12. The control method of the pixel circuit according to claim 11, characterized in that, in the process of realizing global exposure based on the pixel circuit, the signal transmission method includes: performing reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition in sequence; or, Signal transmission methods include: reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition and low-gain reading unit image signal reset, high-gain image signal acquisition and low-gain reading unit image Signal reset, low gain image signal acquisition. 13. The method for controlling a pixel circuit according to claim 11, wherein the readout process of the pixel circuit includes a first stage and a second stage, and in the first stage, the pixel circuit outputs an output voltage signal Vsig+(Vdd-Vrst), in the second stage, the pixel circuit outputs the first power supply voltage signal Vdd. 14. The method for controlling a pixel circuit according to claim 10, wherein the signal output modes of the high-gain reading unit and the low-gain reading unit include serial output or parallel output. 15. The control method of the pixel circuit according to any one of claims 10-14, characterized in that, after the reset signal is reset, the reset transistor is set to a first potential, and low voltage is performed under the first potential. Gain reset signal acquisition, high gain reset signal acquisition, image signal reset, high gain image signal acquisition and low gain image signal acquisition; and/or, when there is a first high gain source follower transistor and a first low gain source follower transistor or When the two are shared, in the process of resetting the reset signal and the process of resetting the image signal, the potential of the first high-gain source following the transistor is the same, and the potential of the first low-gain source following the transistor is the same. 16. A CMOS image sensor, characterized in that the CMOS image sensor comprises: the pixel circuit according to any one of claims 1-9. 17. The image sensor according to claim 16, characterized in that the image sensor comprises a first semiconductor substrate and a second semiconductor substrate arranged in a stack, and the photosensitive control module is located in the first semiconductor substrate , the reading module is located in the second semiconductor substrate; or, the image sensor includes a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate stacked, and the photosensitive control module is located in In the first semiconductor substrate, the reading module is located in the second semiconductor substrate, and the image sensor further includes a logic circuit, and the logic circuit is located in the third semiconductor substrate; or, the The image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module and the reading module are located in the first semiconductor substrate, the image sensor also includes a logic circuit, the A logic circuit is located on the second semiconductor substrate.

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