CN116112815A

CN116112815A - Pixel circuit, CMOS image sensor and control method

Info

Publication number: CN116112815A
Application number: CN202111314041.4A
Authority: CN
Inventors: 刘洲宏; 侯金剑
Original assignee: SmartSens Technology Shanghai Co Ltd
Current assignee: SmartSens Technology Shanghai Co Ltd
Priority date: 2021-11-08
Filing date: 2021-11-08
Publication date: 2023-05-12

Abstract

The invention provides a pixel circuit, comprising: the device comprises a reset module, a gain control module, a photosensitive control module and a reading module; the reading module comprises a high-gain reading unit and a low-gain reading unit which are both connected to the floating diffusion point, wherein the high-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a high-gain transmission mode, and the low-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a low-gain transmission mode; the high-gain reading unit comprises a first capacitor and the low-gain reading unit comprises a second capacitor, wherein the first capacitor is used for acquiring the voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor is used for acquiring the voltage difference between the image signal and the reset signal in the low-gain transmission mode. The pixel circuit provided by the invention solves the problem of low dynamic range of the conventional CMOS image sensor.

Description

Pixel circuit, CMOS image sensor and control method

Technical Field

The present invention relates to the field of CMOS image sensors, and more particularly, to a pixel circuit, a CMOS image sensor, and a control method thereof.

Background

A global exposure technique (global camera) is an imaging technique that needs to be applied in realizing high-speed photography, all signals are exposed simultaneously, and an image without distortion is generated; the main implementation principle is that a storage capacitor is added in each pixel circuit, all pixel circuits are exposed simultaneously, and then photoelectric conversion signals are stored in the storage capacitor to wait for the subsequent circuit to read.

In some environments with large light difference, the dynamic range is a key index for influencing the imaging effect; it determines the range of light intensity distribution from the darkest shadow to the brightest highlight acceptable for CMOS image sensors, i.e., determines the details, level, and characteristics of the captured image. Therefore, how to increase the dynamic range of CMOS image sensors is a problem to be solved by those skilled in the art.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a pixel circuit, a CMOS image sensor and a control method for solving the problem of low dynamic range of the existing CMOS image sensor.

To achieve the above and other related objects, the present invention provides a pixel circuit including: the device comprises a reset module, a gain control module, a photosensitive control module and a reading module, wherein,

The reset module comprises a reset transistor, wherein a gate end of the reset transistor is connected with a reset control signal, a first connecting end is connected with a power supply voltage, and a second connecting end is connected to a floating diffusion point;

the gain control module is connected between the second connection end of the reset transistor and the floating diffusion point, is controlled by a gain control signal and is used for adjusting the equivalent charge storage capacity of the floating diffusion point according to the gain control signal so that the pixel circuit works in different gain transmission modes;

the photosensitive control module is connected between the floating diffusion point and the first reference voltage, is controlled by a transmission control signal, and is used for generating exposure charges according to a photoelectric effect and transferring and outputting the exposure charges according to the transmission control signal;

the reading module comprises a high-gain reading unit and a low-gain reading unit which are both connected to the floating diffusion point, wherein the high-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a high-gain transmission mode; the low-gain reading unit is used for reading and outputting the voltage signal of the floating diffusion point in the low-gain transmission mode; the high-gain reading unit comprises a first capacitor, the low-gain reading unit comprises a second capacitor, the first capacitor is used for acquiring the voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor is used for acquiring the voltage difference between the image signal and the reset signal in the low-gain transmission mode.

Optionally, the high-gain transmission mode includes a first high-gain transmission mode in which a left plate of the first capacitor stores a high-gain reset voltage signal Vrst hcg, a right plate stores a first power voltage signal Vdd, and a second high-gain transmission mode in which a left plate of the first capacitor stores a high-gain image voltage signal vsighcg, a right plate stores a high-gain output voltage signal vsighcg+ (Vdd-Vrst hcg); and/or the low-gain transmission mode includes a first low-gain transmission mode in which the left plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg, the right plate stores a first power supply voltage signal Vdd, and a second low-gain transmission mode in which the left plate of the second capacitor stores a low-gain image voltage signal vsiglcg, and the right plate stores an output low-gain voltage signal vsiglcg+ (Vdd-Vrst lcg).

Optionally, the high gain reading unit further includes at least: a first high-gain source follower transistor, a first high-gain memory control transistor, a second high-gain source follower transistor, and a first row select transistor; the gate end of the first high-gain source follower transistor is connected to the floating diffusion point, the first connecting end is connected to a first variable voltage, and the second connecting end is connected to the first connecting end of the first high-gain storage control transistor; the gate end of the first high-gain storage control transistor is connected with a first high-gain storage control signal, and the second connecting end of the first high-gain storage control transistor is connected with the left polar plate of the first capacitor; the right polar plate of the first capacitor is connected with the second connecting end of the second high-gain storage control transistor and the gate end of the second high-gain source follower transistor; the gate end of the second high-gain storage control transistor is connected with a second high-gain storage control signal, and the first connecting end is connected with a first power supply voltage; the first connecting end of the second high-gain source follower transistor is connected with a second power supply voltage, and the second connecting end is connected with the first connecting end of the first row selection transistor; the gate end of the first row selection transistor is connected with a high-gain row selection signal, and the second connection end is used as the output end of the high-gain reading unit;

The low gain reading unit further includes at least: a first low-gain source follower transistor, a first low-gain memory control transistor, a second low-gain source follower transistor, and a second row select transistor; the gate end of the first low-gain source follower transistor is connected to the floating diffusion point, the first connecting end is connected to a second variable voltage, and the second connecting end is connected to the first connecting end of the first low-gain storage control transistor; the gate end of the first low-gain storage control transistor is connected with a first low-gain storage control signal, and the second connecting end of the first low-gain storage control transistor is connected with the left polar plate of the second capacitor; the right polar plate of the second capacitor is connected with the second connecting end of the second low-gain storage control transistor and the gate end of the second low-gain source follower transistor; the gate end of the second low-gain storage control transistor is connected with a second low-gain storage control signal, and the first connecting end is connected with a third power supply voltage; the first connecting end of the second low-gain source follower transistor is connected with a fourth power supply voltage, and the second connecting end of the second low-gain source follower transistor is connected with the first connecting end of the second row selection transistor; and the gate end of the second row selection transistor is connected with a low-gain row selection signal, and the second connection end is used as the output end of the low-gain reading unit.

Optionally, the first high-gain source follower transistor and the first low-gain source follower transistor are the same source follower transistor, a gate terminal of the common source follower transistor is connected to the floating diffusion point, a first connection terminal is connected to a variable voltage, and a second connection terminal is respectively connected to the first connection terminal of the first high-gain storage control transistor and the first connection terminal of the first low-gain storage control transistor.

Optionally, the high-gain reading unit includes a third capacitor connected between the second connection terminal of the first high-gain storage control transistor and a second reference voltage; and/or the low gain reading unit comprises a fourth capacitor connected between the second connection terminal of the first low gain storage control transistor and a third reference voltage.

Optionally, the gain control module includes: the gain control transistor and the gain adjustment capacitor, wherein the gate end of the gain control transistor is connected with the gain control signal, the first connecting end is connected with the second connecting end of the reset transistor, the gain control transistor is connected with the fourth reference voltage through the gain adjustment capacitor, and the second connecting end is connected to the floating diffusion point.

Optionally, the gain adjustment capacitor is a parasitic capacitor of the connection point of the reset transistor and the gain control transistor to ground; alternatively, the gain adjustment capacitance is a device capacitance.

Optionally, the photosensitive control module includes: the output end of the photoelectric conversion element is connected with the first connecting end of the transmission transistor, and the other end of the photoelectric conversion element is connected with the first reference voltage; the gate end of the transmission transistor is connected with the transmission control signal, and the second connecting end is connected to the floating diffusion point.

Optionally, the high gain reading unit and the low gain reading unit correspond to the same or different column lines to realize serial output or parallel output of signals respectively.

The invention also provides a control method of the pixel circuit, which comprises the following steps: providing a pixel circuit as claimed in any one of the above; and realizing global exposure based on the pixel circuit, acquiring the voltage difference between the image signal and the reset signal in the high-gain transmission mode through the first capacitor, and acquiring the voltage difference between the image signal and the reset signal in the low-gain transmission mode through the second capacitor so as to enable the pixel circuit to work in different gain transmission modes.

Optionally, the control method includes: in a first high-gain transmission mode, the left plate of the first capacitor stores a high-gain reset voltage signal Vrst hcg, the right plate stores a first power voltage signal Vdd, and the voltage difference between the left plate and the right plate of the first capacitor is Vdd-Vrst hcg, so that in a second high-gain transmission mode, when the left plate of the first capacitor stores a high-gain image voltage signal Vsig hcg, the right plate stores a high-gain output voltage signal Vsig hcg+ (Vdd-Vrst hcg); in the first low-gain transmission mode, the left plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg, the right plate stores a first power voltage signal Vdd, and the voltage difference between the left plate and the right plate of the second capacitor is Vdd-Vrst lcg, so that when the left plate of the second capacitor stores the low-gain image voltage signal Vsig lcg in the second low-gain transmission mode, the right plate stores and outputs a low-gain voltage signal Vsig lcg+ (Vdd-Vrst lcg).

Optionally, in the process of implementing global exposure based on the pixel circuit, the signal transmission mode includes: reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and low-gain image signal acquisition are sequentially carried out; alternatively, the signal transmission method includes: resetting the reset signal, collecting the low-gain reset signal, collecting the high-gain reset signal, and simultaneously resetting the image signal of the low-gain reading unit, collecting the high-gain image signal, and simultaneously resetting the image signal of the low-gain reading unit and collecting the low-gain image signal.

Optionally, the readout process of the pixel circuit includes a first phase in which the pixel circuit outputs the output voltage signal vsig+ (Vdd-Vrst) and a second phase in which the pixel circuit outputs the first power supply voltage signal Vdd.

Optionally, the signal output modes of the high gain reading unit and the low gain reading unit include serial output or parallel output.

Optionally, resetting the reset transistor to a first potential after resetting the reset signal, and performing low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and low-gain image signal acquisition under the first potential; and/or when the first high-gain source follower transistor and the first low-gain source follower transistor or both are shared, the potential of the first high-gain source follower transistor is the same and the potential of the first low-gain source follower transistor is the same in the reset signal reset process and the image signal reset process.

The present invention also provides a CMOS image sensor including: a pixel circuit as claimed in any one of the preceding claims.

Optionally, the image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module is located in the first semiconductor substrate, and the reading module is located in the second semiconductor substrate; or the image sensor comprises a first semiconductor substrate, a second semiconductor substrate and a third semiconductor substrate which are stacked, wherein the photosensitive control module is positioned in the first semiconductor substrate, the reading module is positioned in the second semiconductor substrate, and the image sensor further comprises a logic circuit which is positioned in the third semiconductor substrate; or, the image sensor comprises a first semiconductor substrate and a second semiconductor substrate which are stacked, the photosensitive control module and the reading module are positioned in the first semiconductor substrate, and the image sensor further comprises a logic circuit which is positioned in the second semiconductor substrate.

As described above, according to the pixel circuit, the CMOS image sensor and the control method of the present invention, the dynamic range of the CMOS image sensor is effectively improved by adopting the dual conversion gain technology through the design of the gain control module and the reading module; and a larger capacitor is used for a high-intensity illumination area, the stored charge is improved, the gain is reduced to improve the dynamic range, a smaller capacitor is used for a low-intensity illumination area, the gain is improved, and high sensitivity is realized.

Drawings

Fig. 1 is a schematic diagram of a parallel output pixel circuit according to a first embodiment of the invention.

Fig. 2 is a schematic diagram of the pixel circuit shown in fig. 1 when the pixel circuit shares a first source follower transistor.

Fig. 3 is a schematic diagram of a serial output pixel circuit according to a first embodiment of the invention.

Fig. 4 is a timing chart showing signals in the pixel circuit shown in fig. 2.

Description of element reference numerals

100. Reset module

200. Gain control module

300. Photosensitive control module

400. Reading module

401. High gain reading unit

402. Low gain reading unit

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 4. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Example 1

As shown in fig. 1, fig. 1 is a schematic diagram of a parallel output pixel circuit according to a first embodiment of the invention. The present embodiment provides a pixel circuit including: the device comprises a reset module 100, a gain control module 200, a photosensitive control module 300 and a reading module 400.

As shown in fig. 1, the reset module 100 includes a reset transistor M1, where a gate of the reset transistor M1 is connected to a reset control signal rst, a first connection terminal is connected to a power supply voltage VDD, and a second connection terminal is connected to a floating diffusion FD, for resetting a voltage of the floating diffusion FD according to the reset control signal rst, so as to complete a reset operation of a photoelectric conversion element (e.g., a photodiode PD) in the photosensitive control module 300. Optionally, the reset transistor M1 is an NMOS transistor, and the first connection terminal is a drain terminal, and the second connection terminal is a source terminal.

As shown in fig. 1, the gain control module 200 is connected between the second connection terminal of the reset transistor M1 and the floating diffusion FD, and is controlled by the gain control signal dcg, and is used for adjusting the equivalent charge storage capacity of the floating diffusion FD according to the gain control signal dcg, so that the pixel circuit operates in different gain transmission modes, that is, the CMOS image sensor formed by the pixel circuit operates in different gain transmission modes.

Specifically, as shown in fig. 1, the gain control module 200 includes: the gain control transistor M2 and the gain adjustment capacitor Cdcg, where the gate of the gain control transistor M2 is connected to the gain control signal dcg, the first connection terminal is connected to the second connection terminal of the reset transistor M1, and is connected to the fourth reference voltage through the gain adjustment capacitor Cdcg, and the second connection terminal is connected to the floating diffusion FD. Optionally, the gain control transistor M2 is an NMOS transistor, and the first connection terminal is a drain terminal, and the second connection terminal is a source terminal; the gain adjustment capacitor Cdcg may be a parasitic capacitor of the connection point of the reset transistor M1 and the gain control transistor M2 to ground, or may be a device capacitor (i.e. an external capacitor); optionally, the fourth reference voltage is a ground voltage.

In this embodiment, when the gain control signal dcg is at a high level, the gain control transistor M2 is turned on, and the equivalent charge storage capacity of the floating diffusion FD is increased by the gain adjustment capacitor Cdcg, so that the final charge storage capacity is the sum of the charge storage capacity of the floating diffusion FD and the charge storage capacity of the gain adjustment capacitor Cdcg, and at this time, the CMOS image sensor formed by the pixel circuit operates in a low gain transmission mode (LCG); conversely, when the gain control signal dcg is low, the gain control transistor M2 is turned off, so that the charge storage capacity of the floating diffusion FD itself is the final charge storage capacity, and at this time, the CMOS image sensor formed by the pixel circuit operates in the high gain transmission mode (HCG).

As shown in fig. 1, the photosensitive control module 300 is connected between the floating diffusion FD and the first reference voltage, and is controlled by a transmission control signal tx for generating an exposure charge according to the photoelectric effect and transferring the exposure charge according to the transmission control signal tx.

Specifically, as shown in fig. 1, the photosensitive control module 300 includes: the photoelectric conversion device comprises a photoelectric conversion element and a transmission transistor M3, wherein the output end of the photoelectric conversion element is connected with a first connection end of the transmission transistor M3, and the other end of the photoelectric conversion element is connected with a first reference voltage; the gate terminal of the transfer transistor M3 is connected to the transfer control signal tx, and the second connection terminal is connected to the floating diffusion FD. Optionally, the photoelectric conversion element is a photodiode PD, the output end of the photoelectric conversion element is a cathode of the photodiode PD, and the other end of the photoelectric conversion element is an anode of the photodiode PD; the transmission transistor M3 is an NMOS (N-channel metal oxide semiconductor) tube, a first connecting end of the transmission transistor M3 is a drain end, and a second connecting end of the transmission transistor M is a source end; in an embodiment of the present invention, optionally, the first reference voltage is a ground voltage.

In this embodiment, the photodiode PD generates exposure charges according to the photoelectric effect in response to incident light, and the transfer transistor M3 is turned on when the transfer control signal tx is at a high level, and transfers and outputs the exposure charges generated by the photodiode PD.

As shown in fig. 1, the reading module 400 includes a high gain reading unit 401 and a low gain reading unit 402, both connected to the floating diffusion FD; the high gain reading unit 401 is configured to read and output a voltage signal of the floating diffusion FD in the high gain transmission mode; the low gain reading unit 402 is configured to read and output a voltage signal of the floating diffusion FD in the low gain transmission mode; the high-gain reading unit 401 includes a first capacitor C1, the low-gain reading unit 402 includes a second capacitor C2, the first capacitor C1 is used for acquiring a voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor C2 is used for acquiring a voltage difference between the image signal and the reset signal in the low-gain transmission mode.

Specifically, the high-gain transmission mode includes a first high-gain transmission mode in which the left plate of the first capacitor C1 stores the high-gain reset voltage signal Vrst hcg, the right plate stores the first power voltage signal Vdd, and a second high-gain transmission mode in which the left plate of the first capacitor stores the high-gain image voltage signal vsighcg, the right plate stores the high-gain output voltage signal vsighcg+ (Vdd-Vrst hcg), so that a voltage difference between the image signal and the reset signal in the high-gain transmission mode is obtained by using the first capacitor C1; and/or the low-gain transmission mode comprises a first low-gain transmission mode and a second low-gain transmission mode, wherein in the first low-gain transmission mode, a left polar plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg, a right polar plate stores a first power voltage signal Vdd, in the second low-gain transmission mode, a left polar plate of the second capacitor stores a low-gain image voltage signal Vsig lcg, and a right polar plate stores and outputs a low-gain voltage signal Vsig lcg+ (Vdd-Vrst lcg), so that a voltage difference between the image signal and the reset signal in the low-gain transmission mode is obtained by utilizing the second capacitor C2. Alternatively, the first power supply voltage Vdd is a power supply voltage Vdd of a positive potential.

Specifically, as shown in fig. 1, the high-gain reading unit 401 further includes at least: a first high-gain source follower transistor M4, a first high-gain memory control transistor M5, a second high-gain memory control transistor M6, a second high-gain source follower transistor M7, and a first row selection transistor M8; the gate end of the first high-gain source follower transistor M4 is connected to the floating diffusion FD, the first connection end is connected to the first variable voltage Vrsf1, and the second connection end is connected to the first connection end of the first high-gain memory control transistor M5; the gate end of the first high-gain storage control transistor M5 is connected with a first high-gain storage control signal SHCG, and the second connecting end is connected with the left polar plate of the first capacitor C1; the right electrode plate of the first capacitor C1 is connected with the second connection end of the second high-gain storage control transistor M6 and the gate end of the second high-gain source follower transistor M7; the gate terminal of the second high-gain memory control transistor M6 is connected to the second high-gain memory control signal rstH, and the first connection terminal is connected to the first power supply voltage Vdd1; the first connection end of the second high-gain source follower transistor M7 is connected to the second power supply voltage Vdd2, and the second connection end is connected to the first connection end of the first row selection transistor M8; the gate terminal of the first row selection transistor M8 is connected to the high-gain row selection signal rsH, and the second connection terminal is used as the output terminal of the high-gain reading unit 401. Optionally, the first high-gain source follower transistor M4, the first high-gain memory control transistor M5, the second high-gain memory control transistor M6, the second high-gain source follower transistor M7, and the first row select transistor M8 are NMOS transistors, and the first connection terminal is a drain terminal, and the second connection terminal is a source terminal.

The low gain reading unit 402 further includes at least: a first low-gain source follower transistor M9, a first low-gain memory control transistor M10, a second low-gain memory control transistor M11, a second low-gain source follower transistor M12, and a second row selection transistor M13; the gate end of the first low-gain source follower transistor M9 is connected to the floating diffusion point FD, the first connecting end is connected to the second variable voltage Vrsf2, and the second connecting end is connected to the first connecting end of the first low-gain storage control transistor M10; the gate end of the first low-gain storage control transistor M10 is connected with a first low-gain storage control signal SLCH, and the second connecting end is connected with the left polar plate of the second capacitor C2; the right electrode plate of the second capacitor C2 is connected to the second connection end of the second low-gain storage control transistor M11 and the gate end of the second low-gain source follower transistor M12; the gate terminal of the second low-gain memory control transistor M11 is connected to the second low-gain memory control signal rstL, and the first connection terminal is connected to the third power supply voltage Vdd3; the first connection end of the second low-gain source follower transistor M12 is connected to the fourth power supply voltage Vdd4, and the second connection end is connected to the first connection end of the second row selection transistor M13; the gate terminal of the second row selection transistor M13 is connected to the low gain row selection signal rsL, and the second connection terminal is used as the output terminal of the low gain reading unit 402.

Optionally, the first high-gain source follower transistor M4, the first high-gain memory control transistor M5, the second high-gain memory control transistor M6, the second high-gain source follower transistor M7, the first row selection transistor M8, the first low-gain source follower transistor M9, the first low-gain memory control transistor M10, the second low-gain memory control transistor M11, the second low-gain source follower transistor M12 and the second row selection transistor M13 are NMOS transistors, the first connection terminal is a drain terminal, and the second connection terminal is a source terminal; alternatively, the first variable voltage Vrsf1 and the second variable voltage Vrsf2 are the same variable voltage Vrsf, that is, the first high-gain memory control transistor M5 and the first low-gain source follower transistor M9 are the same source follower transistor, and the drain of this source follower transistor is connected to the variable voltage Vrsf; optionally, the first variable voltage Vrsf1 and the second variable voltage Vrsf2 are different variable voltages, that is, the first high-gain storage control transistor M5 and the first low-gain source follower transistor M9 are different source follower transistors, and the drains of the two are respectively connected to the first variable voltage Vrsf1 and the second variable voltage Vrsf2; the first power supply voltage Vdd1, the second power supply voltage Vdd2, the third power supply voltage Vdd3, and the fourth power supply voltage Vdd4 are all power supply voltages Vdd of positive potential.

In the present embodiment, for the high gain reading unit 401: in the first high-gain transmission mode, the variable voltage Vrsf is at a high level, and the first high-gain source follower transistor M4, the first high-gain storage control transistor M5 and the second high-gain storage control transistor M6 are turned on, so that the left plate of the first capacitor C1 stores the high-gain reset voltage signal Vrst hcg and the right plate stores the power voltage signal VDD; in the second high gain transmission mode, the variable voltage Vrsf is at a high level, the first high gain source follower transistor M4 and the first high gain storage control transistor M5 are turned on, the second high gain storage control transistor M6 is turned off, the left plate of the first capacitor C1 stores the high gain image voltage signal Vsig hcg, and the right plate of the first capacitor C1 stores the high gain output voltage signal Vsig hcg+ (VDD-Vrst hcg) in order to maintain the voltage difference between the left and right plates of the first capacitor C1. For the low gain reading unit 402: in the first low-gain transmission mode, the variable voltage Vrsf is at a high level, and the first low-gain source follower transistor M9, the first low-gain storage control transistor M10 and the second low-gain storage control transistor M11 are turned on, so that the left plate of the second capacitor C2 stores the low-gain reset voltage signal Vrst lcg and the right plate stores the power voltage signal VDD; in the second low-gain transmission mode, the variable voltage Vrsf is at a high level, the first low-gain source follower transistor M9 and the first low-gain storage control transistor M10 are turned on, the second low-gain storage control transistor M11 is turned off, the left plate of the second capacitor C2 stores the low-gain image voltage signal vsiglcg, and the right plate of the second capacitor C2 stores and outputs the low-gain voltage signal vsiglcg+ (VDD-Vrst lcg) in order to maintain the voltage difference between the left and right plates of the second capacitor C2.

Further, as shown in fig. 1, the high-gain reading unit 401 includes a third capacitor C3, where the third capacitor C3 is connected between the second connection terminal of the first high-gain storage control transistor M5 and the second reference voltage, and is used to absorb the charge at the moment when the first high-gain storage control transistor M5 is turned off; and/or, the low-gain reading unit 402 includes a fourth capacitor C4, where the fourth capacitor C4 is connected between the second connection terminal of the first low-gain storage control transistor M10 and the third reference voltage, and is used to absorb the charge at the moment when the first low-gain storage control transistor M10 is turned off. It should be noted that, in the reading module 400 of the present embodiment, only one of the third capacitor C3 and the fourth capacitor C4 may be included, or the third capacitor C3 and the fourth capacitor C4 may be included at the same time. Optionally, the reading module 400 includes a third capacitor C3 and a fourth capacitor C4, and the second reference voltage and the third reference voltage are both ground voltages.

For simplifying the circuit, as shown in fig. 2, fig. 2 is a schematic diagram of the pixel circuit shown in fig. 1 when the pixel circuit shares the first source follower transistor. The first high-gain source follower transistor M4 and the first low-gain source follower transistor M9 are the same source follower transistor, the gate terminal of the common source follower transistor is connected to the floating diffusion FD, the first connection terminal is connected to the variable voltage Vrsf, and the second connection terminal is connected to the first connection terminal of the first high-gain storage control transistor M5 and the first connection terminal of the first low-gain storage control transistor M10, respectively. Specifically, the high gain reading unit 401 and the low gain reading unit 402 correspond to the same or different column lines, so as to realize serial output or parallel output of signals respectively; for example, the high gain reading unit 401 and the low gain reading unit 402 correspond to different column lines to realize parallel output of signals (as shown in fig. 1 and 2); the high gain reading unit 401 and the low gain reading unit 402 correspond to the same column line to realize serial output of signals (as shown in fig. 3, fig. 3 is a schematic diagram of a serial output pixel circuit in the first embodiment of the present invention). In practical applications, the parallel output and the serial output can be selected according to specific requirements, which has no influence on the embodiment, and only the conduction time sequences of the high-gain row selection signal rsH and the low-gain row selection signal rsL need to be adjusted.

Referring to fig. 4 in conjunction with fig. 2, fig. 4 is a timing chart of signals in the pixel circuit shown in fig. 2, so as to describe the specific operation of the pixel circuit of this embodiment in detail.

Before time t0, a global reset phase (global reset); in this stage, the transfer transistor M3 is turned on, and at the same time, the reset transistor M1 and the gain control transistor M2 are in an on state, and the reset operation of the photodiode PD is completed by resetting the voltage of the floating diffusion FD by the reset transistor M1; after the reset operation is completed, the transfer transistor M3 is turned off, and global exposure starts.

At times t1 to t2, a precharge (pre-chg rst) phase is performed for the reset signal; in this stage, the reset transistor M1, the gain control transistor M2, the second high-gain memory control transistor M6, and the second low-gain memory control transistor M11 are all in an on state, the variable voltage Vrsf is changed from a high potential to a low potential, and at the same time, the first high-gain memory control transistor M5 and the first low-gain memory control transistor M10 are turned on, the left plate of the first capacitor C1 and the left plate of the second capacitor C2 are set to a low potential, and the right plate of the first capacitor C1 and the right plate of the second capacitor C2 are set to VDD. After the completion of the setting, the first high-gain memory control transistor M5 and the first low-gain memory control transistor M10 are turned off first, and then the variable voltage Vrsf is set to a high potential.

At time t2 to time t3, a reset voltage sampling phase (global sample LCG rst) of the global LCG; in this stage, the reset transistor M1 is turned off, i.e., reset is ended; then the first low-gain storage control transistor M10 is turned on, the low-gain reset voltage signal voltage Vrst_ lcg is stored on the left plate of the second capacitor C2 through the first source follower transistor M4, and at this time, the voltage difference of the capacitor plates of the second capacitor C2 is (VDD-Vrst_ lcg); after the voltage saving is completed, the first low gain memory control transistor M10 returns to the off state.

t3 to t4 phases, which are reset voltage sampling phases (global sample HCG rst) of the global HCG; in this stage, the second low-gain memory control transistor M11 is turned off, then the gain control transistor M2 is turned off, and then the first high-gain memory control transistor M5 is turned on, and the high-gain reset voltage signal vrst_ hcg is stored on the left plate of the first capacitor C1 through the first source follower transistor M4, where the voltage difference between the capacitor plates of the first capacitor C1 is (VDD-vrst_ hcg); after the voltage saving is completed, the first high gain memory control transistor M5 returns to the off state.

t4 to t5, a pixel voltage precharge phase (pre-chg sig); in this stage, the variable voltage Vrsf changes from the high potential to the low potential, and at the same time, the first high gain memory control transistor M5 and the first low gain memory control transistor M10 are turned on, setting the left plate of the first capacitor C1 and the left plate of the second capacitor C2 to the low potential.

t5 to t6, which is an HCG image voltage sampling stage (global sample HCG sig); in this stage, the transfer transistor M3 is turned on, the photodiode PD transfers the exposure charge to the floating diffusion FD, the voltage at this point is changed, then the first high-gain storage control transistor M5 is turned on, the source terminal of the first source follower transistor M4 is connected to the left plate of the first capacitor C1, and the high-gain image voltage signal vsig— hcg is sampled onto the left plate of the first capacitor C1; the second high gain memory control transistor M6 is in an off state, and the right plate of the first capacitor C1 is in a floating state, and at this time, in order to maintain the voltage difference between the left and right plates of the first capacitor C1, the voltage of the right plate of the first capacitor C1 is vsig— hcg + (VDD-vrst_ hcg).

t6 to t7, which are LCG image voltage sampling phases (global sample LCG sig); in this stage, the gain control transistor M2 is turned on, then the transfer transistor M3 is turned on, the photodiode PD transfers the exposure charge to the floating diffusion FD and the gain adjustment capacitor Cdcg to redistribute the charge, and finally the first low gain storage control transistor M10 is turned on, the source terminal of the first source follower transistor M4 is connected to the left plate of the second capacitor C2, and the low gain image voltage signal vlsig_ lcg is sampled onto the left plate of the second capacitor C2; the second low-gain memory control transistor M11 is in an off state, and the right plate of the second capacitor C2 is in a floating state, and at this time, in order to maintain the voltage difference between the left plate and the right plate of the second capacitor C2, the voltage of the right plate of the second capacitor C2 is vsig— lcg + (VDD-vrst_ lcg); after the sampling is completed, the first low-gain memory control transistor M10 returns to the off state, the reset transistor M1 returns to the on state, and the subsequent read operation is controlled by the high-gain row selection signal rsH and the low-gain row selection signal rsL (e.g., stages t9 to t 10).

In the whole process from t2 to t7, the global conversion operation is completed; by utilizing the characteristic of the capacitor storing charge, a high gain image voltage signal is stored on the first capacitor C1, a low gain image voltage signal is stored on the second capacitor C2, and the image voltage is read out row by the high gain row selection signal rsH and the low gain row selection signal rsL. In the reading stage, the signal on the capacitor plate is read first, and then a power supply signal VDD is read, and the difference is made between the signal and the power supply signal VDD, so that the required Vrst-Vsig can be obtained. Note that az in fig. 4 represents a clear signal of the readout circuit, clk represents a clock signal of the readout circuit, and clock on represents readout.

Example two

The embodiment provides a control method of a pixel circuit, which includes the following steps: providing the pixel circuit according to the first embodiment, global exposure is realized based on the pixel circuit, the voltage difference between the image signal and the reset signal in the high-gain transmission mode is obtained through the first capacitor, and the voltage difference between the image signal and the reset signal in the low-gain transmission mode is obtained through the second capacitor, so that the pixel circuit works in different gain transmission modes.

Specifically, in the process of implementing global exposure based on the pixel circuit shown in fig. 1 (the high-gain reading unit 401 and the low-gain reading unit 402 do not share a source follower transistor), the signal transmission manner may include: reset signal reset, low gain reset signal acquisition, high gain reset signal acquisition, image signal reset, high gain image signal acquisition and low gain image signal acquisition are sequentially performed, and may also include: resetting the reset signal, collecting the low-gain reset signal, collecting the high-gain reset signal, and simultaneously resetting the image signal of the low-gain reading unit, collecting the high-gain image signal, and simultaneously resetting the image signal of the low-gain reading unit and collecting the low-gain image signal.

In practical applications, the first high-gain source follower transistor M4 and the first low-gain source follower transistor M9 are connected to different variable voltages, such as the first high-gain source follower transistor M4 is connected to a high-level variable voltage, the first low-gain source follower transistor M9 is connected to a low-level variable voltage, so that the image signal of the low-gain reading unit is reset while the high-gain reset signal is collected, the first low-gain source follower transistor M9 is connected to a high-level variable voltage, and the first high-gain source follower transistor M4 is connected to a low-level variable voltage, thereby realizing the image signal reset of the high-gain reading unit while the low-gain image signal is collected. The second signal transmission mode (i.e., the signal transmission sequence is that the reset signal is reset, the low-gain reset signal is collected, the high-gain reset signal is collected, the image signal of the low-gain reading unit is reset, the high-gain image signal is collected, the image signal of the low-gain reading unit is reset, the low-gain image signal is collected) saves the time of one image signal reset compared with the first signal transmission mode, thereby saving the time of the pixel period, wherein the second signal transmission mode can be realized based on a circuit which does not share the first source following transistor.

Resetting the reset signal, and then carrying out low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and low-gain image signal acquisition on the reset transistor M1 to a first potential; when the first high-gain source follower transistor and the first low-gain source follower transistor are present, the potential of the first high-gain source follower transistor is the same and the potential of the first low-gain source follower transistor is the same in the reset signal reset process and the image signal reset process. Optionally, the first potential, the potential of the first high gain source follower transistor and the potential of the first low gain source follower transistor are all at or near ground potential. In the reset signal reset process and the image signal reset process, the potential of the first high-gain source follower transistor and the potential of the first low-gain source follower transistor are set at a sufficiently low level, so that the problem that the rear-end source follower transistor cannot be conducted due to the fact that the potential of the floating diffusion FD is reduced (potential reduction is caused by overlong exposure time) is avoided, and low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and low-gain image signal acquisition can be performed under the first potential, and power consumption is saved; moreover, the potential of the floating diffusion FD is less affected by the exposure time due to the design of the gain control transistor M2.

Specifically, in the process of implementing global exposure based on the pixel circuit shown in fig. 2 (the source follower transistor is shared by the high-gain reading unit 401 and the low-gain reading unit 402), the signal transmission manner includes: reset signal reset, low gain reset signal acquisition, high gain reset signal acquisition, image signal reset, high gain image signal acquisition and low gain image signal acquisition are sequentially performed.

Resetting the reset signal, and then carrying out low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and low-gain image signal acquisition on the reset transistor M1 to a first potential; in the reset signal reset process and the image signal reset process, the potential of the common source follower transistor is the same. Optionally, the first potential and the potential of the common source follower transistor are both at or near ground. In the reset signal reset process and the image signal reset process, the potential of the common source follower transistor is set at a low enough level, so that the problem that the rear source follower transistor cannot be conducted due to the fact that the potential of the floating diffusion FD is reduced (potential reduction is caused by overlong exposure time) is avoided, and the low-gain reset signal acquisition, the high-gain reset signal acquisition, the image signal reset, the high-gain image signal acquisition and the low-gain image signal acquisition can be performed at a first potential, so that power consumption is saved; moreover, the potential of the floating diffusion FD is less affected by the exposure time due to the design of the gain control transistor M2.

Specifically, the control method comprises the following steps: in the first high-gain transmission mode, the left plate of the first capacitor stores a high-gain reset voltage signal Vrst hcg, the right plate stores a first power voltage signal Vdd, and the voltage difference between the left plate and the right plate of the first capacitor is Vdd-Vrst hcg, so that in the second high-gain transmission mode, when the left plate of the first capacitor stores a high-gain image voltage signal Vsig hcg, the right plate stores a high-gain output voltage signal Vsig hcg+ (Vdd-Vrst hcg); in the first low-gain transmission mode, the left plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg, the right plate stores a first power voltage signal Vdd, and the voltage difference between the left plate and the right plate of the second capacitor is Vdd-Vrst lcg, so that when the left plate of the second capacitor stores a low-gain image voltage signal Vsig lcg in the second low-gain transmission mode, the right plate stores and outputs a low-gain voltage signal Vsig lcg+ (Vdd-Vrst lcg). It should be noted that, the specific control manner can be seen in the first embodiment, and will not be described herein.

More specifically, the readout process of the pixel circuit includes a first stage in which the pixel circuit outputs the voltage signal vsig+ (Vdd-Vrst) and a second stage in which the pixel circuit outputs the first power supply voltage signal Vdd. The voltage difference between the image voltage signal and the reset voltage signal, namely the pixel signal, under different gain transmission modes can be obtained by making a difference between the voltage signals output by the first stage and the second stage.

Specifically, the signal output modes of the high-gain reading unit and the low-gain reading unit include serial output or parallel output. In practical applications, serial output and parallel output can be selected according to specific requirements, which has no influence on the embodiment, and only the conduction time sequences of the high-gain row selection signal rsH and the low-gain row selection signal rsL need to be adjusted.

Example III

The present embodiment provides a CMOS image sensor including: at least one pixel circuit as in example one.

Specifically, the CMOS image sensor includes a plurality of pixels, which are arranged in rows and columns to form a pixel array, and the pixels correspond to the pixel circuits. In practical application, the pixels are in one-to-one correspondence with the pixel circuits, namely, each pixel is formed by the pixel circuits; of course, a plurality of pixels may also share the same reading module 400, which has no effect on the present embodiment.

Specifically, in an example, the CMOS image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module 300 is located in the first semiconductor substrate, and the reading module 400 is located in the second semiconductor substrate. In yet another example, the CMOS image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module 300 and the reading module 400 are located in the first semiconductor substrate, and the CMOS image sensor further includes a logic circuit located in the second semiconductor substrate. In yet another example, the CMOS image sensor includes a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate stacked, the photosensitive control module 300 is located in the first semiconductor substrate, the read module 400 is located in the second semiconductor substrate, and the CMOS image sensor further includes a logic circuit located in the third semiconductor substrate. It should be noted that, the electrical connection (bonding) between the substrates may be implemented by using an existing process based on a circuit, for example, using metal pads and interconnection lines or using TSV vias to implement electrical connection between transistor devices.

In summary, according to the pixel circuit, the CMOS image sensor and the control method, through the design of the gain control module and the reading module, the dynamic range of the CMOS image sensor is effectively improved by adopting a double conversion gain technology; and a larger capacitor is used for a high-intensity illumination area, the stored charge is improved, the gain is reduced to improve the dynamic range, a smaller capacitor is used for a low-intensity illumination area, the gain is improved, and high sensitivity is realized. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A pixel circuit, the pixel circuit comprising: the device comprises a reset module, a gain control module, a photosensitive control module and a reading module, wherein,

2. The pixel circuit of claim 1, wherein the high gain transmission mode comprises a first high gain transmission mode in which a left plate of the first capacitor stores a high gain reset voltage signal Vrst hcg, a right plate stores a first power supply voltage signal Vdd, and a second high gain transmission mode in which a left plate of the first capacitor stores a high gain image voltage signal vsighcg, a right plate stores a high gain output voltage signal vsighcg+ (Vdd-Vrst hcg); and/or the number of the groups of groups,

the low gain transmission mode includes a first low gain transmission mode in which a left plate of the second capacitor stores a low gain reset voltage signal Vrst lcg, a right plate stores a first power voltage signal Vdd, and a second low gain transmission mode in which a left plate of the second capacitor stores a low gain image voltage signal Vsig lcg, and a right plate stores and outputs a low gain voltage signal Vsig lcg+ (Vdd-Vrst lcg).

3. The pixel circuit of claim 1, wherein the high gain read unit further comprises at least: a first high-gain source follower transistor, a first high-gain memory control transistor, a second high-gain source follower transistor, and a first row select transistor;

The gate end of the first high-gain source follower transistor is connected to the floating diffusion point, the first connecting end is connected to a first variable voltage, and the second connecting end is connected to the first connecting end of the first high-gain storage control transistor; the gate end of the first high-gain storage control transistor is connected with a first high-gain storage control signal, and the second connecting end of the first high-gain storage control transistor is connected with the left polar plate of the first capacitor; the right polar plate of the first capacitor is connected with the second connecting end of the second high-gain storage control transistor and the gate end of the second high-gain source follower transistor; the gate end of the second high-gain storage control transistor is connected with a second high-gain storage control signal, and the first connecting end is connected with a first power supply voltage; the first connecting end of the second high-gain source follower transistor is connected with a second power supply voltage, and the second connecting end is connected with the first connecting end of the first row selection transistor; the gate end of the first row selection transistor is connected with a high-gain row selection signal, and the second connection end is used as the output end of the high-gain reading unit;

the low gain reading unit further includes at least: a first low-gain source follower transistor, a first low-gain memory control transistor, a second low-gain source follower transistor, and a second row select transistor;

The gate end of the first low-gain source follower transistor is connected to the floating diffusion point, the first connecting end is connected to a second variable voltage, and the second connecting end is connected to the first connecting end of the first low-gain storage control transistor; the gate end of the first low-gain storage control transistor is connected with a first low-gain storage control signal, and the second connecting end of the first low-gain storage control transistor is connected with the left polar plate of the second capacitor; the right polar plate of the second capacitor is connected with the second connecting end of the second low-gain storage control transistor and the gate end of the second low-gain source follower transistor; the gate end of the second low-gain storage control transistor is connected with a second low-gain storage control signal, and the first connecting end is connected with a third power supply voltage; the first connecting end of the second low-gain source follower transistor is connected with a fourth power supply voltage, and the second connecting end of the second low-gain source follower transistor is connected with the first connecting end of the second row selection transistor; and the gate end of the second row selection transistor is connected with a low-gain row selection signal, and the second connection end is used as the output end of the low-gain reading unit.

4. A pixel circuit according to claim 3, wherein the first high-gain source follower transistor and the first low-gain source follower transistor are the same source follower transistor, a gate terminal of the common source follower transistor is connected to the floating diffusion point, a first connection terminal is connected to a variable voltage, and a second connection terminal is connected to the first connection terminal of the first high-gain storage control transistor and the first connection terminal of the first low-gain storage control transistor, respectively.

5. The pixel circuit according to claim 3 or 4, wherein the high-gain reading unit includes a third capacitor connected between the second connection terminal of the first high-gain storage control transistor and a second reference voltage; and/or the low gain reading unit comprises a fourth capacitor connected between the second connection terminal of the first low gain storage control transistor and a third reference voltage.

6. The pixel circuit of claim 1, wherein the gain control module comprises: the gain control transistor and the gain adjustment capacitor, wherein the gate end of the gain control transistor is connected with the gain control signal, the first connecting end is connected with the second connecting end of the reset transistor, the gain control transistor is connected with the fourth reference voltage through the gain adjustment capacitor, and the second connecting end is connected to the floating diffusion point.

7. The pixel circuit according to claim 6, wherein the gain adjustment capacitance is a parasitic capacitance of the reset transistor to ground at the gain control transistor connection point; alternatively, the gain adjustment capacitance is a device capacitance.

8. The pixel circuit of claim 1, wherein the photosensitive control module comprises: the output end of the photoelectric conversion element is connected with the first connecting end of the transmission transistor, and the other end of the photoelectric conversion element is connected with the first reference voltage; the gate end of the transmission transistor is connected with the transmission control signal, and the second connecting end is connected to the floating diffusion point.

9. The pixel circuit according to claim 1, wherein the high gain read unit and the low gain read unit correspond to the same or different column lines to achieve serial output or parallel output of signals, respectively.

10. A method for controlling a pixel circuit, comprising the steps of:

providing a pixel circuit according to any one of claims 1-9; and realizing global exposure based on the pixel circuit, acquiring the voltage difference between the image signal and the reset signal in the high-gain transmission mode through the first capacitor, and acquiring the voltage difference between the image signal and the reset signal in the low-gain transmission mode through the second capacitor so as to enable the pixel circuit to work in different gain transmission modes.

11. The control method of the pixel circuit according to claim 10, characterized in that the control method comprises:

in a first high-gain transmission mode, the left plate of the first capacitor stores a high-gain reset voltage signal Vrst hcg, the right plate stores a first power voltage signal Vdd, and the voltage difference between the left plate and the right plate of the first capacitor is Vdd-Vrst hcg, so that in a second high-gain transmission mode, when the left plate of the first capacitor stores a high-gain image voltage signal Vsig hcg, the right plate stores a high-gain output voltage signal Vsig hcg+ (Vdd-Vrst hcg);

In the first low-gain transmission mode, the left plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg, the right plate stores a first power voltage signal Vdd, and the voltage difference between the left plate and the right plate of the second capacitor is Vdd-Vrst lcg, so that when the left plate of the second capacitor stores the low-gain image voltage signal Vsiglcg in the second low-gain transmission mode, the right plate stores and outputs a low-gain voltage signal vsiglcg+ (Vdd-Vrst lcg).

12. The method according to claim 11, wherein in the process of implementing global exposure based on the pixel circuit, the signal transmission manner includes:

reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and low-gain image signal acquisition are sequentially carried out; or,

the signal transmission mode comprises the following steps: resetting the reset signal, collecting the low-gain reset signal, collecting the high-gain reset signal, and simultaneously resetting the image signal of the low-gain reading unit, collecting the high-gain image signal, and simultaneously resetting the image signal of the low-gain reading unit and collecting the low-gain image signal.

13. A control method of a pixel circuit according to claim 11, characterized in that the readout process of the pixel circuit comprises a first phase in which the pixel circuit outputs an output voltage signal vsig+ (Vdd-Vrst) and a second phase in which the pixel circuit outputs a first power supply voltage signal Vdd.

14. The method according to claim 10, wherein the signal output modes of the high gain reading unit and the low gain reading unit include serial output or parallel output.

15. The method according to any one of claims 10 to 14, wherein the reset transistor is reset to a first potential after reset signal reset, and low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition are performed at the first potential; and/or when the first high-gain source follower transistor and the first low-gain source follower transistor are present or are shared, the potential of the first high-gain source follower transistor is the same and the potential of the first low-gain source follower transistor is the same in the reset signal reset process and the image signal reset process.

16. A CMOS image sensor, the CMOS image sensor comprising: a pixel circuit as claimed in any one of claims 1 to 9.

17. The image sensor of claim 16, wherein the image sensor comprises a first semiconductor substrate and a second semiconductor substrate arranged in a stack, the photosensitive control module is located within the first semiconductor substrate, and the read module is located within the second semiconductor substrate; or the image sensor comprises a first semiconductor substrate, a second semiconductor substrate and a third semiconductor substrate which are stacked, wherein the photosensitive control module is positioned in the first semiconductor substrate, the reading module is positioned in the second semiconductor substrate, and the image sensor further comprises a logic circuit which is positioned in the third semiconductor substrate; or, the image sensor comprises a first semiconductor substrate and a second semiconductor substrate which are stacked, the photosensitive control module and the reading module are positioned in the first semiconductor substrate, and the image sensor further comprises a logic circuit which is positioned in the second semiconductor substrate.