CN116095521A - Pixel circuit, CMOS image sensor and method for improving dynamic range of CMOS image sensor - Google Patents
Pixel circuit, CMOS image sensor and method for improving dynamic range of CMOS image sensor Download PDFInfo
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Abstract
The invention provides a pixel circuit, a CMOS image sensor and a method for improving dynamic range thereof, wherein the pixel circuit comprises a photoelectric conversion element, a transmission transistor, a storage capacitor and a gain switching module, wherein the output end of the photoelectric conversion element is connected with the first end of the storage capacitor through the transmission transistor, and the other end of the photoelectric conversion element is connected with a second reference potential; the second end of the storage capacitor is connected with a first reference potential, the gate end of the transmission transistor is connected with a transmission control signal, and the gain switching module is connected between the first end of the storage capacitor and a third reference potential and is used for adjusting the equivalent capacitance value of the storage capacitor according to the predicted light intensity so as to realize switching of different transmission gain modes. The pixel circuit, the CMOS image sensor and the method for improving the dynamic range solve the problem that the conventional CMOS image sensor cannot realize the high dynamic range.
Description
Technical Field
The present invention relates to the field of CMOS image sensors, and more particularly, to a pixel circuit, a CMOS image sensor, and a method for improving dynamic range thereof.
Background
The dynamic range (DynamicRange) is one of the most important parameters of the image sensor, and determines the range of the brightness intensity distribution from the darkest shadow portion to the brightest highlight portion that the image sensor can accept, that is, the details, levels and characteristics of the captured image.
Fig. 1 shows a pixel circuit comprising: a photodiode PD, a transfer transistor M1, a reset transistor M2, a source follower transistor M3, and a row select transistor M4; wherein, the positive electrode of the photodiode PD is grounded, and the negative electrode is connected with the first connection terminal of the transmission transistor M1; the gate end of the transmission transistor M1 is connected with a transmission control signal tx, and the second connection end of the transmission transistor M is connected to a floating diffusion point FD; the gate end of the reset transistor M2 is connected with a reset control signal rst, the first connecting end is connected with a working voltage PIXVDD, and the second connecting end is connected to the floating diffusion FD; the gate end of the source following transistor M3 is connected to the floating diffusion FD, the first connection end is connected to the working voltage PIXVDD, and the second connection end is connected to the first connection end of the row selection transistor M4; the gate terminal of the row selection transistor M4 is connected to a row selection signal rowsel, and the second connection terminal reads out a pixel signal.
In the pixel circuit shown in fig. 1, since the charge storage capacity of the floating diffusion FD is fixed, the transfer gain (CG) is fixed when the pixel signal is quantized, and thus a high dynamic range cannot be realized. In view of this, how to achieve a high dynamic range of a CMOS image sensor is a technical problem that those skilled in the art are urgent to solve.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a pixel circuit, a CMOS image sensor and a method for improving dynamic range thereof, which are used for solving the problem that the dynamic range of the existing CMOS image sensor is low due to fixed transmission gain.
To achieve the above and other related objects, the present invention provides a pixel circuit including: photoelectric conversion element, transmission transistor, storage capacitor and gain switching module, wherein,
the first end of the storage capacitor is connected with the output end of the photoelectric conversion element through the transmission transistor, the second end of the storage capacitor is connected with a first reference potential, the gate end of the transmission transistor is connected with a transmission control signal, and the other end of the photoelectric conversion element is connected with a second reference potential;
the gain switching module is connected between the first end of the storage capacitor and the third reference potential and is used for adjusting the equivalent capacitance value of the storage capacitor according to the predicted light intensity so as to realize switching of different transmission gain modes.
Optionally, the pixel circuit further includes: and the pixel reading module is connected with the first end of the storage capacitor and used for reading out pixel signals.
Optionally, the pixel readout module includes: a reset transistor, a first source follower transistor, a first memory transistor, a first capacitor, a second memory transistor, a second capacitor, a second source follower transistor, and a row select transistor, wherein,
the gate end of the reset transistor is connected with a reset control signal, the first connecting end is connected with a first working voltage, and the second connecting end is connected with the first end of the storage capacitor;
the gate end of the first source following transistor is connected with the first end of the storage capacitor, the first connecting end is connected with variable voltage, and the second connecting end is connected with the first connecting end of the first storage transistor;
the gate end of the first storage transistor is connected with a first storage control signal, the second connection end of the first storage transistor is connected with the first connection end of the second storage transistor, and the second connection end of the first storage transistor is connected with a fourth reference potential through the first capacitor;
the gate end of the second storage transistor is connected with a second storage control signal, and the second connection end is connected with the gate end of the second source follower transistor and is connected with a fifth reference potential through the second capacitor;
the first connecting end of the second source following transistor is connected with a second working voltage, and the second connecting end of the second source following transistor is connected with the first connecting end of the row selecting transistor;
the gate end of the row selection transistor is connected with a row selection control signal, and the second connection end generates the pixel signal.
Optionally, the pixel readout module includes: a reset transistor, a first source follower transistor, a first memory transistor, a first capacitor, a second memory transistor, a second capacitor and a second source follower transistor, wherein,
the gate end of the reset transistor is connected with a reset control signal, the first connecting end is connected with a first variable voltage, and the second connecting end is connected with the first end of the storage capacitor;
the gate end of the first source following transistor is connected with the first end of the storage capacitor, the first connecting end is connected with the second variable voltage, and the second connecting end is connected with the first connecting end of the first storage transistor;
the gate end of the first storage transistor is connected with a first storage control signal, the second connection end of the first storage transistor is connected with the first connection end of the second storage transistor, and the second connection end of the first storage transistor is connected with a sixth reference potential through the first capacitor;
the gate end of the second storage transistor is connected with a second storage control signal, and the second connection end is connected with the gate end of the second source follower transistor and is connected with a seventh reference potential through the second capacitor;
the first connecting end of the second source following transistor is connected to the working voltage, and the second connecting end of the second source following transistor generates the pixel signal.
Optionally, the gain switching module includes: the device comprises a main control transistor and an adjusting capacitor, wherein the gate end of the main control transistor is connected with a switching control signal related to the predicted light intensity, the first connecting end is connected with the first end of the storage capacitor, and the second connecting end is connected with the third reference potential through the adjusting capacitor.
Optionally, the gain switching module further includes: the gate end of the auxiliary control transistor is connected with an auxiliary control signal, the first connecting end is connected with the switching control signal related to the predicted light intensity, and the second connecting end is connected with the gate end of the main control transistor.
The present invention also provides a CMOS image sensor including: at least one pixel circuit as claimed in any one of the preceding claims.
Optionally, the CMOS image sensor includes a plurality of pixels, where the pixels are arranged in rows and columns to form a pixel array, and the pixels correspond to the pixel circuits, where when the pixel circuits include the auxiliary control transistors, the first connection terminals of the auxiliary control transistors in a same column access the corresponding switching control signals related to the predicted light intensity based on a same control line.
Optionally, the image sensor includes a first substrate and a second substrate stacked, wherein the storage capacitor and the gain switching module are prepared on the same substrate; and/or the image sensor comprises a third substrate, and the peripheral logic control circuit is prepared on the third substrate.
Optionally, the photoelectric conversion element, the transmission transistor, the storage capacitor and the gain switching module are prepared on the first substrate; the readout circuitry is fabricated on the second substrate; alternatively, the photoelectric conversion element and the transfer transistor are prepared on the first substrate; the storage capacitor, the gain switching module and the readout circuit are prepared on the second substrate.
The invention also provides a method for improving the dynamic range of a CMOS image sensor by adopting the pixel circuit, which comprises the following steps:
predicting the light intensity corresponding to the pixel signal of the next frame based on the historical pixel signal;
when the light intensity corresponding to the pixel signal of the next frame is the first light intensity, adopting an equivalent capacitance value of the storage capacitor to make the CMOS image sensor work in a high transmission gain mode;
when the light intensity corresponding to the pixel signal of the next frame is the second light intensity, adopting an equivalent capacitance value of the storage capacitor with larger value to enable the CMOS image sensor to work in a low transmission gain mode;
the first light intensity is smaller than a preset light intensity threshold value, and the second light intensity is larger than the preset light intensity threshold value.
Optionally, the method comprises:
after the pixel signals of the nth row of the kth frame are read, generating a switching control signal of the nth row of the (k+1) th frame;
and opening an auxiliary control signal of the (k+1) th row of the frame, writing the switching control signal into a grid electrode of a main control transistor of the (k+1) th row of the frame, wherein k is greater than or equal to 1, and n is greater than or equal to 1.
Optionally, after generating the switching control signal of the nth row of the k+1th frame, the switching control signal is stored in a register.
The pixel signal reading method of the (n+1) th row of the k frame optionally comprises the following steps:
the (k+1) th row of the k+1 th frame is read during or after writing the (k+1) th row of the switching control signal.
As described above, according to the pixel circuit, the CMOS image sensor and the method for improving the dynamic range thereof, the pixel circuit can work in different transmission gain modes according to the predicted light intensity through the design of the gain switching module, and the pixel signal can be ensured to be normally transmitted under the small light intensity and the large light intensity through the switching of the low transmission gain mode and the high transmission gain mode, so that the high dynamic range is realized.
Drawings
Fig. 1 is a circuit diagram of a conventional pixel circuit.
Fig. 2 shows a circuit diagram of a pixel circuit according to the invention.
Fig. 3 shows another circuit diagram of the pixel circuit of the present invention.
Fig. 4 is a layout diagram of control signal lines in the gain switching module according to the present invention.
FIG. 5 is a timing diagram of related signals in the pixel circuit shown in FIG. 2.
Fig. 6 (a) shows one way of device division for a stacked design image sensor of the present invention.
Fig. 6 (b) shows another way of device division for a stacked design image sensor of the present invention.
Description of element reference numerals
101. Gain switching module
102. Pixel readout module
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to fig. 6 (b). It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 2 and 3, the present embodiment provides a pixel circuit including: the photoelectric conversion element, the transfer transistor M1, the storage capacitor Cfd, and the gain switching module 101.
The output end of the photoelectric conversion element is connected with the first connection end of the transmission transistor M1, and the other end of the photoelectric conversion element is connected with a second reference potential for generating exposure charges according to the photoelectric effect.
As an example, the photoelectric conversion element is implemented by a photodiode PD, where an anode of the photodiode PD is connected to the second reference potential, and a cathode of the photodiode PD is connected to the first connection terminal of the transfer transistor M1. Optionally, the second reference potential is ground potential.
The first connection end of the transmission transistor M1 is connected with the output end of the photoelectric conversion element, the second connection end of the transmission transistor M1 is connected with the first end of the storage capacitor Cfd, and the gate end of the transmission transistor M is connected with a transmission control signal tx for transferring and outputting exposure charges generated by the photoelectric conversion element according to the transmission control signal tx. Optionally, the transmission transistor M1 is an NMOS transistor, and the first connection terminal is a source terminal, and the second connection terminal is a drain terminal. In this embodiment, when the transfer control signal tx is at a high level, the transfer transistor M1 is turned on, and transfers and outputs the exposure charge generated by the photoelectric conversion element.
The first end of the storage capacitor Cfd is connected to the second connection end of the transmission transistor M1, and the second end of the storage capacitor Cfd is connected to a first reference potential and is used for storing the exposure charge transferred and output by the transmission transistor M1. Optionally, the first reference potential is ground potential. In practical applications, the storage capacitor Cfd may be a parasitic capacitor of the second connection end of the transfer transistor M1 to ground, or may be an external capacitor device, which has no influence on the embodiment.
The gain switching module 101 is connected between the first end of the storage capacitor Cfd and a third reference potential, and is configured to adjust an equivalent capacitance value of the storage capacitor Cfd according to a predicted light intensity, so as to implement switching of different transmission gain modes.
As an example, the gain switching module 101 includes: the device comprises a main control transistor M2 and an adjusting capacitor Cdcg, wherein a gate end of the main control transistor M2 is connected with a switching control signal ycamp related to the predicted light intensity, a first connecting end is connected with a first end of a storage capacitor Cfd, and a second connecting end is connected with the third reference potential through the adjusting capacitor Cdcg. Optionally, the third reference potential is ground potential, the master control transistor M2 is an NMOS transistor, and the first connection terminal is a drain terminal, and the second connection terminal is a source terminal. In practical application, the adjustment capacitance Cdcg may be a parasitic capacitance of the second connection end of the main control transistor M2 to ground, or may be an external capacitive device, which has no influence on the embodiment.
In this embodiment, the main control transistor M2 is controlled by a switching control signal ycamp related to the predicted light intensity, and when the light intensity is small, the switching control signal ycamp controls the main control transistor M2 to be turned off, and the capacitance value of the storage capacitor Cfd is the equivalent capacitance value (smaller equivalent capacitance value of the storage capacitor), so that the pixel circuit works in the high transmission gain mode, and when the light intensity is large, the switching control signal ycamp controls the main control transistor M2 to be turned on, and the equivalent capacitance value of the storage capacitor Cfd (larger equivalent capacitance value of the storage capacitor) is increased by the parallel adjustment capacitor Cdcg, so that the pixel circuit works in the low transmission gain mode, and the pixel signal is ensured to be normally transmitted under both the low light intensity and the large light intensity, so as to realize the high dynamic range. In practical application, the prediction of the light intensity and thus the generation of the switching control signal ycamp can be realized by an image processing module (e.g., ISP) at the back end, and the switching control signal ycamp can be generated according to the pixel signal output by the pixel circuit, and is also used for predicting the light intensity corresponding to the pixel signal of the next frame according to the historical pixel signal output by the pixel circuit, and generating the switching control signal ycamp related to the predicted light intensity; if the light intensity corresponding to the pixel signal of the previous frame or the previous frames is the large light intensity, the light intensity corresponding to the pixel signal of the next frame is predicted to be the large light intensity, and a high-level switching control signal ycamp is generated at the moment, otherwise, if the light intensity corresponding to the pixel signal of the previous frame or the previous frames is the small light intensity, the light intensity corresponding to the pixel signal of the next frame is predicted to be the small light intensity, and a low-level switching control signal ycamp is generated at the moment. In one embodiment, the image processing module may include a processing circuit, where the pixel signal of the previous frame or frames is compared with a set threshold, for example, by a comparator, and a corresponding value of ycamp is obtained based on the comparison result. In addition, peripheral logic control circuitry may also be used to generate the auxiliary control signal xcamp.
Further, the gain switching module 101 further includes: the gate end of the auxiliary control transistor M3 is connected with an auxiliary control signal xcamp, the first connecting end is connected with a switching control signal ycamp related to the predicted light intensity, and the second connecting end is connected with the gate end of the main control transistor M2. Optionally, the auxiliary control transistor M3 is an NMOS transistor, and the first connection terminal is a drain terminal, and the second connection terminal is a source terminal. It should be noted that, when the gain switching module 101 further includes the auxiliary control transistor M3, that is, when the gain switching module 101 is formed by the main control transistor M2, the auxiliary control transistor M3, and the adjustment capacitor Cdcg, the gate terminal of the main control transistor M2 is not connected to the switching control signal ycamp related to the predicted light intensity, and is only connected to the second connection terminal of the auxiliary control transistor M3.
In this embodiment, the auxiliary control transistor M3 is controlled by an auxiliary control signal xcamp, and when the auxiliary control transistor M3 is turned on, a switching control signal ycamp related to the predicted light intensity is applied to the gate terminal of the main control transistor M2, so as to control the main control transistor M2. According to the embodiment, through the design of the auxiliary control transistor M3, the first connection ends of the auxiliary control transistors M3 in the same column in the pixel array can be connected into a switching control signal ycamp related to the predicted light intensity through the same control line, so that the number of control lines is greatly reduced; for the pixel array formed by the pixel circuit according to the present embodiment, the signal line layout of the switching control signal ycamp and the auxiliary control signal xcamp related to the predicted light intensity is shown in fig. 4, and the corresponding timing is shown in fig. 5.
Specifically, as shown in fig. 2 and 3, the pixel circuit further includes: and the pixel readout module 102 is connected with the first end of the storage capacitor Cfd and is used for reading out pixel signals.
As an example, the pixel readout module 102 includes: the circuit comprises a reset transistor M4, a first source following transistor M5, a first storage transistor M6, a first capacitor Csig, a second storage transistor M7, a second capacitor Crst, a second source following transistor M8 and a row selection transistor M9, wherein a gate end of the reset transistor M4 is connected with a reset control signal rst, a first connecting end is connected with a first working voltage, and a second connecting end is connected with a first end of a storage capacitor Cfd; the gate end of the first source follower transistor M5 is connected with the first end of the storage capacitor Cfd, the first connection end is connected with the variable voltage VRSF, and the second connection end is connected with the first connection end of the first storage transistor M6; the gate end of the first memory transistor M6 is connected to a first memory control signal gs_sig, and the second connection end is connected to the first connection end of the second memory transistor M7 and is connected to a fourth reference potential through the first capacitor Csig; the gate end of the second storage transistor M7 is connected with a second storage control signal gs_rst, and the second connection end is connected with the gate end of the second source follower transistor M8 and is connected with a fifth reference potential through the second capacitor Crst; the first connection end of the second source following transistor M8 is connected with a second working voltage, and the second connection end is connected with the first connection end of the row selection transistor M9; the gate terminal of the row selection transistor M9 is connected to the row selection control signal gs_sel, and the second connection terminal generates the pixel signal pixout (as shown in fig. 2). Optionally, the reset transistor M4, the first source follower transistor M5, the first storage transistor M6, the second storage transistor M7, the second source follower transistor M8, and the row select transistor M9 are NMOS transistors, wherein a first connection terminal is a drain terminal, a second connection terminal is a source terminal, the first operating voltage and the second operating voltage are both the operating voltage PIXVDD of the pixel circuit, and the fourth reference potential and the fifth reference potential are both ground potentials.
Of course, the pixel readout module 102 may be implemented in other manners, such as the pixel readout module 102 includes: the circuit comprises a reset transistor M4, a first source following transistor M5, a first storage transistor M6, a first capacitor Csig, a second storage transistor M7, a second capacitor Crst and a second source following transistor M8, wherein the gate of the reset transistor M4 is connected with a reset control signal rst, a first connecting end is connected with a first variable voltage VRSF1, and a second connecting end is connected with a first end of the storage capacitor Cfd; the gate end of the first source follower transistor M5 is connected to the first end of the storage capacitor Cfd, the first connection end is connected to the second variable voltage VRSF2, and the second connection end is connected to the first connection end of the first storage transistor M6; the gate terminal of the first memory transistor M6 is connected to a first memory control signal gs_sig, and the second connection terminal is connected to the first connection terminal of the second memory transistor M7 and is connected to a sixth reference potential through the first capacitor Csig; the gate terminal of the second memory transistor M7 is connected to the second memory control signal gs_rst, and the second connection terminal is connected to the gate terminal of the second source follower transistor M8 and is connected to the seventh reference potential through the second capacitor Csig; the first connection terminal of the second source follower transistor M8 is connected to the operating voltage PIXVDD, and the second connection terminal generates the pixel signal pixout (as shown in fig. 4). Optionally, the reset transistor M4, the first source follower transistor M5, the first memory transistor M6, the second memory transistor M7, and the second source follower transistor M8 are all NMOS transistors, wherein the first connection terminal is a drain terminal, the second connection terminal is a source terminal, and the sixth reference potential and the seventh reference potential are both ground potentials.
Referring to fig. 5 in conjunction with fig. 2 and fig. 4, a transmission gain mode switching process of the pixel circuit according to the present embodiment is described in detail; here, the pixel < m, n > is taken as an example.
1. The reset transistor M4 and the transfer transistor M1 are turned on to clear the charge in the photoelectric conversion element, and perform global reset (pre-chg);
2. the transfer transistor M1 is turned off, and global exposure (global exposure) is performed;
3. the reset transistor M4 is turned on, the variable voltage VRSF is low level, the first memory transistor M6 and the second memory transistor M7 are turned on, the first capacitor Csig and the second capacitor Crst are pulled to low level, and reset signal precharge (pre-chg rst) is carried out;
4. the reset transistor M4 is turned off, the first source follower transistor M5 is turned on, the variable voltage VRSF is high level, the first storage transistor M6 and the second storage transistor M7 are turned on, and the first capacitor Csig and the second capacitor Crst respectively store 1/2Vrst and perform reset signal sampling (global sample rst);
5. the first source follower transistor M5 is turned on, the variable voltage VRSF is at a low level, the first memory transistor M6 is turned on, the first capacitor Csig is pulled to a low level, and the image signal precharge (pre-chg sig) is performed;
6. the transfer transistor M1 is turned on, the photoelectric conversion element transfers exposure charges to the storage capacitor Cfd, and exposure is finished; the transfer transistor M1 is turned off, the first storage transistor M6 is turned on, the exposure charge in the storage capacitor Cfd is transferred to the first capacitor Csig, vsig is stored in the first capacitor Csig, and image signal sampling is performed (golbal sample sig);
7. the row select transistor M9 is turned on and reads 1/2Vrst; the second memory transistor M7 is turned on, and 1/2vsig+1/4Vrst is read (read/identification) for pixel readout.
8. After the pixel is read out, predicting the light intensity corresponding to the pixel < m, n > of the next frame according to the historical pixel, so as to obtain a switching control signal related to the predicted light intensity and write in the y ramp < m >; if the light intensity corresponding to the pixel of the next frame is predicted to be small, writing a low level in the yramp < m >, otherwise, writing a high level in the yramp < m >;
the auxiliary control signal written in xramp < n > is used for controlling the auxiliary control transistor M3 to be conducted, the switching control signal written in yramp < M > is written in the grid electrode of the main control transistor M2, so that the main control transistor M2 is controlled to be conducted or turned off, and the transmission gain mode for controlling the pixels < M, n > of the next frame is realized.
Accordingly, the present embodiment also provides a CMOS image sensor, including: at least one pixel circuit as described above.
Specifically, the CMOS image sensor includes a plurality of pixels, where the pixels are arranged in rows and columns to form a pixel array, and the pixels correspond to the pixel circuits, where when the pixel circuits include the auxiliary control transistors M3, the first connection terminals of the auxiliary control transistors M3 in a same column are connected to the switching control signals related to the corresponding predicted light intensity based on a same control line. For example, each column of pixels may be a control line, which is connected to one end of the column of auxiliary transistors, and further, the control line may be a same register, so that pixels of each row may be multiplexed based on the above design, for example, writing and reading of next frame switching control signals of n and n+1 rows are realized through the same control line and register.
Specifically, the CMOS image sensor further includes an image processing module (e.g., ISP) that may include an image generation circuit for receiving pixel signals generated by the pixel circuits and generating an image based on the pixel signals. In practical applications, the image processing module is configured to predict the light intensity and generate the switching control signal ycamp according to the light intensity, and may further write the switching control signal ycamp into the corresponding transistor through the peripheral logic control circuit. In addition, other control signals (such as a transmission control signal tx, a reset control signal rst, a first storage control signal gs_sig, a second storage control signal gs_rst, a row selection control signal gs_sel, etc.), an auxiliary control signal xcamp, etc. related to the pixel circuit may be implemented by a peripheral logic control circuit.
As an example, referring to fig. 6 (a) and 6 (b), the image sensor includes a first substrate and a second substrate stacked, wherein the storage capacitor and the gain switching module are prepared on the same substrate. In this example, the image sensor is arranged in a stacked structure, and the storage capacitor and the gain switching module are fabricated on the same substrate, which is beneficial to improving the overall performance of the image sensor and improving the switching performance of the conversion gain mode and realizing the gain effect.
In one embodiment, as shown in fig. 6 (a), the photoelectric conversion element and the transfer transistor on one side of a chain line are prepared on the first substrate; the storage capacitor, the gain switching module and the readout circuit which are positioned on the other side of the dot-dash line are prepared on the second substrate, so that the pixel photosensitive effect can be further improved. In another embodiment, as shown in fig. 6 (b), the photoelectric conversion element, the transfer transistor, the storage capacitor, and the gain switching module, which are located on one side of a chain line, are prepared on the first substrate; the readout circuitry is provided on the other side of the dash-dot line on the second substrate. In addition, in a further example, the peripheral logic circuit may also be fabricated on the third substrate, implementing a three-substrate stacked structure, thereby facilitating efficient implementation of high dynamic range effects in globally exposed circuits. It should be further noted that, the electrical connection (bonding) between the substrates may be implemented by using existing technologies based on the circuit, for example, using metal pads and interconnection lines or using TSV through holes to implement electrical connection between transistor devices.
Accordingly, the present embodiment also provides a method for improving the dynamic range of a CMOS image sensor using the pixel circuit as described above, the method comprising:
1) Predicting the light intensity corresponding to the pixel signal of the next frame based on the historical pixel signal; if the light intensity corresponding to the pixel signal of the previous frame or the previous frames is the first light intensity, the light intensity corresponding to the pixel signal of the next frame is predicted to be the first light intensity, otherwise, if the light intensity corresponding to the pixel signal of the previous frame or the previous frames is the second light intensity, the light intensity corresponding to the pixel signal of the next frame is predicted to be the second light intensity, wherein the first light intensity is smaller than a preset light intensity threshold value, and the second light intensity is larger than the preset light intensity threshold value; in practical applications, the first light intensity smaller than the preset light intensity threshold is set to be a small light intensity, and the second light intensity larger than the preset light intensity threshold is set to be a large light intensity, for example, the preset light intensity threshold may be selected from the pixel signals 240.
2) When the light intensity corresponding to the pixel signal of the next frame is the first light intensity, adopting an equivalent capacitance value of the storage capacitor to make the CMOS image sensor work in a high transmission gain mode; when the light intensity corresponding to the pixel signal of the next frame is the second light intensity, the equivalent capacitance value of the storage capacitor is larger, so that the CMOS image sensor works in a low transmission gain mode.
Specifically, the implementation can be achieved by controlling, by the master control transistor M2, whether the adjustment capacitor Cdcg is incorporated into both ends of the storage capacitor Cfd, for example, when the light intensity corresponding to the pixel signal of the next frame is predicted to be the second light intensity, the master control transistor M2 is controlled to be turned on by the switching control signal yramp, so that the adjustment capacitor Cdcg is incorporated into both ends of the storage capacitor Cfd, and thus the equivalent capacitance value of the storage capacitor Cfd is increased, and the CMOS image sensor is operated in the low transmission gain mode by adopting a larger equivalent capacitance value of the storage capacitor; otherwise, when the light intensity corresponding to the pixel signal of the next frame is predicted to be the first light intensity, the main control transistor M2 is controlled to be turned off through the switching control signal yramp, so that the regulating capacitor Cdcg is not combined with two ends of the storage capacitor Cfd, and the CMOS image sensor is enabled to work in a high transmission gain mode by adopting an equivalent capacitance value of the smaller storage capacitor; through switching between the low transmission gain mode and the high transmission gain mode, the normal transmission of pixel signals under the conditions of small light intensity and large light intensity is ensured, and therefore a high dynamic range is realized.
As an example, the method of controlling the master transistor M2 by the switching control signal includes: after the pixel signals of the nth row of the kth frame are read, generating a switching control signal yramp of the nth row of the (k+1) th frame; opening an auxiliary control signal xcamp of the (k+1) th row of the frame to enable the auxiliary control transistor M3 to be conducted, and writing the switching control signal yramp into a grid electrode of a main control transistor M2 of the (k+1) th row of the frame; wherein k is greater than or equal to 1, and n is greater than or equal to 1.
In one embodiment, k is 1, which may be a selection of a gain mode for predicting a subsequent frame based on a pixel signal of a previous frame, in other embodiments, k may be 2, which may be a selection of a gain mode for predicting a subsequent frame based on a pixel signal of a previous two frames, for example, when a pixel signal of a previous two frames is read, a gain mode of a pixel of a next frame at a corresponding position is calculated based on an average of two frames to realize a selection of a gain mode of a next frame, where k may be other positive integers, and in another example, the number of rows in a pixel array is M, and n may be an integer between 1 and M-1.
Further, after generating the switching control signal yramp of the n-th row of the k+1th frame, the switching control signal yramp is stored in a register. In this example, the switching control signal of the pixel corresponding to the k+1th frame generated by the k-th frame may be generated and then stored in a register of the corresponding column, and then when the switching control signal of the pixel of the k+1th frame is written, the xramp is turned on again and the switching control signal is acquired from the register to realize the turning on and off of the main control transistor.
Further, the pixel signal reading method of the (n+1) th row of the kth frame includes: the (k+1) th row of the k+1 th frame is read during or after writing the (k+1) th row of the switching control signal, that is, for example, for the current frame, the reading of the pixel signal of the next row may overlap with the timing of the generation and writing of the prediction signal of the previous row, and the logic circuit may be controlled to perform timing control, although the two may not overlap.
In summary, according to the pixel circuit, the CMOS image sensor and the method for improving dynamic range thereof, the design of the gain switching module enables the pixel circuit to work in different transmission gain modes according to the predicted light intensity, and the switching between the low transmission gain mode and the high transmission gain mode ensures that the pixel signal can be normally transmitted in both small light intensity and large light intensity, thereby realizing high dynamic range. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (14)
1. A pixel circuit, the pixel circuit comprising: photoelectric conversion element, transmission transistor, storage capacitor and gain switching module, wherein,
the first end of the storage capacitor is connected with the output end of the photoelectric conversion element through the transmission transistor, the second end of the storage capacitor is connected with a first reference potential, the gate end of the transmission transistor is connected with a transmission control signal, and the other end of the photoelectric conversion element is connected with a second reference potential;
the gain switching module is connected between the first end of the storage capacitor and the third reference potential and is used for adjusting the equivalent capacitance value of the storage capacitor according to the predicted light intensity so as to realize switching of different transmission gain modes.
2. The pixel circuit of claim 1, wherein the pixel circuit further comprises: and the pixel reading module is connected with the first end of the storage capacitor and used for reading out pixel signals.
3. The pixel circuit of claim 2, wherein the pixel readout module comprises: a reset transistor, a first source follower transistor, a first memory transistor, a first capacitor, a second memory transistor, a second capacitor, a second source follower transistor, and a row select transistor, wherein,
the gate end of the reset transistor is connected with a reset control signal, the first connecting end is connected with a first working voltage, and the second connecting end is connected with the first end of the storage capacitor;
the gate end of the first source following transistor is connected with the first end of the storage capacitor, the first connecting end is connected with variable voltage, and the second connecting end is connected with the first connecting end of the first storage transistor;
the gate end of the first storage transistor is connected with a first storage control signal, the second connection end of the first storage transistor is connected with the first connection end of the second storage transistor, and the second connection end of the first storage transistor is connected with a fourth reference potential through the first capacitor;
the gate end of the second storage transistor is connected with a second storage control signal, and the second connection end is connected with the gate end of the second source follower transistor and is connected with a fifth reference potential through the second capacitor;
the first connecting end of the second source following transistor is connected with a second working voltage, and the second connecting end of the second source following transistor is connected with the first connecting end of the row selecting transistor;
the gate end of the row selection transistor is connected with a row selection control signal, and the second connection end generates the pixel signal.
4. The pixel circuit of claim 2, wherein the pixel readout module comprises: a reset transistor, a first source follower transistor, a first memory transistor, a first capacitor, a second memory transistor, a second capacitor and a second source follower transistor, wherein,
the gate end of the reset transistor is connected with a reset control signal, the first connecting end is connected with a first variable voltage, and the second connecting end is connected with the first end of the storage capacitor;
the gate end of the first source following transistor is connected with the first end of the storage capacitor, the first connecting end is connected with the second variable voltage, and the second connecting end is connected with the first connecting end of the first storage transistor;
the gate end of the first storage transistor is connected with a first storage control signal, the second connection end of the first storage transistor is connected with the first connection end of the second storage transistor, and the second connection end of the first storage transistor is connected with a sixth reference potential through the first capacitor;
the gate end of the second storage transistor is connected with a second storage control signal, and the second connection end is connected with the gate end of the second source follower transistor and is connected with a seventh reference potential through the second capacitor;
the first connecting end of the second source following transistor is connected to the working voltage, and the second connecting end of the second source following transistor generates the pixel signal.
5. The pixel circuit according to any one of claims 1-4, wherein the gain switching module comprises: the device comprises a main control transistor and an adjusting capacitor, wherein the gate end of the main control transistor is connected with a switching control signal related to the predicted light intensity, the first connecting end is connected with the first end of the storage capacitor, and the second connecting end is connected with the third reference potential through the adjusting capacitor.
6. The pixel circuit of claim 5, wherein the gain switching module further comprises: the gate end of the auxiliary control transistor is connected with an auxiliary control signal, the first connecting end is connected with the switching control signal related to the predicted light intensity, and the second connecting end is connected with the gate end of the main control transistor.
7. A CMOS image sensor, the CMOS image sensor comprising: at least one pixel circuit according to any one of claims 1-6.
8. The CMOS image sensor according to claim 7, wherein the CMOS image sensor comprises a plurality of pixels arranged in a pixel array in rows and columns, and the pixels correspond to the pixel circuits, wherein when the pixel circuits include the auxiliary control transistors, the first connection terminals of the same column of the auxiliary control transistors are connected to the corresponding switching control signals related to the predicted light intensity based on the same control line.
9. The CMOS image sensor according to claim 7 or 8, wherein the image sensor comprises a stacked first substrate and second substrate, the storage capacitor and the gain switching module being fabricated on the same substrate; and/or the image sensor comprises a third substrate, and the peripheral logic control circuit is prepared on the third substrate.
10. The CMOS image sensor according to claim 9, wherein the photoelectric conversion element, the transfer transistor, the storage capacitor, and the gain switching module are fabricated on the first substrate; the readout circuitry is fabricated on the second substrate; alternatively, the photoelectric conversion element and the transfer transistor are prepared on the first substrate; the storage capacitor, the gain switching module and the readout circuit are prepared on the second substrate.
11. A method for improving the dynamic range of a CMOS image sensor using a pixel circuit according to any one of claims 1 to 6, the method comprising:
predicting the light intensity corresponding to the pixel signal of the next frame based on the historical pixel signal;
when the light intensity corresponding to the pixel signal of the next frame is the first light intensity, adopting an equivalent capacitance value of the storage capacitor to make the CMOS image sensor work in a high transmission gain mode;
when the light intensity corresponding to the pixel signal of the next frame is the second light intensity, adopting an equivalent capacitance value of the storage capacitor with larger value to enable the CMOS image sensor to work in a low transmission gain mode;
the first light intensity is smaller than a preset light intensity threshold value, and the second light intensity is larger than the preset light intensity threshold value.
12. The method of claim 11, wherein the method comprises:
after the pixel signals of the nth row of the kth frame are read, generating a switching control signal of the nth row of the (k+1) th frame;
and opening an auxiliary control signal of the (k+1) th row of the frame, writing the switching control signal into a grid electrode of the main control transistor of the (k+1) th row of the frame, wherein k is more than or equal to 1, and n is more than or equal to 1.
13. The method of claim 12, wherein the switching control signal is stored in a register after generating the switching control signal of the nth row of the k+1st frame.
14. The method of claim 12, wherein the pixel signal reading mode of the n+1th row of the kth frame comprises:
the (k+1) th row of the k+1 th frame is read during or after writing the (k+1) th row of the switching control signal.
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