CN117939321A

CN117939321A - Sensor pixel unit, signal processing circuit and electronic device

Info

Publication number: CN117939321A
Application number: CN202311853350.8A
Authority: CN
Inventors: 韩润泽
Original assignee: Beijing Fusion Future Technology Co ltd
Current assignee: Beijing Fusion Future Technology Co ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-04-26

Abstract

The embodiment of the disclosure discloses a sensor pixel unit, a signal processing circuit and an electronic device, wherein the sensor pixel unit comprises: the detector, the integrating capacitor, the reset transistor and the reset control circuit; the detector is used for converting the first signal into an electric signal and transmitting the electric signal to the integrating capacitor for storage; the integrating capacitor is used for transmitting the stored electric signals to the reset control circuit, and determining and outputting output signals of the sensor pixel units based on the electric signals; the reset transistor is used for communicating the integrating capacitor with a power signal through a source electrode terminal and a drain electrode terminal, and resetting the integrating capacitor through the power signal when the reset transistor is turned on; the reset control circuit is used for determining a reset control signal based on the electric signal and controlling whether the reset transistor is conducted or not according to the reset control signal.

Description

Sensor pixel unit, signal processing circuit and electronic device

Technical Field

The disclosure relates to the technical field of sensors, in particular to a sensor pixel unit, a signal processing circuit and electronic equipment.

Background

Image sensors have been widely used in the fields of digital cameras, mobile phones, medical treatment, automobiles, unmanned aerial vehicles, machine recognition, etc., and particularly, the rapid development of the technology for manufacturing complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensors has led to higher demands on the quality of the output images of the image sensors. CMOS image sensors can be classified into two categories according to the signal acquisition mode: one way is to set the exposure time length for the pixels and then measure the voltage signal variation; the second method is a method of setting a voltage change amount for a pixel and measuring an exposure time period, and such an image sensor is called a pulse train type image sensor.

Disclosure of Invention

According to an aspect of the embodiments of the present disclosure, there is provided a sensor pixel unit including: the detector, the integrating capacitor, the reset transistor and the reset control circuit;

the detector is used for converting the first signal into an electric signal and transmitting the electric signal to the integrating capacitor for storage;

The integrating capacitor is used for transmitting the stored electric signals to the reset control circuit, and determining and outputting output signals of the sensor pixel units based on the electric signals;

The reset transistor is used for communicating the integrating capacitor with a power signal through a source electrode terminal and a drain electrode terminal, and resetting the integrating capacitor through the power signal when the reset transistor is turned on;

the reset control circuit is used for determining a reset control signal based on the electric signal and controlling whether the reset transistor is conducted or not according to the reset control signal.

Optionally, the reset control circuit includes: a latch circuit and a reset latch control circuit;

the latch circuit is used for latching a target signal determined based on the electric signal and transmitting the target signal to the reset latch control circuit;

The reset latch control circuit is used for enabling the reset transistor to be conducted according to control of a preset control clock signal when the sensor pixel unit does not output the output signal.

Optionally, the reset latch control circuit includes: and logic circuitry;

One input end of the AND logic circuit is connected with the output end of the latch circuit, receives the target signal, the other input end of the AND logic circuit is connected with the preset control clock signal, determines a reset control signal based on the target signal and the AND logic operation result of the preset control clock signal, and controls whether the reset transistor is conducted or not through the reset control signal.

Optionally, the reset latch control circuit further includes: or logic circuits;

One input end of the OR logic circuit is connected with the output end of the AND logic circuit, receives the reset control signal, the other input end receives an initial reset signal, and the output end is connected with the grid electrode of the reset transistor; and determining whether the reset transistor is turned on or not based on the OR logic operation result of the reset control signal and the initial reset signal.

Optionally, the reset latch control circuit further includes: an initial reset switch in parallel with the reset transistor;

And the source terminal of the initial reset switch is connected with the power supply signal, the drain terminal of the initial reset switch is connected with the integrating capacitor, the gate terminal of the initial reset switch receives an initial reset signal, and the integrating capacitor is reset when the initial reset signal is in a high level.

Optionally, the reset control circuit further includes: a comparator;

The positive input end of the comparator is connected with a preset threshold signal, the negative input end of the comparator receives the electric signal, and the output end of the comparator is connected with the latch circuit.

Optionally, the comparator performs comparison of the electrical signal and the preset threshold signal according to control of a comparison control signal, determines the target signal based on a comparison result, and inputs the target signal to the latch circuit.

Optionally, the method further comprises: a counter;

the counter is used for receiving the target signals output by the latch circuit, counting the target signals which meet preset conditions in the target signals, and outputting a counting result according to a counting control signal.

Optionally, the method further comprises: a transmission switch;

the transmission switch is characterized in that a source end is connected with the detector, a drain end is connected with the integrating capacitor, a grid end receives an external conduction signal, and the detector and the integrating capacitor are conducted according to the control of the external conduction signal.

Optionally, the method further comprises: a voltage output module;

the voltage output module is used for outputting the output signal according to the control of the output control signal.

Optionally, the voltage output module includes: a source follower transistor and a pixel selection transistor;

the grid end of the source following transistor is connected with the integrating capacitor, the drain end of the source following transistor is connected with a power supply signal, and the source end of the source following transistor is connected with the drain end of the pixel selection transistor; for detecting and following a change in the potential of the integrating capacitor, determining the output signal;

The drain terminal of the pixel selection transistor is connected with the source terminal of the source following transistor, the source terminal is the output terminal of the sensor pixel unit, the gate terminal is connected with an output control signal, and whether the output signal is output or not is determined according to the control of the output control signal.

According to another aspect of the embodiments of the present disclosure, there is provided a signal processing circuit including: a pixel array consisting of m rows by n columns of sensor pixel cells according to any one of the embodiments above, a row control module, and k column readout modules; wherein each column readout module corresponds to at least one column of the sensor pixel units; m, n and k are integers greater than or equal to 1 respectively;

The row control module is used for transmitting an output control signal to each sensor pixel unit in the pixel array;

The pixel array is used for enabling k sensor pixel units in each row of sensor pixel units to perform signal processing according to control of the output control signals, outputting k output signals and counting results and respectively sending the k output signals and the counting results to k column readout modules;

The column readout module is used for reading out the output signals and the counting results transmitted by the sensor pixel units.

Optionally, the column readout module sequentially receives the output signal and the count result output by the corresponding at least one sensor pixel unit.

According to still another aspect of the embodiments of the present disclosure, there is provided an electronic device including: the processor, and the memory communicatively connected with the processor, further including the sensor pixel unit according to any one of the above embodiments;

The memory stores computer-executable instructions;

the processor executes computer-executable instructions stored by the memory to control the sensor pixel unit.

Optionally, the electronic device is incorporated into any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.

The sensor pixel unit, the signal processing circuit and the electronic device provided based on the above embodiments of the present disclosure include: the detector, the integrating capacitor, the reset transistor and the reset control circuit; the detector is used for converting the first signal into an electric signal and transmitting the electric signal to the integrating capacitor for storage; wherein the first signal comprises at least one of: an infrared signal, an optical signal; the integrating capacitor is used for transmitting the stored electric signals to the reset control circuit, and determining and outputting output signals of the sensor pixel units based on the electric signals; the reset transistor is used for communicating the integrating capacitor with a power signal through a source electrode terminal and a drain electrode terminal, and resetting the integrating capacitor through the power signal when the reset transistor is turned on; the reset control circuit is used for determining a reset control signal based on the electric signal and controlling whether the reset transistor is conducted or not according to the reset control signal. According to the embodiment of the disclosure, the reset control circuit is arranged in the sensor pixel unit, so that accurate reset of the integrating capacitor is realized, and the problem that an output signal is unavailable due to reset in the process of reading out the output signal is solved.

The technical scheme of the present disclosure is described in further detail below through the accompanying drawings and examples.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic circuit diagram of a sensor pixel unit according to an exemplary embodiment of the present disclosure;

fig. 2 is a schematic circuit diagram of a sensor pixel unit according to another exemplary embodiment of the present disclosure;

Fig. 3 is a schematic circuit diagram of a reset control circuit in a sensor pixel unit according to an exemplary embodiment of the present disclosure;

fig. 4 is a schematic circuit configuration diagram of a sensor pixel unit according to still another exemplary embodiment of the present disclosure;

fig. 5 is a schematic circuit diagram of a sensor pixel unit according to still another exemplary embodiment of the present disclosure;

fig. 6 is a schematic circuit diagram of a sensor pixel unit according to still another exemplary embodiment of the present disclosure;

Fig. 7 is a schematic circuit diagram of a signal processing circuit according to an exemplary embodiment of the present disclosure;

FIG. 8 is a timing diagram of signals in a plurality of rows of pixel cells in a pixel array in a signal processing circuit according to an exemplary embodiment of the present disclosure;

fig. 9 illustrates a block diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present disclosure and not all of the embodiments of the present disclosure, and that the present disclosure is not limited by the example embodiments described herein.

It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.

It will be appreciated by those of skill in the art that the terms "first," "second," etc. in embodiments of the present disclosure are used merely to distinguish between different steps, devices or modules, etc., and do not represent any particular technical meaning nor necessarily logical order between them.

It should also be understood that in embodiments of the present disclosure, "plurality" may refer to two or more, and "at least one" may refer to one, two or more.

It should also be appreciated that any component, data, or structure referred to in the presently disclosed embodiments may be generally understood as one or more without explicit limitation or the contrary in the context.

In addition, the term "and/or" in this disclosure is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the front and rear association objects are an or relationship. The data referred to in this disclosure may include unstructured data, such as text, images, video, and the like, as well as structured data.

It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and that the same or similar features may be referred to each other, and for brevity, will not be described in detail.

Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In carrying out the present disclosure, the inventors have found that in the pulse imaging mode of the current infrared field of the prior art, the column stage and the output stage read pixel integration results row by row over time, the pixel integration proceeds without interruption, and that the main difference between the conventional integration mode is that the signal transmitted to the column stage process includes a reset count signal in addition to the analog signal of the conventional readout mode. The electrical signal obtained by the detector is continuously integrated in the pixel unit through an integration capacitor; while outputting the electric signal in the integral capacitor, determining whether to reset the integral capacitor according to whether the electric signal in the integral capacitor reaches a preset threshold value, and outputting the reset times of the integral capacitor while resetting the integral capacitor; and the output electric signals and the reset times are synchronously output by a circuit through a column reading module. In the above implementation, it can be seen that the integral reset and the electric signal readout process are performed independently, so when the electric signal on the integral capacitor in the pixel unit is read, the pixel unit may be in the reset process, and the readout signal is not available, so that the information of the current frame needs to be complemented according to the information of the previous and subsequent frames. In order to solve the problem that the reset process and the read process overlap in time possibly resulting in the read data being unusable, the inventors propose the following technical solution.

Fig. 1 is a schematic circuit diagram of a sensor pixel unit according to an exemplary embodiment of the present disclosure. As shown in fig. 1, a pixel unit of a sensor (hereinafter referred to as a pixel unit) provided in this embodiment includes: a detector 110, an integrating capacitor 120, a reset transistor 130, and a reset control circuit 140.

The detector 110 is configured to convert the first signal into an electrical signal, and transmit the electrical signal to the integrating capacitor for storage.

Wherein the first signal comprises at least one of: infrared signals, optical signals. When the sensor pixel unit is applied to an infrared pulse image sensor, the first signal is an infrared signal, and the detector may be an infrared electrical device that converts the infrared signal into an electrical signal, including but not limited to: and when the detector converts an electric signal, charges on the integrating capacitor are extracted or injected, and the voltage on the integrating capacitor after reset can be reduced or increased. When the sensor pixel unit is applied to a general pulse image sensor, the first signal is an optical signal, and the detector may be a photoelectric conversion device, such as a photodiode, etc., that converts the optical signal into an electrical signal. The detector obtains charges after converting the first signal, and stores the charges by transmitting the charges to the integrating capacitor, for example, when the detector is a photodiode, the integrating capacitor is a floating diffusion area, and the floating diffusion area is used for storing photoelectric charges generated by the photodiode and transmitting the photoelectric charges in the form of an electric signal. Optionally, one end of the detector 110 is grounded GND, and the other end is connected to a connection between the integrating capacitor 120 and the reset transistor 130.

The integration capacitor 120 is used for transmitting the stored electric signal to the reset control circuit 140, and determining and outputting an output signal of the sensor pixel unit based on the electric signal.

Optionally, before storing the electrical signal, the integrating capacitor 120 resets according to the conduction condition of the reset transistor 130, so as to avoid inaccurate output signal caused by multiple accumulation of the electrical signal without resetting. One end of the integrating capacitor 120 is connected with the detector 110 and the reset transistor 130, and the other end is grounded GND.

And a reset transistor 130 for connecting the integrating capacitor to the power supply signal VDD through the source terminal and the drain terminal, and resetting the integrating capacitor 120 through the power supply signal VDD in response to the reset transistor 130 being turned on.

In this embodiment, the reset transistor 130 may be a field effect transistor, where the source terminal is connected to the power supply signal VDD, the drain terminal is connected to the integrating capacitor, the gate terminal is connected to the reset control circuit 140, and whether to be turned on is determined according to the reset control signal output by the reset control circuit 140; for example, the reset transistor is turned on when the reset control signal is high level, and is turned off when the reset control signal is low level.

The reset control circuit 140 is configured to determine a reset control signal based on the electrical signal, and control whether the reset transistor 130 is turned on according to the reset control signal.

In this embodiment, by setting the reset control circuit in the pixel unit, the time when the reset occurs and the time when the signal is read out are accurately controlled, so that the conflict between the reset time of the integrating capacitor 120 and the output time of the output signal is avoided, and the problem that the read voltage data is not available is further avoided.

The sensor pixel unit provided in the above embodiment of the present disclosure includes: the detector, the integrating capacitor, the reset transistor and the reset control circuit; the detector is used for converting the first signal into an electric signal and transmitting the electric signal to the integrating capacitor for storage; wherein the first signal comprises at least one of: an infrared signal, an optical signal; the integrating capacitor is used for transmitting the stored electric signals to the reset control circuit, and determining and outputting output signals of the sensor pixel units based on the electric signals; the reset transistor is used for communicating the integrating capacitor with a power signal through a source electrode terminal and a drain electrode terminal, and resetting the integrating capacitor through the power signal when the reset transistor is turned on; the reset control circuit is used for determining a reset control signal based on the electric signal and controlling whether the reset transistor is conducted or not according to the reset control signal. According to the embodiment of the disclosure, the reset control circuit is arranged in the sensor pixel unit, so that accurate reset of the integrating capacitor is realized, and the problem that an output signal is unavailable due to reset in the process of reading out the output signal is solved.

Fig. 2 is a schematic circuit diagram of a sensor pixel unit according to another exemplary embodiment of the present disclosure. As shown in fig. 2, the reset control circuit 140 includes: a latch circuit 141 and a reset latch control circuit 142;

a latch circuit 141 for latching a target signal determined based on the electric signal and transmitting the target signal to the reset latch control circuit.

In this embodiment, the latch circuit 141 may be a component such as a latch (e.g., a D flip-flop), and the target signal at the input end of the latch circuit 141 is latched in the latch circuit 141 according to the latch control signal Dclk input from the outside (e.g., a row controller in a sensor), and the latched target signal is input into the reset latch control circuit 142 according to the latch control signal, and the latch circuit 141 latches the target signal, so that the target signal corresponding to the electrical signal output after each detector exposure can be accurately used as the basis of the reset control signal for resetting the integrating capacitor 120 without being interfered by other signals, thereby improving the accuracy of the reset control.

The reset latch control circuit 142 is configured to turn on the reset transistor according to control of a preset control clock signal when the sensor pixel unit does not output an output signal.

In this embodiment, by designing the timing relationship between reset and signal readout, when the pixel unit outputs an output signal, the output signal is not output when the integral capacitor is reset, so that the situation that the output signal is unavailable is avoided. The problem that the integration capacitor is in a reset state possibly encountered in the process of reading out the output signal is solved, so that delay is reduced, and meanwhile, through accurate control of the reset process, the number of pixels in the reset state at the same time can be reduced, so that the requirement on driving current can be reduced, and the power consumption of a chip is reduced.

Fig. 3 is a schematic circuit diagram of a reset control circuit in a sensor pixel unit according to an exemplary embodiment of the present disclosure. As shown in fig. 3, the reset latch control circuit 142 includes: and logic circuit 143;

One input end of the AND logic circuit 143 is connected with the output end of the latch circuit 141, receives the target signal, the other input end is connected with a preset control clock signal Ren, determines a reset control signal based on the AND logic operation result of the target signal and the preset control clock signal Ren, and controls whether the reset transistor is turned on or not through the reset control signal.

In this embodiment, the and logic circuit 143 controls the output of the target signal by the preset control clock signal, and because of the characteristics of the and logic circuit, the and logic circuit outputs a high level only when the input signals of the two input terminals are both high, and outputs a low level otherwise, so that when the target signal is high, the reset of the integrating capacitor can be realized based on the technical scheme of the prior art, but in order to solve the problem that the reset is executed at different time from the output signal, the embodiment controls the timing of the preset control clock signal, and only after the readout of the output signal is completed, the reset stage of the pixel unit is performed, the preset control clock signal Ren is given a high level, so that the reset of the integrating capacitor is realized.

However, when only the and logic circuit 143 is present in the reset latch control circuit 142, the reset of the integration capacitance can be started only after the start of outputting the target signal, and the initial reset of the integration capacitance cannot be performed until the pixel unit initially acquires the electric signal, and therefore, as shown in fig. 3, the reset latch control circuit 142 provided in the present embodiment further includes: or logic 144;

Or logic circuit 144 has one input connected to the output of logic circuit 143, receives the reset control signal, the other input receives the initial reset signal SET, and the output is connected to the gate of reset transistor 130; and determining whether the reset transistor is turned on based on the OR logic operation result of the reset control signal and the initial reset signal SET.

In this embodiment, the reset control signal output by the and logic circuit 143 is input to one input end of the or logic circuit 144, the other input end receives the initial reset signal SET, and based on the characteristics of the or logic circuit, only one high level exists in the two input signals, and the high level signal can be output, so that the or logic circuit 144 can provide one high level to the reset transistor 130 through the initial reset signal SET before the pixel unit initially performs signal conversion, so as to realize initial reset to the integrating capacitor 120, and then after the integrating capacitor starts outputting an electrical signal, the initial reset signal SET can be controlled to always maintain a low level, so that the reset transistor 130 is reset only under the influence of the reset control signal.

In addition, in addition to the and logic circuit in the above embodiment, there may be many other ways to implement the initial reset of the pixel unit, for example, fig. 4 is a schematic circuit structure of the sensor pixel unit according to still another exemplary embodiment of the present disclosure. As shown in fig. 4, the reset latch control circuit 142 in this embodiment includes: an initial reset switch 145 in parallel with the logic circuit 143 and with the reset transistor 130;

The source terminal of the initial reset switch 145 is connected to the power supply signal VDD, the drain terminal is connected to the integration capacitor 120, the gate terminal receives the initial reset signal SET, and the integration capacitor 120 is reset in response to the initial reset signal SET being at a high level.

In this embodiment, the reset transistor 130 is skipped, the capacitance signal VDD and the integrating capacitor 120 are directly connected through the initial reset switch 145, and the initial reset of the integrating capacitor 120 can be achieved only by giving an initial reset signal SET with a high initial time and a low remaining time to the initial reset switch 145, and the reset of the subsequent integrating capacitor 120 can be controlled only according to the signal output by the logic circuit 143 without any influence on other circuits.

Fig. 5 is a schematic circuit diagram of a sensor pixel unit according to still another exemplary embodiment of the present disclosure. As shown in fig. 5, the reset control circuit 140 includes: a latch circuit 141, a reset latch control circuit 142, and a comparator 146;

the positive input end of the comparator 146 is connected to the preset threshold signal Vref, the negative input end thereof receives the electrical signal, and the output end thereof is connected to the latch circuit 141.

In this embodiment, the comparator 146 performs threshold control on the electric signal output from the integrating capacitor, and outputs the target signal to the latch circuit 141. The input preset threshold signal Vref is compared with the electrical signal by the comparator 146, and when the electrical signal is smaller than the preset threshold signal Vref, the target signal output by the comparator 146 is at a high level. In addition, the comparator 146 performs comparison of the electric signal with a preset threshold signal Vref according to control of the comparison control signal Cen, determines a target signal based on the comparison result, and inputs the target signal to the latch circuit 141. In this embodiment, a comparison control signal Cen may be added to the comparator, and the comparator 146 can only operate when the comparison control signal Cen is valid (e.g., high level), so that the time difference problem of the reset of the integrating capacitor and the signal output can be further solved by controlling the operation time of the comparator 146 by the comparison control signal Cen.

Fig. 6 is a schematic circuit diagram of a sensor pixel unit according to still another exemplary embodiment of the present disclosure. As shown in fig. 6, the pixel unit provided in this embodiment further includes: a counter 150;

The counter 150 is configured to receive the target signals output by the latch circuit 141, count target signals that meet a preset condition among the target signals, and output a count result according to the count control signal.

In this embodiment, the counter 150 counts the target signals reaching the preset condition in the target signals, so as to accumulate the reset times of the integrating capacitor, where the preset condition may be set according to the actual application scenario, for example, when the target signals are voltage signals, the preset condition is set to be that the target signals are at a high level. The counter 150 may receive a count control signal Den, control of starting the counter 150 according to control of the count control signal Den, and the timing of the count control signal Den may be after the latch control signal Dclk for controlling the latch circuit 141, and each high level of the latch control signal Dclk may be followed by a high level of the count control signal Den, that is, the counter 150 may count the target signal latched by the latch circuit 141, and may further include a count output signal Dsel for controlling the output timing of the counter 150 according to the count output signal Dsel, and the count output signal Dsel may be generally consistent with an external control signal outputted by the control output signal, so that the count result and the output signal are outputted together.

The implementation form of the counter 150 is not limited to a certain implementation form, and may be any implementation form as long as the counting function is realized. The comparator 146 is implemented using an operational amplifier, the output result is latched by a D flip-flop (latch), the latched comparison result and the preset control clock signal Ren are and-operated, the and logic circuit 143 output is always 0 when the preset control clock signal Ren is in a low level state, the initial reset signal SET is low level, or the logic circuit 144 output is always a low level voltage. When the preset control clock signal Ren is at a high level, the output of the AND logic circuit and the OR logic circuit is consistent with the latched comparison result when the initial reset signal SET is in a low level state. The latched comparison result is sent to the counter 150 for accumulation under the action of the count control signal Den, and the accumulated result is output according to the control of the count output signal Dsel.

As shown in fig. 6, the sensor pixel unit provided in this embodiment may further include: and a transmission switch 160.

The transmission switch 160 has a source terminal connected to the detector 110, a drain terminal connected to the integration capacitor 120, and a gate terminal receiving the external on signal GPOL, and turns on the detector 110 and the integration capacitor 120 according to the control of the external on signal GPOL.

When the transmission switch 160 is turned on, the detector 110 transmits the converted electric signal to the integrating capacitor 120 through the transmission switch 160 for signal storage, so that the voltage of the integrating capacitor 120 after reset is reduced along with the receiving of the electric signal; the transmission and storage of the electrical signal obtained after the conversion of the first signal by the detector 110 are realized.

As shown in fig. 6, the sensor pixel unit provided in this embodiment may further include: a voltage output module 170;

The voltage output module 170 is configured to output an output signal according to the control of the output control signal Vsel.

Optionally, the voltage output module 170 includes: a source follower transistor 171 and a pixel select transistor 172.

The source follower transistor 171 has a gate terminal connected to the integration capacitor 120, a drain terminal connected to the power supply signal VDD, and a source terminal connected to the drain terminal of the pixel selection transistor 172; for detecting and following the potential change of the integrating capacitor 120, determining an output signal;

The pixel selection transistor 172 has a drain terminal connected to the source terminal of the source follower transistor 171, a source terminal being an output terminal of the sensor pixel unit, a gate terminal connected to the output control signal Vsel, and determines whether to output the output signal according to control of the output control signal.

In this embodiment, the gate terminal of the source follower transistor 171 is connected to the integration capacitor 120, and follows the potential change of the integration capacitor 120 to obtain an output signal, and the pixel select transistor 172 selects whether to output the output signal according to the control of the external control signal Vsel, which may be an external clock signal or an external pulse signal, or the like; the pixel selection transistor 172 is controlled to output an output signal based on the timing transmission signal of the external clock circuit, and the output signal may be any one or more of a pulse signal, a potential signal, a value with a limit, and the like.

Fig. 7 is a schematic circuit diagram of a signal processing circuit according to an exemplary embodiment of the present disclosure. As shown in fig. 7, the signal processing circuit provided in this embodiment includes: a pixel array 710 composed of m rows by n columns of the sensor pixel units 711 (hereinafter referred to as pixel units) provided in any of the above embodiments, a row control module 720, and k column readout modules 730; wherein each column readout module 730 corresponds to at least one column of sensor pixel cells 711; m, n and k are integers greater than or equal to 1.

The row control module 720 is configured to transmit an output control signal to each sensor pixel unit 711 in the pixel array.

Optionally, the row control module 720 transmits at least one control signal of the row end to each sensor pixel unit 711, for example, the at least one control signal may include a preset control clock signal Ren, a latch control signal Dclk, a comparison control signal Cen, a count control signal Den, a count output signal Dsel, and an output control signal Vsel. The initial reset signal SET, the external conducting signal GPOL and the preset threshold value signal Vref can be directly input into the pixel array through the outside; the output signal of the pixel unit and the counting result of the counter are output together.

A pixel array 710 for processing the k sensor pixel units 711 in each row of sensor pixel units 711 according to control of an output control signal Vsel, outputting k output signals and count results, and respectively transmitting to k column readout modules 730;

And a column readout module 730 for reading out the output signal and the count result transmitted by the sensor pixel unit 730.

Alternatively, the column readout module 730 sequentially receives the output signal and the count result output from the corresponding at least one sensor pixel unit 711, and the column readout module 730 reads out the output signal and the count result output from one sensor pixel unit 711 at a time.

In this embodiment, the column readout module 730 may be any circuit structure capable of realizing signal readout in the prior art. In this embodiment, n columns of pixel units share a set of column readout modules (k column readout modules) to take charge of reading out signals, and each column reads out an output signal and a counter signal in a time-sharing manner. There are n columns in the entire array, so each column readout module 730 corresponds to n/k columns of pixel cells, where the remainder corresponds to one column readout module 730 when n/k is not divisible. The manner of applying various signals to each pixel cell in the same row in the pixel array 710 is shown in fig. 8, which is a timing diagram of signals in a plurality of rows of pixel cells in the pixel array in a signal processing circuit according to an exemplary embodiment of the present disclosure. As shown in fig. 8, vsel [1] represents an output control signal of the first column pixel unit, vsel [2] represents an output control signal of the second column pixel unit, and so on. For the pixel array 710, it is divided into two phases, a readout phase (output signal and count result readout) and a reset phase (integrating capacitance reset), respectively, since the length of time required for reset is much longer than the length of time required for readout for a single pixel cell, the time required for the reset phase is much longer. In the readout stage, under the drive of the comparison control signal Cen, the electrical signals in the pixel units in the same row are compared with the preset threshold signal Vref, then the comparison result is latched by the latch, the latched result is accumulated in the counter under the action of the counting control signal Den, the normal readout of the voltage is not affected in the process of comparing and accumulating, and the synchronous readout can be performed. After the output signal of the selected row is read out, a reset is performed at a subsequent stage. It should be noted that the timing diagram herein refers to the voltage timing relationship of a certain row, which is divided into an odd row and an even row, and when the pixel cells of the odd row are in the readout phase, the pixel cells of the even row are in the reset phase, and the readout and the reset are alternately performed between the two rows.

As understood from the above timing chart, the reset of the pixel unit is performed only in the range (high level) where the preset control clock signal Ren is valid, and the comparison is performed only in the range (high level) where the comparison control signal Cen is valid, and the comparator corresponding to each pixel unit in the pixel array does not need to be in an operating state all the time when operating. And meanwhile, the odd lines and the even lines are separated, so that the number of devices in a reset state at the same time is reduced, the requirement on device reset current driving is reduced, and the power consumption of a driving module is reduced.

According to still another aspect of the embodiments of the present disclosure, there is provided an electronic device including: the processor, and the memory communicatively connected with the processor, further including the sensor pixel unit or the signal processing circuit according to any one of the above embodiments;

The memory stores computer-executable instructions;

the processor executes computer-executable instructions stored by the memory to control the sensor pixel unit or signal processing circuitry.

The electronic device provided by the present disclosure may be incorporated as any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.

The electronic device provided by the present disclosure may be applied to any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.

Next, an electronic device according to an embodiment of the present disclosure is described with reference to fig. 9. The electronic device may be either or both of the first device and the second device, or a stand-alone device independent thereof, which may communicate with the first device and the second device to receive the acquired input signals therefrom.

As shown in fig. 9, the electronic device includes one or more processors and memory.

The processor may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device to perform the desired functions.

The memory may store one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program products may be stored on the computer readable storage medium that can be run by a processor to implement the sensor pixel units or signal processing circuits and/or other desired functions of the various embodiments of the disclosure described above.

In one example, the electronic device may further include: input devices and output devices, which are interconnected by a bus system and/or other forms of connection mechanisms (not shown).

In addition, the input device may include, for example, a keyboard, a mouse, and the like.

The output device may output various information including the determined distance information, direction information, etc., to the outside. The output device may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, etc.

Of course, only some of the components of the electronic device relevant to the present disclosure are shown in fig. 9 for simplicity, components such as buses, input/output interfaces, and the like being omitted. In addition, the electronic device may include any other suitable components depending on the particular application.

In addition to the methods and apparatus described above, embodiments of the present disclosure may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the sensor pixel units or signal processing circuits according to the various embodiments of the present disclosure described in the above section of the specification.

The computer program product may write program code for performing the operations of embodiments of the present disclosure in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

Furthermore, embodiments of the present disclosure may also be a computer-readable storage medium, having stored thereon computer program instructions, which when executed by a processor, cause the processor to perform the sensor pixel units or signal processing circuits according to the various embodiments of the present disclosure described in the above section of the present disclosure.

The computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The basic principles of the present disclosure have been described above in connection with specific embodiments, but it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present disclosure. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, since the disclosure is not necessarily limited to practice with the specific details described.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, so that the same or similar parts between the embodiments are mutually referred to. For system embodiments, the description is relatively simple as it essentially corresponds to method embodiments, and reference should be made to the description of method embodiments for relevant points.

The block diagrams of the devices, apparatuses, devices, systems referred to in this disclosure are merely illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the disclosure to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims

1. A sensor pixel cell, comprising: the detector, the integrating capacitor, the reset transistor and the reset control circuit;

2. The pixel cell of claim 1, wherein the reset control circuit comprises: a latch circuit and a reset latch control circuit;

3. The pixel unit according to claim 2, wherein the reset latch control circuit includes: and logic circuitry;

4. A pixel cell according to claim 3, wherein the reset latch control circuit further comprises: or logic circuits;

5. A pixel cell according to claim 3, wherein the reset latch control circuit further comprises: an initial reset switch in parallel with the reset transistor;

6. The pixel cell according to any one of claims 2-5, wherein the reset control circuit further comprises: a comparator;

7. The pixel unit according to claim 6, wherein the comparator performs comparison of the electric signal with the preset threshold signal according to control of a comparison control signal, determines the target signal based on a comparison result, and inputs the target signal to the latch circuit.

8. A pixel cell according to any one of claims 2-7, further comprising: a counter;

9. A pixel cell according to any one of claims 1-8, further comprising: a voltage output module;

10. The pixel cell of claim 9, wherein the voltage output module comprises: a source follower transistor and a pixel selection transistor;

11. A signal processing circuit, comprising: a pixel array consisting of m rows by n columns of sensor pixel cells according to any one of claims 1 to 10, a row control module, and k column readout modules; wherein each column readout module corresponds to at least one column of the sensor pixel units; m, n and k are integers greater than or equal to 1 respectively;

12. The signal processing circuit of claim 11, wherein the column readout module sequentially receives the output signal and the count result output by the corresponding at least one of the sensor pixel cells.

13. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor, further comprising the sensor pixel unit of any one of claims 1-10 or the signal processing circuit of claim 11 or 12;

The memory stores computer-executable instructions;

the processor executes computer-executable instructions stored by the memory to control the sensor pixel unit or the signal processing circuit.

14. The electronic device of claim 13, wherein the electronic device is incorporated as any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.