CN220732924U - Pulse sequence type sensor pixel unit, pulse sequence type sensor and equipment - Google Patents

Abstract

The embodiment of the disclosure discloses a pulse sequence type sensor pixel unit, a pulse sequence type sensor and equipment, wherein the pulse sequence type sensor pixel unit comprises: the device comprises a signal acquisition circuit, a signal quantization circuit and a feedback control circuit; the signal acquisition circuit is respectively connected with the signal quantization circuit and the feedback control circuit; the signal quantization circuit is respectively connected with the signal acquisition circuit and the feedback control circuit; the feedback control circuit is respectively connected with the signal acquisition circuit and the signal quantization circuit; in this embodiment, by storing the reference signal in the signal quantization circuit, capacitance noise generated due to the fact that the reference voltage is close to the reset voltage in the prior art is reduced, quantization noise caused by fluctuation of the production process is optimized, quality of an output image of the sensor, especially quality of an image in a dark light environment is improved, and signal to noise ratio of the image can be effectively improved.

Description

Pulse sequence type sensor pixel unit, pulse sequence type sensor and equipment

Technical Field

The present disclosure relates to sensor technology, and more particularly, to a pulse train sensor pixel unit, a pulse train sensor, and a device.

Background

Image sensors have been widely used in the fields of digital cameras, mobile phones, medical treatment, automobiles, unmanned aerial vehicles, machine recognition, etc., and particularly, the rapid development of the technology for manufacturing complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensors has led to higher demands on the quality of the output images of the image sensors. CMOS image sensors can be classified into two categories according to the signal acquisition mode: one way is to set the exposure time length for the pixels and then measure the voltage signal variation; the second method is a method of setting a voltage change amount for a pixel and measuring an exposure time period, and such an image sensor is called a pulse train type image sensor.

Disclosure of Invention

According to an aspect of the embodiments of the present disclosure, there is provided a pulse train sensor pixel unit including: the device comprises a signal acquisition circuit, a signal quantization circuit and a feedback control circuit;

the signal acquisition circuit is respectively connected with the signal quantization circuit and the feedback control circuit;

the signal quantization circuit is respectively connected with the signal acquisition circuit and the feedback control circuit;

The feedback control circuit is respectively connected with the signal acquisition circuit and the signal quantization circuit.

Optionally, the signal quantization circuit includes: a signal storage circuit and a comparator;

the signal storage circuit is connected with the signal acquisition circuit and the first input end of the comparator;

the first input end of the comparator is connected with the signal storage circuit, the second input end of the comparator is connected with the signal acquisition circuit, and the output end of the comparator is used as the output end of the pulse sequence type sensor pixel unit.

Optionally, the signal storage circuit includes: a first switching transistor, a second switching transistor, a third switching transistor, and a capacitor;

the drain electrode of the first switching transistor is connected with the signal acquisition circuit, the source electrode of the first switching transistor is connected with one end of the capacitor, the grid electrode of the first switching transistor is connected with the feedback control circuit, and the drain electrode of the first switching transistor is used as the output end of the signal storage circuit to be connected with the first input end of the comparator;

the drain electrode of the second switching transistor is connected with the other end of the capacitor, the source electrode of the second switching transistor is grounded, and the grid electrode of the second switching transistor is connected with the feedback control circuit;

The drain electrode of the third switching transistor is connected with the other end of the capacitor, the source electrode of the third switching transistor is connected with the reference signal, and the grid electrode of the third switching transistor is connected with the feedback control circuit;

one end of the capacitor is connected with the source electrode of the first switching transistor, and the other end of the capacitor is connected with the drain electrode of the second switching transistor and the drain electrode of the third switching transistor respectively.

Optionally, the feedback control circuit includes: a first D flip-flop and a second D flip-flop;

the D end of the first D trigger is connected with the signal quantization circuit, and the Q end of the first D trigger is connected with the signal acquisition circuit and the D end of the second D trigger;

the D end of the second D trigger is connected with the Q end of the first D trigger; and the Q end is connected with the signal quantization circuit.

Optionally, the feedback control circuit includes: a first D flip-flop and a second D flip-flop;

the end D of the first D trigger is connected with the signal quantization circuit, and the end Q is connected with the signal acquisition circuit;

the D end of the second D trigger is connected with the signal quantization circuit; and the Q end is connected with the signal quantization circuit.

Optionally, the signal acquisition circuit includes: a photodiode, a reset transistor, and an auxiliary circuit;

The source electrode of the reset transistor is connected with the photodiode, the drain electrode of the reset transistor is connected with the power supply module, and the grid electrode of the reset transistor is connected with the feedback control circuit;

the anode of the photodiode is grounded, and the cathode of the photodiode is connected with the source electrode of the reset transistor;

the auxiliary circuit is connected with the cathode of the photodiode.

Optionally, the auxiliary circuit includes a source follower transistor and a pixel select transistor;

the grid electrode of the source following transistor is connected with the cathode of the photodiode, the source electrode of the source following transistor is connected with the pixel selection transistor, and the drain electrode of the source following transistor is connected with the power supply module;

the drain electrode of the pixel selection transistor is connected with the source electrode of the source following transistor, the source electrode is connected with the signal quantization circuit, and the grid electrode is connected with an external control signal.

Optionally, the auxiliary circuit further comprises a bias transistor;

the drain electrode of the bias transistor is connected with the source electrode of the pixel selection transistor, the source electrode is grounded, and the grid electrode is connected with an external conduction signal.

According to another aspect of the disclosed embodiments, there is provided a pulse train sensor including: a plurality of pulse train sensor pixel units according to any of the above embodiments.

According to still another aspect of the embodiments of the present disclosure, there is provided an electronic device including: the processor, and the memory communicatively connected with the processor, further including the pulse sequence type sensor pixel unit according to any one of the above embodiments or the pulse sequence type sensor according to the above embodiment;

the memory stores computer-executable instructions;

the processor executes computer-executable instructions stored by the memory to control the operation of the pulse train sensor pixel unit or the pulse train sensor.

Optionally, the electronic device is incorporated as any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.

The pulse sequence type sensor pixel unit, the pulse sequence type sensor and the device provided based on the above embodiments of the present disclosure, wherein the pulse sequence type sensor pixel unit includes: the device comprises a signal acquisition circuit, a signal quantization circuit and a feedback control circuit; the signal acquisition circuit is respectively connected with the signal quantization circuit and the feedback control circuit; the signal quantization circuit is respectively connected with the signal acquisition circuit and the feedback control circuit; the feedback control circuit is respectively connected with the signal acquisition circuit and the signal quantization circuit; in this embodiment, by storing the reference signal in the signal quantization circuit, capacitance noise (KTC noise) generated due to the fact that the reference voltage is close to the reset voltage in the prior art is reduced, quantization noise caused by fluctuation of the production process is optimized, quality of an output image of the sensor is improved, especially quality of an image in a dark light environment is improved, and signal to noise ratio of the image can be effectively improved.

The technical scheme of the present disclosure is described in further detail below through the accompanying drawings and examples.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic diagram of a pulse train sensor pixel unit according to an exemplary embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a signal quantization circuit in a pixel unit of a pulse train sensor according to an exemplary embodiment of the present disclosure;

FIG. 3-1 is a schematic diagram of a feedback control circuit in a pixel cell of a pulse train sensor according to an exemplary embodiment of the present disclosure;

fig. 3-2 is a schematic diagram of a structure of a feedback control circuit in a pixel unit of a pulse train sensor according to another exemplary embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a signal acquisition circuit in a pixel unit of a pulse train sensor according to an exemplary embodiment of the present disclosure;

FIG. 5 is a schematic diagram of signal timing corresponding to a pixel unit of a pulse train sensor according to an exemplary embodiment of the present disclosure;

Fig. 6 illustrates a block diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present disclosure and not all of the embodiments of the present disclosure, and that the present disclosure is not limited by the example embodiments described herein.

It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.

It will be appreciated by those of skill in the art that the terms "first," "second," etc. in embodiments of the present disclosure are used merely to distinguish between different steps, devices or circuits, etc., and do not represent any particular technical meaning nor necessarily logical order between them.

It should also be understood that in embodiments of the present disclosure, "plurality" may refer to two or more, and "at least one" may refer to one, two or more.

It should also be appreciated that any component, data, or structure referred to in the presently disclosed embodiments may be generally understood as one or more without explicit limitation or the contrary in the context.

In addition, the term "and/or" in this disclosure is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the front and rear association objects are an or relationship. The data referred to in this disclosure may include unstructured data, such as text, images, video, and the like, as well as structured data.

It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and that the same or similar features may be referred to each other, and for brevity, will not be described in detail.

Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In the process of realizing the disclosure, the inventor finds that the output end of the photoelectric integration unit in the pulse sequence type image sensor in the prior art is directly connected to the positive input end of the comparator, and the reset operation is performed on the photodiode through the reset tube, so that capacitance (KTC) noise is introduced; because in the image sensor production manufacturing process, process fluctuation exists between different wafers (wafer), between wafer and wafer, or between different chips of the same wafer, even in the same chip, the reset voltage of the photodiode of different pixels after the reset operation has different conditions, the bit stream data quantized by the comparator is influenced, and quantization noise is further introduced; in particular, in a pulse sequence image sensor operating in a dark light environment, the reference voltage is relatively close to the reset signal voltage output by the photodiode, for example, the reference voltage is only 10mV lower than the reset signal voltage of the photodiode, the fluctuation of the reset signal voltage output by pixels between different wafers or different chips of the same wafer may exceed 5mV, and thus the quantized pulse bit stream error of the pixel may exceed 50%. The disadvantage of high noise of the pulse sequence image sensor in the prior art is urgent to be optimally solved so as to improve the signal-to-noise ratio of the image quality output by the image sensor.

Fig. 1 is a schematic diagram of a pulse train sensor pixel unit according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the pulse train sensor pixel unit provided in this embodiment includes: a signal acquisition circuit 11, a signal quantization circuit 12 and a feedback control circuit 13.

The signal acquisition circuit 11 is connected to the signal quantization circuit 12 and the feedback control circuit 13, respectively, for receiving the optical signal during the exposure period to generate a first signal, performing reset according to the control of the first control signal input by the feedback control circuit 13, and outputting a second signal during the reset phase.

Alternatively, the main component in the signal acquisition circuit may be a photoelectric conversion element (for example, an element capable of converting light energy into electric energy, such as a photodiode) through which photoelectric conversion is performed, and a first signal obtained based on the converted electric charge, that is, a photoelectric signal obtained through photoelectric conversion, the first signal representing one frame of image signal acquired by the pulse sequence sensor pixel unit; the signal acquisition circuit 11 may further include an element that resets the photoelectric conversion element, and the reset element may receive control of the feedback control circuit 13, reset the photoelectric conversion element, and output a second signal (e.g., a reset signal).

The signal quantization circuit 12 is respectively connected with the signal acquisition circuit 11 and the feedback control circuit 13, and is used for storing a second signal in a reset stage of the signal acquisition circuit 11 according to the control of the second control signal input by the feedback control circuit 13; when the signal acquisition circuit 11 outputs the first signal, the output target signal is determined by referring to the stored second signal.

In this embodiment, the signal quantization circuit 12 is provided with a component for storing the second signal, and by storing the second signal, the signal quantization circuit 12 determines the target signal based on the second signal as a reference of the first signal when receiving the first signal, and since the second signal is also output from the signal acquisition circuit and the second signal processed by the same component is used as a reference of the first signal, the problem of introducing capacitance noise due to the fact that the reference signal may be similar to the first signal when using the reference signal of the set value is solved.

The feedback control circuit 13 is connected to the signal acquisition circuit 11 and the signal quantization circuit 12, and is configured to receive the target signal output by the signal quantization circuit 12, and determine a first control signal output to the signal acquisition circuit 11 and a second control signal output to the signal quantization circuit 12 according to the target signal.

In this embodiment, the feedback control circuit 13 generates the first control signal and the second control signal according to the target signal received from the signal quantization circuit 12, and realizes the reset control on the signal acquisition circuit 11 through the first control signal, and realizes the signal storage control on the signal quantization circuit 12 through the second control signal, thereby realizing the reset control of the signal acquisition circuit in the pixel unit and the storage control of the signal quantization circuit in the pixel unit.

The pulse sequence type sensor pixel unit provided by the above embodiment of the present disclosure includes: the device comprises a signal acquisition circuit, a signal quantization circuit and a feedback control circuit; the signal acquisition circuit is respectively connected with the signal quantization circuit and the feedback control circuit; the signal quantization circuit is respectively connected with the signal acquisition circuit and the feedback control circuit; the feedback control circuit is respectively connected with the signal acquisition circuit and the signal quantization circuit; in the embodiment provided by the disclosure, the reference signal is stored in the signal quantization circuit, so that capacitance noise (KTC noise) generated due to the fact that the reference voltage is close to the reset voltage in the prior art is reduced, quantization noise caused by fluctuation of a production process is optimized, the quality of an output image of the sensor is improved, particularly the quality of the image in a dim light environment is improved, and the signal to noise ratio of the image can be effectively improved.

Fig. 2 is a schematic diagram of a signal quantization circuit in a pixel unit of a pulse train sensor according to an exemplary embodiment of the present disclosure. As shown in fig. 2 (for simplicity of illustration, the connection relationship between the signal acquisition circuit 11 and the feedback control circuit 13 is not shown), the signal quantization circuit 12 includes: a signal storage circuit 120 and a comparator 110;

the signal storage circuit 120 is connected to the signal acquisition circuit 11 and the first input end of the comparator 110, and is configured to acquire and store a second signal according to control of the second control signal sent by the feedback control circuit 13 when the signal acquisition circuit 11 resets;

the first input end of the comparator 110 is connected with the signal storage circuit 120, the second input end is connected with the signal acquisition circuit 11, and the output end of the comparator 110 is used as the output end of the pulse sequence sensor pixel unit; the comparator 110 is configured to receive the first signal, determine a target signal according to a relationship between the first signal and the second signal, and output the target signal through the output terminal OUT according to control of the set signal Reset.

Alternatively, the comparator may be a double-ended input single-ended output comparator, where the first input terminal may be a positive input terminal INP, the second input terminal may be a negative input terminal INN, and the output time of the output terminal OUT is controlled by a set signal Reset; in the embodiment, the second signal is stored in the signal storage circuit, and when the second input end of the comparator receives the first signal, the stored second signal is input into the first input end, so that the target signal output by the comparator is determined based on the second signal and the first signal.

As shown in fig. 2, further, the signal storage circuit 120 includes: a first switching transistor 106, a second switching transistor 108, a third switching transistor 109, and a capacitor 107;

the first switching transistor 106 and the third switching transistor 109 are turned on or off simultaneously according to the control of the second control signal, and the second switching transistor 108 is turned on or off according to the control of the second control signal and is opposite to the state of the first switching transistor 106;

the capacitor 107 is used for collecting and storing the second signal when the first switching transistor 106 and the third switching transistor 109 are turned on, and inputting the difference between the second signal and the reference signal to the first input terminal of the comparator when the second switching transistor 108 is turned on.

As can be seen from fig. 2, the connection relationship between the respective elements included in the signal storage circuit 120 is as follows: the drain electrode of the first switching transistor 106 is connected with the signal acquisition circuit 11, the source electrode is connected with one end of the capacitor 107, and the grid electrode is connected with the feedback control circuit 13; the drain of the first switching transistor 106 is connected to the first input terminal of the comparator 110 as the output terminal of the signal storage circuit 120;

the drain electrode of the second switching transistor 108 is connected with the other end of the capacitor 107, the source electrode is grounded GND, and the grid electrode is connected with the feedback control circuit 13;

The drain of the third switching transistor 109 is connected to the other end of the capacitor 107, the source is connected to the reference signal Vref, and the gate is connected to the feedback control circuit 13;

one end of the capacitor 107 is connected to the source of the first switching transistor 106, and the other end is connected to the drain of the second switching transistor 108 and the drain of the third switching transistor 109, respectively.

In this embodiment, when the first switching transistor 106 and the third switching transistor 109 are turned on, one section of the capacitor 107 is connected to the signal acquisition circuit 11, and the other section is connected to the reference signal Vref, so as to acquire and store the second signal output by the signal acquisition circuit 11; in some alternative embodiments, the first switching transistor 106, the third switching transistor 109 and the second switching transistor 108 are turned on or off according to the control of the same second control signal SC, so as to realize that the second switching transistor 108 is opposite to the conduction between the drain of the third switching transistor 109 and the capacitor 107, in an example, the first switching transistor 106 is an N-type transistor, the second switching transistor 108 is a P-type transistor, and the third switching transistor 109 is an N-type transistor; alternatively, the first transistor switching device 106 is a P-type transistor, the second transistor switching device 108 is an N-type transistor, and the third transistor switching device 109 is a P-type transistor; accordingly, the second control signal SC may control the first switching transistor 106 and the third switching transistor 109 to be on at the same time, while the second switching transistor 108 is off; the first switching transistor 106 and the third switching transistor 109 may also be controlled to be off, while the second switching transistor 108 is on.

Alternatively, the comparator 110 determines the target signal according to a relationship between the difference signal input from the first input terminal and the first signal, and outputs the target signal according to control of an external trigger signal.

Wherein the difference signal is determined based on a difference between the second signal stored in the capacitor and the reference signal.

In the present embodiment, a difference signal is determined by a difference between the second signal and the reference signal, and a target signal is determined based on a relationship between the difference signal and the first signal, for example, in one example, the difference signal=vreset (second signal) -Vref (reference signal); when the first signal Vss is greater than the difference signal (Vss > (Vreset-Vref)), the target signal output by the comparator is 0; when the first signal Vss is smaller than the difference signal (Vss < (Vreset-Vref)), the target signal output by the comparator is 1.

Fig. 3-1 is a schematic diagram of a feedback control circuit in a pixel unit of a pulse train sensor according to an exemplary embodiment of the present disclosure. As shown in fig. 3-1 (for simplicity of illustration, the connection relationship between the signal acquisition circuit 11 and the signal quantization circuit 12 is not shown), the feedback control circuit 13 includes: a first D flip-flop 111 and a second D flip-flop 112;

The D end of the first D trigger 111 is connected with the signal quantization circuit 12, receives a target signal, the Q end is connected with the signal acquisition circuit 11 and the D end of the second D trigger, locks the signal state of the D end to the Q end according to the control of the first clock signal CK1, and outputs a first control signal RD to the signal acquisition circuit 11 according to the signal state;

the D end of the second D flip-flop 112 is connected to the Q end of the first D flip-flop 111; the Q terminal is connected to the signal quantization circuit 12, locks the signal state of the D terminal to the Q terminal according to the control of the second clock signal CK2, and outputs the second control signal SD to the signal quantization circuit 12 according to the signal state.

In this embodiment, the output Q terminal of the first D flip-flop 111 is connected to the D terminal of the second D flip-flop 112, so that the second D flip-flop 112 necessarily operates after the first D flip-flop 111; the first D flip-flop 111 and the second D flip-flop 112 output the first control signal RD and the second control signal SC, respectively, and the first clock signal CK1 and the second clock signal CK2 control output timings of the first control signal RD and the second control signal SC, thereby realizing control of the signal acquisition circuit 11 and the signal quantization circuit 12.

In addition, since the output timings of the first control signal RD and the second control signal SC are controlled by the first clock signal CK1 and the second clock signal CK2, the first D flip-flop 111 and the second D flip-flop 112 in the feedback control circuit 13 may be connected in parallel in addition to the above connection manner, as shown in fig. 3-2 (for simplifying the display, the connection relationship between the signal acquisition circuit 11 and the signal quantization circuit 12 is not shown in the drawing), and fig. 3-2 is a schematic diagram of a structure of the feedback control circuit in the pulse sequence sensor pixel unit according to another exemplary embodiment of the present disclosure. In this embodiment, the feedback control circuit 13 includes: a first D flip-flop 111 and a second D flip-flop 112;

The D end of the first D flip-flop 111 is connected to the signal quantization circuit 12, receives the target signal, the Q end is connected to the signal acquisition circuit 11, locks the signal state of the D end to the Q end according to the control of the first clock signal CK1, and outputs the first control signal RD to the signal acquisition circuit 11 according to the signal state;

the D terminal of the second D flip-flop 112 is connected to the signal quantizing circuit 12; the Q terminal is connected to the signal quantization circuit 12, locks the signal state of the D terminal to the Q terminal according to the control of the second clock signal CK2, and outputs the second control signal SC to the signal quantization circuit 12 according to the signal state.

Fig. 4 is a schematic diagram of a signal acquisition circuit in a pixel unit of a pulse train sensor according to an exemplary embodiment of the present disclosure. As shown in fig. 4 (connection relationship between the feedback control circuit 13 and the signal quantization circuit 12 is not shown in the drawing), the signal acquisition circuit 11 includes: a photodiode 101, a reset transistor 102, and an auxiliary circuit 130;

a reset transistor 102 having a source connected to the photodiode 101, a drain connected to the power supply module Vdd, and a gate connected to the feedback control circuit 13; for controlling the on or off according to the first control signal RD sent from the feedback control circuit 13 and controlling whether or not the photodiode 101 is on with the power supply circuit Vdd by the on or off of the reset transistor 102.

In this embodiment, the reset transistor 102 performs the reset control on the photodiode 101 according to the first control signal RD output by the feedback control circuit 13, thereby performing the reset control on the photodiode 101 in the pixel unit.

When the first control signal RD is at a high level, the reset transistor 102 is closed, and the photodiode 101 performs reset; when the first control signal RD is at a low level, the reset transistor 102 is turned off, and the photodiode 101 stops resetting. As can be seen from fig. 2, the first control signal RD is determined by the target signal output from the signal quantization circuit 12, and in a normal case, the first control signal RD is at a high level when the target signal is at a high level; when the target signal is at a low level, the first control signal RD is at a low level.

A photodiode 101 having an anode grounded and a cathode connected to a source of the reset transistor 102 and outputting a signal; receiving an optical signal to generate an opto-electric charge for an exposure period while the reset transistor 102 is turned off; when the reset transistor 102 is closed, reset is performed.

A photodiode is a photodetector capable of converting light into a current or voltage signal depending on the manner of use. The die often uses a PN junction with photosensitive characteristics, is very sensitive to light changes, has unidirectional conductivity, and changes electrical characteristics when different light intensities are used, so that the intensity of the light can be used to change the voltage or current in the circuit.

The auxiliary circuit 130 is connected to the cathode of the photodiode 101 for outputting the second signal when the photodiode 101 is reset or outputting the first signal according to a potential change of the photodiode 101.

Optionally, the first signal and the second signal may comprise at least one of the following signals: pulse signals, potential signals, values with limits, etc.

In some alternative embodiments, the auxiliary circuit 130 includes a source follower transistor 103 and a pixel select transistor 104;

the gate of the source follower transistor 103 is connected to the cathode of the photodiode 101, the source is connected to the pixel selection transistor 104, and the drain is connected to the power supply module Vdd; for detecting and following the potential change of the photodiode 101, determining a first signal or a second signal;

the pixel selection transistor 104 has a drain connected to the source of the source follower transistor 103, a source connected to the signal quantization circuit 12, a gate connected to the external control signal v_sel, and determines whether to output the first signal or the second signal according to control of the external control signal v_sel.

In this embodiment, the gate terminal of the source follower transistor 103 is connected to the photodiode 101, and follows the potential change of the photodiode 101 to obtain a potential signal, and the pixel select transistor 104 selects whether to output a target signal or a reset signal according to the control of an external control signal v_sel, where the external control signal v_sel may be an external clock signal or an external pulse signal, etc.; the pixel selection transistor may be controlled to output the first signal or the second signal based on the timing transmission signal of the external clock circuit.

Optionally, the auxiliary circuit 130 may also include a bias transistor 105;

the drain of the bias transistor 105 is connected with the source of the pixel selection transistor 104, the source is grounded GND, and the gate is connected with an external conduction signal Vd; for providing a stable bias current for the pixel select transistor 104.

In this embodiment, a bias transistor 105 is disposed between the source of the pixel selection transistor 104 and the ground GND, the external conduction signal Vd is at a normally high level, that is, the bias transistor 105 is in a normally-on state, and at this time, the output terminal of the signal acquisition circuit 11 is between the drain of the bias transistor 105 and the source of the pixel selection transistor 104; providing a stable bias current to the pixel selection transistor 104 through the bias transistor 105 realizes providing a static reference current, so that the first signal or the second signal acquired by the signal acquisition circuit 11 can be correctly output.

In some optional embodiments, the workflow of the pulse sequence image sensor pixel unit (hereinafter referred to as pixel unit) provided in the embodiments of the present disclosure is described as follows, where the target signal output by the signal quantization circuit has two states: 0 and 1,0 indicates that the target signal is low (e.g., voltage corresponding to ground GND), and 1 indicates that the target signal is high (e.g., voltage corresponding to power supply circuit Vdd). The two states of the target signal can be controlled by using the same timing sequence, so as to achieve the purpose of simplifying and effectively simplifying the timing sequence, and fig. 5 is a schematic diagram of the signal timing sequence corresponding to the pixel unit of the pulse sequence sensor according to an exemplary embodiment of the present disclosure. As shown in fig. 5, a timing diagram of the external control signal v_sel, the first clock signal CK1, the second clock signal CK2, the set signal Reset, and the target signal bit_out is shown, wherein the high level of the signal v_sel, CK1, CK2, reset indicates that the corresponding device is on or active, the high-low two-wire flip action of the target signal bit_out indicates the quantized signal output action, and the quantized signal output is 1 or 0, i.e. the high level Vdd or GND.

When the target signal state is 1, the pixel cell workflow is set forth as follows:

first, the external control signal v_sel is set from a low level to a high level, turning on the pixel selection transistor 104;

next, the signal quantization circuit 12 outputs a target signal bit_out of 1; the first clock signal CK1 is given a high level pulse operation, so that the first D flip-flop 111 is triggered to work, the level of the Q terminal is refreshed to the level of the D terminal, the Q terminal of the output terminal feeds back the high level Vdd as a first control signal RD to the gate terminal of the reset transistor 102, the photodiode 101 in the pixel unit starts to be reset, the signal acquisition module 11 outputs a reset signal (corresponding to a second signal), the target signal bit_out is turned over, and the quantized signal value 0 or 1 is output;

next, a high level pulse operation is given to the second clock signal CK2, the second D flip-flop 112 is triggered, the Q terminal level is refreshed to the D terminal level, the output terminal Q terminal thereof feeds back the high level Vdd as the second control signal SC to the gate terminals of the first switch transistor 106, the second switch transistor 108 and the third switch transistor 109 (the first switch transistor 106 and the third switch transistor 109 are closed, the second switch transistor 108 is opened), and the pixel reset signal storage channel is opened (the acquisition and storage of the reset signal in the previous reset step are started);

Next, the set signal Reset operates in high pulse, and the output terminal OUT of the comparator 110 is set to 0, i.e., to GND level;

next, a high level pulse operation is given to the first clock signal CK1 to trigger the first D flip-flop 111 to operate, the Q terminal level is refreshed to the D terminal level, the Q terminal of the output terminal feeds back the low level GND as the first control signal RD to the gate terminal of the reset transistor 102, the reset operation of the photodiode 101 in the pixel unit is ended, and the pixel unit starts the exposure operation of the next frame;

next, at the time of the exposure operation of the next frame of the pixel unit, a high level pulse operation is given to the second clock signal CK2, the trigger operation of the second D flip-flop 112 is performed, the Q terminal level is refreshed to the D terminal level, the output terminal Q terminal thereof feeds back the low level GND as the second control signal SC to the gate terminals of the first switching transistor 106, the second switching transistor 108 and the third switching transistor 109 (the first switching transistor 106 and the third switching transistor 109 are opened, the second switching transistor 108 is closed), the pixel reset signal storage channel is closed (acquisition of the reset signal is stopped), the reset signal (corresponding to the second signal in the above embodiment) is marked Vreset, and is stored in the capacitor 107;

Next, the external control signal v_sel is set from high level to low level, the pixel selection transistor 104 in the pixel is turned off, and one-time quantization output of the pixel signal is completed. The quantization operation of the pixel unit can be continued according to the next timing control.

When the target signal state is 0, the pixel unit workflow is described as follows in conjunction with the timing diagram shown in fig. 5:

first, the external control signal v_sel is set from a low level to a high level, turning on the pixel selection transistor 104;

next, the signal quantization circuit 12 outputs the target signal bit_out as 0; giving a high level pulse operation to the first clock signal CK1 to trigger the first D flip-flop 111 to operate, refreshing the Q terminal level to the D terminal level, and feeding back the low level GND as the first control signal RD to the gate terminal of the reset transistor 102 at the output terminal Q terminal thereof, wherein the photodiode 101 in the pixel unit keeps continuing the exposure operation;

next, a high level pulse operation is given to the second clock signal CK2, the second D flip-flop 112 is triggered, the Q terminal level is refreshed to the D terminal level, the output terminal Q thereof feeds back the low level Vdd as the second control signal SC to the gate terminals of the first switching transistor 106, the second switching transistor 108 and the third switching transistor 109 (the first switching transistor 106 and the third switching transistor 109 are turned off, the second switching transistor 108 is turned on), and the pixel reset signal storage channel maintains the previous off state;

Next, the set signal Reset operates in high pulse, and the output terminal OUT of the comparator 110 is set to 0, i.e., to GND level;

next, a high level pulse operation is given to the first clock signal CK1 to trigger the first D flip-flop 111 to operate, the Q terminal level is refreshed to the D terminal level, the Q terminal of the output terminal thereof feeds back the low level GND as the first control signal RD to the gate terminal of the reset transistor 102, and the exposure operation of the photodiode 101 in the pixel unit is kept unchanged;

next, a high level pulse operation is given to the second clock signal CK2, the second D flip-flop 112 is triggered, the Q terminal level is refreshed to the D terminal level, the output terminal Q terminal thereof feeds back the low level GND as the second control signal SC to the gate terminals of the first switching transistor 106, the second switching transistor 108 and the third switching transistor 109 (the first switching transistor 106 and the third switching transistor 109 are turned off, the second switching transistor 108 is turned on), the pixel reset signal storage channel maintains the previous off state, and the stored reset signal Vreset thereof is stored in the capacitor 107 to be unchanged;

next, the external control signal v_sel is set from high level to low level, the pixel selection transistor 104 in the pixel unit is turned off, and one-time quantization output of the pixel signal is completed.

In the above-described embodiment of the present disclosure, the reset signal of the pixel unit is stored in the capacitance device 107 of the signal quantization circuit 12, labeled as the second signal Vreset to the quantized signal; in the signal quantization operation performed by the signal quantization circuit 12, the signal at the negative input terminal INN of the comparator 110 is labeled as the first signal Vss. The signal difference vsig=vreset-Vss between the first sample and the second sample is the photo signal acquired by the pixel cell. The pulse sequence type sensor pixel unit provided by the embodiment of the disclosure effectively reduces KTC noise caused by pixel reset operation, and effectively eliminates quantization noise caused by device attribute change caused by process fluctuation, so that the quality of an image output by an image sensor, especially the quality of the image in a dark light environment, is effectively improved, and the signal to noise ratio of the image is greatly improved.

In another aspect of the embodiments of the present disclosure, there is also provided a pulse train type sensor including: a plurality of pulse train sensor pixel units according to any of the above embodiments.

In another aspect of the embodiments of the present disclosure, there is further provided an electronic device, including: the processor, and the memory communicatively connected with the processor, further including the pulse sequence type sensor pixel unit according to any one of the above embodiments or the pulse sequence type sensor according to the above embodiment;

The memory stores computer-executable instructions;

the processor executes computer-executable instructions stored by the memory to control the operation of the pulse train sensor pixel unit or the pulse train sensor.

The electronic device provided by the present disclosure may be incorporated as any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.

The electronic device provided by the present disclosure may be applied to any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.

Next, an electronic device according to an embodiment of the present disclosure is described with reference to fig. 6. The electronic device may be either or both of the first device and the second device, or a stand-alone device independent thereof, which may communicate with the first device and the second device to receive the acquired input signals therefrom.

Fig. 6 illustrates a block diagram of an electronic device according to an embodiment of the disclosure.

As shown in fig. 6, the electronic device includes one or more processors and memory.

The processor may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device to perform the desired functions.

The memory may store one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program products may be stored on the computer readable storage medium that can be run by a processor to implement the workflow and/or other desired functions of the pulse train sensor pixel unit of the various embodiments of the present disclosure described above.

In one example, the electronic device may further include: input devices and output devices, which are interconnected by a bus system and/or other forms of connection mechanisms (not shown).

In addition, the input device may include, for example, a keyboard, a mouse, and the like.

The output device may output various information including the determined distance information, direction information, etc., to the outside. The output device may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, etc.

Of course, only some of the components of the electronic device relevant to the present disclosure are shown in fig. 6, with components such as buses, input/output interfaces, etc. omitted for simplicity. In addition, the electronic device may include any other suitable components depending on the particular application.

The basic principles of the present disclosure have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present disclosure. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, since the disclosure is not necessarily limited to practice with the specific details described.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, so that the same or similar parts between the embodiments are mutually referred to. For system embodiments, the description is relatively simple as it essentially corresponds to method embodiments, and reference should be made to the description of method embodiments for relevant points.

The block diagrams of the devices, apparatuses, devices, systems referred to in this disclosure are merely illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the disclosure to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims (11)

1. A pulse train sensor pixel cell, comprising: the device comprises a signal acquisition circuit, a signal quantization circuit and a feedback control circuit;

the signal acquisition circuit is respectively connected with the signal quantization circuit and the feedback control circuit;

the signal quantization circuit is respectively connected with the signal acquisition circuit and the feedback control circuit;

the feedback control circuit is respectively connected with the signal acquisition circuit and the signal quantization circuit.

2. The pixel cell of claim 1, wherein the signal quantization circuit comprises: a signal storage circuit and a comparator;

the signal storage circuit is connected with the signal acquisition circuit and the first input end of the comparator;

the first input end of the comparator is connected with the signal storage circuit, the second input end of the comparator is connected with the signal acquisition circuit, and the output end of the comparator is used as the output end of the pulse sequence type sensor pixel unit.

3. The pixel cell of claim 2, wherein the signal storage circuit comprises: a first switching transistor, a second switching transistor, a third switching transistor, and a capacitor;

the drain electrode of the first switching transistor is connected with the signal acquisition circuit, the source electrode of the first switching transistor is connected with one end of the capacitor, the grid electrode of the first switching transistor is connected with the feedback control circuit, and the drain electrode of the first switching transistor is used as the output end of the signal storage circuit to be connected with the first input end of the comparator;

the drain electrode of the second switching transistor is connected with the other end of the capacitor, the source electrode of the second switching transistor is grounded, and the grid electrode of the second switching transistor is connected with the feedback control circuit;

the drain electrode of the third switching transistor is connected with the other end of the capacitor, the source electrode of the third switching transistor is connected with a reference signal, and the grid electrode of the third switching transistor is connected with the feedback control circuit;

one end of the capacitor is connected with the source electrode of the first switching transistor, and the other end of the capacitor is connected with the drain electrode of the second switching transistor and the drain electrode of the third switching transistor respectively.

4. A pixel cell according to any one of claims 1-3, wherein the feedback control circuit comprises: a first D flip-flop and a second D flip-flop;

The D end of the first D trigger is connected with the signal quantization circuit, and the Q end of the first D trigger is connected with the signal acquisition circuit and the D end of the second D trigger;

the D end of the second D trigger is connected with the Q end of the first D trigger; and the Q end is connected with the signal quantization circuit.

5. A pixel cell according to any one of claims 1-3, wherein the feedback control circuit comprises: a first D flip-flop and a second D flip-flop;

the end D of the first D trigger is connected with the signal quantization circuit, and the end Q is connected with the signal acquisition circuit;

the D end of the second D trigger is connected with the signal quantization circuit; and the Q end is connected with the signal quantization circuit.

6. A pixel cell according to any one of claims 1-3, wherein the signal acquisition circuit comprises: a photodiode, a reset transistor, and an auxiliary circuit;

the source electrode of the reset transistor is connected with the photodiode, the drain electrode of the reset transistor is connected with the power supply module, and the grid electrode of the reset transistor is connected with the feedback control circuit;

the anode of the photodiode is grounded, and the cathode of the photodiode is connected with the source electrode of the reset transistor;

the auxiliary circuit is connected with the cathode of the photodiode.

7. The pixel cell of claim 6, wherein the auxiliary circuit comprises a source follower transistor and a pixel select transistor;

the grid electrode of the source following transistor is connected with the cathode of the photodiode, the source electrode of the source following transistor is connected with the pixel selection transistor, and the drain electrode of the source following transistor is connected with the power supply module;

the drain electrode of the pixel selection transistor is connected with the source electrode of the source following transistor, the source electrode is connected with the signal quantization circuit, and the grid electrode is connected with an external control signal.

8. The pixel cell of claim 7, wherein the auxiliary circuit further comprises a bias transistor;

the drain electrode of the bias transistor is connected with the source electrode of the pixel selection transistor, the source electrode is grounded, and the grid electrode is connected with an external conduction signal.

9. A pulse train sensor, comprising: a plurality of pulse train sensor pixel units according to any one of claims 1-8.

10. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor, further comprising a pulse train sensor pixel unit according to any one of claims 1-8 or a pulse train sensor according to claim 9;

The memory stores computer-executable instructions;

the processor executes computer-executable instructions stored by the memory to control the operation of the pulse train sensor pixel unit or the pulse train sensor.

11. The electronic device of claim 10, wherein the electronic device is incorporated as any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.