CN115988344A

CN115988344A - Event detection pixel circuit, event image sensor, and electronic device

Info

Publication number: CN115988344A
Application number: CN202211695096.9A
Authority: CN
Inventors: 黄猷淳; 孙伯伟; 陈永福
Original assignee: Egis Technology Inc
Current assignee: Egis Technology Inc
Priority date: 2022-05-30
Filing date: 2022-12-28
Publication date: 2023-04-18
Also published as: CN115988301A; TW202348013A; TWI822527B; WO2023231405A1; TW202348015A; WO2023231381A1

Abstract

The present disclosure provides an event detection pixel circuit, an event image sensor, and an electronic apparatus. The event detection pixel circuit includes: the device comprises a single-photon avalanche diode, a data generation unit, a data register unit and a comparison unit, wherein the single-photon avalanche diode is configured to detect an optical signal and output an electric pulse signal; the data generation unit is configured to generate first data corresponding to the light intensity based on a count of the electric pulse signal output by the single photon avalanche diode; the data registering unit is configured to register second data; the comparison unit is configured to compare the first data and the second data to output an event detection result.

Description

Event detection pixel circuit, event image sensor, and electronic device

Priority is claimed for this application from U.S. provisional patent application serial No. 63/346,913, filed 30/05/2022, 09/19/2022, and U.S. provisional patent application serial No. 63/412,889, filed 04/2022, all of which are incorporated herein by reference in their entirety.

Technical Field

Embodiments of the present disclosure relate to an event detection pixel circuit, an event image sensor, and an electronic apparatus.

Background

An Event-based Camera (also known as a Dynamic Vision Sensor (DVS)) is an imaging Sensor that can respond to local brightness changes (events). The conventional event camera performs light detection through a conventional photodiode, the detection sensitivity of the conventional photodiode is low, and when light to be detected is weak, the conventional photodiode may not detect the light to be detected, so that the sensitivity of event detection of the conventional event camera is low.

Disclosure of Invention

In view of at least one of the above problems, at least one embodiment of the present disclosure provides an event detection pixel circuit, including: the device comprises a single photon avalanche diode, a data generation unit, a data register unit and a comparison unit, wherein the single photon avalanche diode is configured to detect an optical signal and output an electric pulse signal; the data generation unit is configured to generate first data corresponding to light intensity based on a count of electric pulse signals output by the single photon avalanche diode; the data registering unit is configured to register second data; the comparison unit is configured to compare the first data and the second data to output an event detection result.

For example, in an event detection pixel circuit provided in at least one embodiment of the present disclosure, the first data is data corresponding to light intensity of a first counting period, and the data generation unit is further configured to generate the second data corresponding to light intensity of a second counting period based on counting of an electric pulse signal output by the single photon avalanche diode; the second count period is earlier than the first count period.

For example, in an event detection pixel circuit provided in at least one embodiment of the present disclosure, the data generation unit includes a first data generation subunit and a second data generation subunit; the data register unit comprises a first data register subunit and a second data register subunit; the first data registering subunit is configured to register data generated by the first data generating subunit; the second data registering subunit is configured to register the data generated by the second data generating subunit; the first data generation subunit and the second data generation subunit alternately work; and the comparing unit is configured to compare the first data generated by the first data generating subunit with the second data registered by the second data registering subunit, or compare the first data generated by the second data generating subunit with the second data registered by the first data registering subunit.

For example, in an event detection pixel circuit provided in at least one embodiment of the present disclosure, the first data generation subunit and the first data registration subunit are integrated into a first pulse count register; and the second data generating subunit and the second data registering subunit are integrated into a second pulse count register.

For example, in an event-detecting pixel circuit provided in at least one embodiment of the present disclosure, each of the first pulse count register and the second pulse count register is configured to: switching between a count mode in which the electric pulse signals are counted and the first data are generated and a register mode in which the second data are registered, according to a switching signal; and resetting at the start of each counting period in the counting mode in accordance with a reset signal.

For example, in an event detection pixel circuit provided in at least one embodiment of the present disclosure, in a case where the first pulse count register operates in the count mode in the first count period or the second count period and the second pulse count register operates in the register mode in the first count period or the second count period, in response to the event detection result indicating that a difference between the first data and the second data is equal to or greater than a first threshold value or indicating that a difference between the second data and the first data is equal to or greater than a second threshold value, in a next count period adjacent to the first count period or the second count period, the first pulse count register switches from the count mode to the register mode, and the second pulse count register switches from the register mode to the count mode.

For example, in an event detection pixel circuit provided by at least one embodiment of the present disclosure, the data generation unit is configured to count the electric pulse signals output by the single photon avalanche diode to obtain a first pulse count value; and the first data is the first pulse count value.

For example, in an event detection pixel circuit provided in at least one embodiment of the present disclosure, in response to the event detection result indicating that a difference between the first data and the second data is equal to or greater than a first threshold or indicating that a difference between the second data and the first data is equal to or greater than a second threshold, after the comparison unit acquires the second data from the data registration unit, the data generation unit outputs the first data to the data registration unit to update the second data to the first data.

For example, in an event detection pixel circuit provided in at least one embodiment of the present disclosure, the data generation unit is configured to generate the first data based on a clock count value of a clock signal within a period in which the single photon avalanche diode outputs a first predetermined number of electric pulse signals.

For example, in an event detection pixel circuit provided in at least one embodiment of the present disclosure, the data generation unit is configured to generate the first data based on a pulse count value of an electric pulse signal output by the single photon avalanche diode for a period in which a second predetermined number of clock signals are output.

For example, in an event detection pixel circuit provided in at least one embodiment of the present disclosure, the comparison unit is configured to: when the difference between the first data and the second data is larger than or equal to a first threshold value, outputting a first result; when the difference between the second data and the first data is larger than or equal to a second threshold value, outputting a second result; outputting a third result when a difference between the first data and the second data is less than the first threshold and a difference between the second data and the first data is less than the second threshold; the event detection result is one of the first result, the second result, and the third result.

At least one embodiment of the present disclosure provides an event image sensor, including a plurality of event detection pixel units arranged in an array, wherein each event detection pixel unit includes an event detection pixel circuit according to any one embodiment of the present disclosure.

For example, at least one embodiment of the present disclosure provides an event image sensor further including: a row decoder and a row arbiter, wherein each of the event detection pixel units further includes an output request circuit configured to output a request signal to the row arbiter based on an event detection result output by the event detection pixel circuit indicating that a difference between the first data and the second data is equal to or greater than a first threshold or indicating that a difference between the second data and the first data is equal to or greater than a second threshold; the row arbiter is configured to arbitrate to determine a target event detection pixel unit upon receiving a request signal output from at least one of the plurality of event detection pixel units, and control the row decoder to output a row selection signal corresponding to the target event detection pixel unit.

At least one embodiment of the present disclosure also provides an event image sensor, including a plurality of event detection pixel units arranged in an array and a reading circuit, wherein each event detection pixel unit includes an event detection pixel circuit, the event detection pixel circuit includes a single photon avalanche diode configured to detect an optical signal and output an electrical pulse signal, a data generation unit, and a data registration unit; the data generation unit is configured to generate first data corresponding to light intensity based on a count of electric pulse signals output by the single photon avalanche diode; the data registering unit is configured to register second data; the reading circuit includes a comparison unit configured to compare first data and second data output from each of at least two of the plurality of event detection pixel units in a time-sharing manner to output a corresponding event detection result.

For example, in an event image sensor provided in at least one embodiment of the present disclosure, the first data is data corresponding to light intensity of a first counting period, and the data generation unit is further configured to generate the second data corresponding to light intensity of a second counting period based on counting of the electric pulse signal output by the single photon avalanche diode; the second count period is earlier than the first count period.

For example, in an event image sensor provided in at least one embodiment of the present disclosure, the data generation unit includes a first data generation subunit and a second data generation subunit; the data register unit comprises a first data register subunit and a second data register subunit; the first data registering subunit is configured to register data generated by the first data generating subunit; the second data registering subunit is configured to register data generated by the second data generating subunit; the first data generation subunit and the second data generation subunit alternately work; and the first data and the second data output by each event detection pixel unit are respectively the first data generated by the first data generation subunit and the second data registered by the second data registration subunit, or are respectively the first data generated by the second data generation subunit and the second data registered by the first data registration subunit.

For example, in an event image sensor provided in at least one embodiment of the present disclosure, the first data generating subunit and the first data registering subunit are integrated into a first pulse count register; and the second data generating subunit and the second data registering subunit are integrated into a second pulse count register.

For example, in an event image sensor provided in at least one embodiment of the present disclosure, each of the first pulse count register and the second pulse count register is configured to: switching between a count mode in which the electric pulse signals are counted and the first data are generated and a register mode in which the second data are registered, according to a switching signal; and resetting at the start of each counting period in the counting mode in accordance with a reset signal.

For example, in an event image sensor provided in at least one embodiment of the present disclosure, in a case where the first pulse count register operates in the counting mode in the first counting period or the second counting period and the second pulse count register operates in the registering mode in the first counting period or the second counting period, in a next counting period adjacent to the first counting period or the second counting period, the first pulse count register is switched from the counting mode to the registering mode, and the second pulse count register is switched from the registering mode to the counting mode.

For example, in an event image sensor provided by at least one embodiment of the present disclosure, the data generation unit is configured to count the electric pulse signals output by the single photon avalanche diode to obtain a first pulse count value; and the first data is the first pulse count value.

For example, in an event image sensor provided in at least one embodiment of the present disclosure, for each of the at least two event detection pixel units, after the comparison unit acquires the second data from the data registration unit in the event detection pixel circuit of the event detection pixel unit, the data generation unit in the event detection pixel circuit of the event detection pixel unit outputs the first data to the data registration unit in the event detection pixel circuit of the event detection pixel unit to update the second data to the first data.

For example, in an event image sensor provided in at least one embodiment of the present disclosure, the data generation unit is configured to generate the first data based on a clock count value of a clock signal within a period in which the single photon avalanche diode outputs a first predetermined number of electric pulse signals.

For example, in an event image sensor provided in at least one embodiment of the present disclosure, the data generation unit is configured to generate the first data based on a pulse count value of an electric pulse signal output by the single photon avalanche diode for a period in which a second predetermined number of clock signals are output.

For example, in an event image sensor provided in at least one embodiment of the present disclosure, for each of the at least two event detection pixel units, the comparison unit is configured to: outputting a first result when a difference between the first data and the second data output by the event detection pixel unit is greater than or equal to a first threshold; outputting a second result when the difference between the second data and the first data output by the event detection pixel unit is greater than or equal to a second threshold; outputting a third result when a difference between the first data and the second data output by the event detection pixel unit is smaller than the first threshold and a difference between the second data and the first data is smaller than the second threshold; the event detection result corresponding to the event detection pixel unit is one of the first result, the second result and the third result.

For example, in an event image sensor provided in at least one embodiment of the present disclosure, the at least two event detection pixel units are located in the same column.

For example, at least one embodiment of the present disclosure provides an event image sensor further including: a row decoder, wherein each event detection pixel cell further comprises an output circuit, the row decoder configured to time-divisionally output at least two row selection signals to the at least two event detection pixel cells, respectively; for each of the at least two event detection pixel cells: the output circuit of the event detection pixel unit is configured to output the first data and the second data of the event detection pixel unit to the comparison unit under the control of the row selection signal corresponding to the event detection pixel unit.

At least one embodiment of the present disclosure also provides an electronic device including: an event image sensor according to any embodiment of the present disclosure.

According to the event detection pixel circuit, the event image sensor and the electronic device provided by any embodiment of the disclosure, the sensing output of an event is achieved by comparing the difference of data generated by counting of electric pulse signals output by a Single Photon Avalanche Diode (SPAD) in different counting time periods by utilizing the photosensitive characteristics of the SPAD, so that the event detection is realized; the single photon avalanche diode can detect single photon, so that the sensitivity of light detection can be improved, and the sensitivity of event detection is improved; because the data corresponding to the light intensity is generated by counting the electric pulse signals to detect the event, the counting range can be expanded by increasing the number of counted bits, thereby expanding the dynamic range of light intensity sensing and achieving a higher dynamic range of image operation; in addition, the electric pulse signals output by the single photon avalanche diode can be counted through a simple device, so that event detection is realized, the structure of a sensing pixel circuit can be simplified, the pixel area is reduced, the resolution is increased, and the cost is reduced.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic diagram of a single photon avalanche diode based light intensity detection pixel;

FIG. 1B is a schematic diagram of a photon detection pulse and counting period;

FIG. 1C is a graph showing the relationship between light intensity and pulse count value;

fig. 2 is a schematic block diagram of an event detection pixel circuit provided in at least one embodiment of the present disclosure;

fig. 3A is a schematic structural diagram of an event detection pixel circuit according to at least one embodiment of the present disclosure;

fig. 3B is a schematic structural diagram of another event detection pixel circuit according to at least one embodiment of the present disclosure;

FIG. 4 is a graph illustrating light intensity and signal timing for pixel-based event detection in accordance with at least one embodiment of the present disclosure;

fig. 5 is a schematic diagram of an event image sensor provided in at least one embodiment of the present disclosure;

fig. 6 is a schematic diagram of another event image sensor provided in at least one embodiment of the present disclosure;

fig. 7A is a schematic diagram of an event detection pixel circuit according to at least one embodiment of the present disclosure;

fig. 7B is a schematic structural diagram of an event detection pixel circuit according to at least one embodiment of the present disclosure;

FIG. 8 is a diagram illustrating light intensity and signal timing for frame-based event detection according to at least one embodiment of the present disclosure; and

fig. 9 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components may be omitted from the present disclosure.

At least one embodiment of the present disclosure provides an event detection pixel circuit. The event detection pixel circuit includes: the device comprises a single photon avalanche diode, a data generating unit, a data registering unit and a comparing unit. The single photon avalanche diode is configured to detect an optical signal and output an electrical pulse signal; the data generation unit is configured to generate first data corresponding to the light intensity based on a count of the electric pulse signal output by the single photon avalanche diode; the data registering unit is configured to register second data; the comparison unit is configured to compare the first data and the second data to output an event detection result.

In the event detection pixel circuit provided by the embodiment of the disclosure, the sensing output of an event is achieved by comparing the difference of data generated by counting of electric pulse signals output by the single photon avalanche diode in different counting time periods by utilizing the photosensitive characteristic of the single photon avalanche diode, so that the event detection is realized; the single photon avalanche diode can detect single photon, so that the sensitivity of light detection can be improved; in addition, unlike the conventional event camera which is limited by the operation mode of current to voltage, and thus the dynamic range is limited by the operation range of the analog circuit, in the present disclosure, since the data corresponding to the light intensity is generated by counting the electrical pulse signal for event detection, the counting range can be extended by increasing the number of bits counted, thereby increasing the dynamic range of light intensity sensing and achieving a higher dynamic range of image operation; in addition, the electric pulse signals output by the single photon avalanche diode can be counted through a simple device, so that event detection is realized, the structure of a sensing pixel circuit can be simplified, the pixel area is reduced, the resolution is increased, and the cost is reduced.

Embodiments of the present disclosure also provide an event image sensor and an electronic device. The event image sensor includes the event detection pixel circuit as described above, and is applicable to an electronic apparatus provided by the embodiments of the present disclosure, which may be a digital camera, an electronic optical device, or the like.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

Fig. 1A is a schematic diagram of a light intensity detection pixel based on a single photon avalanche diode, fig. 1B is a schematic diagram of a photon detection pulse and a counting period, and fig. 1C is a schematic diagram of a relationship between light intensity and a pulse count value.

The number of times of breakdown of the single photon avalanche diode in a fixed time period is in direct proportion to the intensity of light, so that the detection of the light intensity can be realized by recording the number of times of breakdown of the single photon avalanche diode in unit time. The principle of detecting light intensity based on a single photon avalanche diode is briefly explained below with reference to fig. 1A and 1B.

As shown in fig. 1A, the light intensity detection pixel includes a single photon avalanche diode SPAD, a quenching circuit (quenching circuit), and a counter. The anode of the single photon avalanche diode SPAD is connected to the quenching circuit and the counter, and the cathode of the single photon avalanche diode SPAD receives a bias voltage V _DD . The single photon avalanche diode SPAD can detect an optical signal and output an electric pulse signal, and when the single photon avalanche diode SPAD receives the optical signal and collapses, the single photon avalanche diode SPAD can output an electric pulse signal. Each timeAfter an electric pulse signal is output, the quenching circuit quenches and resets the single-photon avalanche diode SPAD. The counter is used for counting the electric pulse signals output by the single photon avalanche diode SPAD to obtain a pulse count value. As shown in FIG. 1B, a fixed count period T may be recorded _INT The number of photon detection pulses output by the inner single photon avalanche diode SPAD is used as a pulse counting value. As shown in fig. 1C, the larger the pulse count value, the larger the light intensity.

The dark count is an error count generated by the breakdown of the single photon avalanche diode SPAD per unit time based on a noise signal in a completely dark environment. Because the single photon avalanche diode SPAD works in a Geiger mode, an avalanche current can be triggered by both an optical signal and a noise signal, and therefore, when light intensity detection is carried out based on the single photon avalanche diode, the influence of the noise signal needs to be eliminated. Therefore, as shown in fig. 1C, the influence of the dark count needs to be removed when determining the relationship between the light intensity and the pulse count value.

Fig. 2 is a schematic block diagram of an event detection pixel circuit according to at least one embodiment of the present disclosure.

As shown in fig. 2, the event detecting pixel circuit 100 may include a single photon avalanche diode 110, a data generating unit 120, a data registering unit 130, and a comparing unit 140.

The single photon avalanche diode 110 is configured to detect an optical signal and output an electrical pulse signal; the data generation unit 120 is configured to generate first data corresponding to the light intensity based on a count of the electric pulse signal output by the single photon avalanche diode 110; the data registering unit 130 is configured to register the second data; the comparison unit 140 is configured to compare the first data and the second data to output an event detection result.

For example, the first data is data corresponding to the light intensity of the first count period. The data generation unit 120 is further configured to generate second data corresponding to light intensity of a second count period, which is earlier than the first count period, based on the count of the electric pulse signal output from the single photon avalanche diode 110, that is, the second data is previously held history data with respect to the first data.

For example, the duration of the first count period and the duration of the second count period are equal.

For example, in the embodiments of the present disclosure, the first count period and the second count period may be any two count periods as long as the second count period is satisfied earlier than the first count period. The first counting period may be a current counting period, the second counting period may be a counting period before the current counting period, and a time interval between the first counting period and the second counting period may be determined according to actual situations.

For example, in one embodiment, the data generation unit 120 includes a first data generation sub-unit and a second data generation sub-unit, and the data register unit 130 includes a first data register sub-unit configured to register data generated by the first data generation sub-unit and a second data register sub-unit configured to register data generated by the second data generation sub-unit, the first data generation sub-unit and the second data generation sub-unit alternately operate. For example, in one example, the second data generating subunit is configured to generate second data corresponding to the light intensity of the second counting period based on the count of the electric pulse signal output by the single photon avalanche diode 110, the second data registering subunit may register the second data, the first data generating subunit is configured to generate first data corresponding to the light intensity of the first counting period based on the count of the electric pulse signal output by the single photon avalanche diode 110, at this time, the comparing unit 140 is configured to compare the first data generated by the first data generating subunit and the second data registered by the second data registering subunit; in another example, the first data producing subunit is configured to generate second data corresponding to the light intensity of the second counting period based on the count of the electric pulse signal output by the single photon avalanche diode 110, the first data registering subunit may register the second data, the second data producing subunit is configured to generate first data corresponding to the light intensity of the first counting period based on the count of the electric pulse signal output by the single photon avalanche diode 110, and at this time, the comparing unit 140 is configured to compare the first data produced by the second data producing subunit and the second data registered by the first data registering subunit.

For example, the first data generating subunit and the second data generating subunit may be implemented as any digital device that can perform counting, such as a counter or the like; the first data registering sub-unit and the second data registering sub-unit may be implemented as any digital devices that can perform storage, for example, registers, etc.

In the disclosure, as the digital counting device is adopted to count the electric pulse signals output by the single photon avalanche diode, and the digital registering device is adopted to register the counted data, the counting range of the digital counter and the registering range of the digital register are larger, even under the condition of larger light intensity, the digital counter can accurately sense the light intensity, so that the dynamic range of the light intensity is larger; in addition, by increasing the bit number of the digital counter and the digital register, the counting and registering range can be expanded, so that the dynamic range of the light intensity is expanded, and different application scenes are met. In addition, the digital counting device and the digital register device can be reduced along with the reduction of the manufacturing process technology, thereby realizing the pixel micro design and reducing the pixel area.

Fig. 3A is a schematic structural diagram of an event detection pixel circuit according to at least one embodiment of the present disclosure, fig. 3B is a schematic structural diagram of another event detection pixel circuit according to at least one embodiment of the present disclosure, and fig. 4 is a schematic structural diagram of light intensity and signal timing of a pixel-based event detection according to at least one embodiment of the present disclosure.

As shown in fig. 3A and 3B, in one embodiment, the first data generation subunit and the first data register subunit are integrated into a first pulse count register 201, and the second data generation subunit and the second data register subunit are integrated into a second pulse count register 202.

For example, each of the first pulse count register 201 and the second pulse count register 202 is configured to: switching between a counting mode and a registering mode according to the switching signal, wherein in the counting mode, the electric pulse signal is counted and first data is generated, and in the registering mode, second data is registered; and resetting at the start of each counting period in the counting mode in accordance with the reset signal.

For example, the first pulse count register 201 and the second pulse count register 202 alternately operate in a counting mode or a registering mode, and in the same counting period, one of the first pulse count register 201 and the second pulse count register 202 operates in the counting mode, and the other of the first pulse count register 201 and the second pulse count register 202 operates in the registering mode, that is, in a certain counting period, if the first pulse count register 201 operates in the counting mode, the second pulse count register 202 operates in the registering mode; in a counting period, if the first pulse count register 201 operates in the register mode, the second pulse count register 202 operates in the counting mode.

As shown in fig. 3A and 3B, in one example, a first pulse count register 201 is connected to the output of the single photon avalanche diode 110 to count the electrical pulse signals output by the single photon avalanche diode 110; the first pulse count register 201 is further connected to the first input terminal of the comparing unit 140, so as to send the data generated by the first data generating subunit or the data registered by the first data registering subunit to the comparing unit 140 when necessary. The first pulse count register 201 is configured to: receiving a switching signal KEEP _ A and a reset signal RST _ A; switching between a counting mode and a registering mode according to a switching signal KEEP _ A; and resetting at the start of each counting period in the counting mode according to the reset signal RST _ a. In the counting mode, the first data generation subunit in the first pulse counting register 201 counts the electrical pulse signals and generates first data; in the register mode, the first data register subunit in the first pulse count register 201 registers the second data generated by the first data generating subunit in the first pulse count register 201. The second pulse counting register 202 is connected to the output end of the single photon avalanche diode 110 to count the electric pulse signal output by the single photon avalanche diode 110; the second pulse count register 202 is also connected to a second input terminal of the comparing unit 140, so as to send the data generated by the second data generating subunit or the data registered by the second data registering subunit to the comparing unit 140 when needed. The second pulse count register 202 is configured to: receiving a switching signal KEEP _ B and a reset signal RST _ B; switching between a counting mode and a registering mode according to a switching signal KEEP _ B; and resetting at the start of each counting period in the counting mode according to the reset signal RST _ B. In the counting mode, the second data generation subunit in the second pulse counting register 202 counts the electrical pulse signals and generates first data; in the register mode, the second data register subunit in the second pulse count register 202 registers second data, which is generated by the second data generation subunit in the second pulse count register 202.

Taking the first pulse count register 201 as an example, in particular, the first pulse count register 201 is configured to: when the level of the switching signal KEEP _ a is the first switching level, the counting module works in a counting mode; when the level of the switching signal KEEP _ a is the second switching level, the register circuit operates in the register mode to execute the register function. In the count mode, the first pulse count register 201 performs a count function when the level of the reset signal RST _ a is a first reset level, and the first pulse count register 201 performs a reset function when the level of the reset signal RST _ a is a second reset level.

For example, the first switching level and the first reset level are low levels, and the second switching level and the second reset level are high levels. As shown in fig. 4, in the count period EXP (N), the count period EXP (N + 1), and the count period EXP (N + 5), the levels of the switching signal KEEP _ a are all low level 0, i.e., the first switching level, so that the first pulse count register 201 operates in the count mode; in the counting mode, when the level of the reset signal RST _ a is low level 0, i.e., a first reset level, the first pulse counting register 201 performs a counting function, and when the level of the reset signal RST _ a is high level 1, i.e., a second reset level, the first pulse counting register 201 performs a reset function, i.e., resets the data generated by the first data generating subunit, as shown in fig. 4, in the counting mode, the level of the reset signal RST _ a is high level for a period of time at the start of each counting period, thereby enabling resetting at the start of each counting period in the counting mode. In the count period EXP (N + 2), the count period EXP (N + 3), the count period EXP (N + 4), and the count period EXP (N + 6), the level of the switching signal KEEP _ a is all the high level 1, that is, the second switching level, so that the first pulse count register 201 operates in the register mode, at which the level of the reset signal RST _ a is all the low level 0 at each count period, and the reset function is not performed.

As shown in fig. 4, in the count period EXP (N), the count period EXP (N + 1), and the count period EXP (N + 5), the second pulse count register 202 operates in the register mode; the second pulse count register 202 operates in the count mode during the count period EXP (N + 2), the count period EXP (N + 3), the count period EXP (N + 4), and the count period EXP (N + 6). The operation of the second pulse count register 202 is similar to that of the first pulse count register 201, and the repetition is not repeated.

For example, in one embodiment, in a case where the first pulse count register 201 operates in the count mode for a first count period and the second pulse count register 202 operates in the register mode for the first count period, in response to the event detection result indicating that the difference between the first data and the second data is equal to or greater than a first threshold or indicating that the difference between the second data and the first data is equal to or greater than a second threshold, in a next count period adjacent to the first count period, the first pulse count register 201 switches from the count mode to the register mode, and the second pulse count register 202 switches from the register mode to the register mode; in contrast, in the case where the first pulse count register 201 operates in the register mode for the first count period and the second pulse count register 202 operates in the count mode for the first count period, in response to the event detection result indicating that the difference between the first data and the second data is equal to or greater than the first threshold or indicating that the difference between the second data and the first data is equal to or greater than the second threshold, in the next count period adjacent to the first count period, the first pulse count register 201 switches from the register mode to the count mode, and the second pulse count register 202 switches from the count mode to the register mode. That is, in response to the event detection result indicating that the difference between the first data and the second data is equal to or greater than the first threshold or indicating that the difference between the second data and the first data is equal to or greater than the second threshold, the levels of the switching signal KEEP _ a and the switching signal KEEP _ B are inverted. Without contradiction, the description of this paragraph for the first count period also applies to the second count period, i.e. the first count period of this paragraph may also be replaced by the second count period.

In addition, in response to the event detection result indicating that the difference between the first data and the second data is smaller than the first threshold and indicating that the difference between the second data and the first data is smaller than the second threshold, in a next counting period adjacent to the first counting period, the operating modes of the first pulse counting register 201 and the second pulse counting register 202 when the first counting period is still maintained are unchanged, that is, in the first counting period, if the first pulse counting register 201 operates in the counting mode and the second pulse counting register 202 operates in the register mode, in the next counting period adjacent to the first counting period, the first pulse counting register 201 still maintains operating in the counting mode and the second pulse counting register 202 still maintains operating in the register mode; in the first counting period, if the first pulse counting register 201 works in the register mode and the second pulse counting register 202 works in the counting mode, the first pulse counting register 201 still keeps working in the register mode and the second pulse counting register 202 still keeps working in the counting mode in the next counting period adjacent to the first counting period. Without contradiction, the description of this paragraph for the first count period also applies to the second count period, i.e. the first count period of this paragraph may also be replaced by the second count period.

In fig. 4, the data transmitted from the first pulse count register 201 to the comparison unit 140 is denoted as CNT _ a, the data transmitted from the second pulse count register 202 to the comparison unit 140 is denoted as CNT _ B, and in a certain counting period EXP (X), if the first pulse count register 201 operates in the counting mode, the generated data corresponding to the light intensity of the counting period EXP (X) is denoted as CNT _ a (X); if the second pulse count register 202 operates in the count mode, the generated data corresponding to the light intensity of the count period EXP (X) is denoted as CNT _ B (X).

As shown in fig. 4, if the counting period EXP (N) is the current counting period, i.e. the first counting period is the counting period EXP (N), as can be seen from fig. 4, the second counting period is the counting period EXP (N-K). In the counting period EXP (N), since the level of the switching signal KEEP _ a is low level 0 and the level of the switching signal KEEP _ B is high level 1, the first pulse counting register 201 operates in the counting mode, the first pulse counting register 201 counts the electric pulse signal output by the single photon avalanche diode to generate the data CNT _ a (N) corresponding to the light intensity of the counting period EXP (N), and the second pulse counting register 202 operates in the register mode, which is configured to register the data CNT _ B (N-K) corresponding to the light intensity of the counting period EXP (N-K). In the counting period EXP (N), the data CNT _ a (N) is the first data, the data CNT _ B (N-K) is the second data, and since the difference between the data CNT _ a (N) and the data CNT _ B (N-K) is smaller than the first threshold CNTth1, in the next counting period EXP (N + 1) adjacent to the counting period EXP (N), the operation mode of the first pulse counting register 201 does not change, i.e. still operates in the counting mode, and the operation mode of the second pulse counting register 202 does not change, i.e. still operates in the register mode.

As shown in fig. 4, after the end of the count period EXP (N), the current count period becomes the count period EXP (N + 1), and at this time, the first count period is the count period EXP (N + 1), and as can be seen from fig. 4, the second count period is still the count period EXP (N-K). In the counting period EXP (N + 1), the level of the switching signal KEEP _ a is still maintained at low level 0, the level of the switching signal KEEP _ B is still maintained at high level 1, the first pulse counting register 201 operates in the counting mode, the first pulse counting register 201 counts the electric pulse signal output by the single photon avalanche diode to generate data CNT _ a (N + 1) corresponding to the light intensity of the counting period EXP (N + 1), and the second pulse counting register 202 operates in the register mode, and is configured to register the data CNT _ B (N-K). In the counting period EXP (N + 1), the data CNT _ a (N + 1) is the first data, the data CNT _ B (N-K) is the second data, and since the difference between the data CNT _ a (N + 1) and the data CNT _ B (N-K) is greater than the first threshold CNTth1, the operation mode of the first pulse counting register 201 is switched from the counting mode to the registering mode, and the operation mode of the second pulse counting register 202 is switched from the registering mode to the counting mode in the next counting period EXP (N + 2) adjacent to the counting period EXP (N + 1).

As shown in fig. 4, after the end of the count period EXP (N + 1), the current count period becomes the count period EXP (N + 2), and at this time, the first count period is the count period EXP (N + 2), and as can be seen from fig. 4, the second count period becomes the count period EXP (N + 1). In the counting period EXP (N + 2), the level of the switching signal KEEP _ a changes to high level 1, so that the first pulse count register 201 operates in the register mode, the first pulse count register 201 registers the data CNT _ a (N + 1), the level of the switching signal KEEP _ B changes to low level 0, so that the second pulse count register 202 operates in the counting mode, and the second pulse count register 202 counts the electric pulse signal output by the single photon avalanche diode to generate the data CNT _ a (N + 2) corresponding to the light intensity of the counting period EXP (N + 2). In the counting period EXP (N + 2), the data CNT _ a (N + 2) is the first data, the data CNT _ B (N + 1) is the second data, and the difference between the data CNT _ a (N + 1) and the data CNT _ B (N + 2) is smaller than the second threshold CNTth2, so that in the next counting period EXP (N + 3) of the counting period EXP (N + 2), the first pulse counting register 201 still operates in the register mode, the second pulse counting register 202 still operates in the counting mode, and so on.

When the counting period EXP (N + 3) is over, the current counting period is changed to a counting period EXP (N + 4), and at this time, the first counting period is the counting period EXP (N + 4), as can be seen from fig. 4, the second counting period is the counting period EXP (N + 1), and in the counting period EXP (N + 4), the level of the switching signal KEEP _ a is high level 1, so that the first pulse counting register 201 operates in the register mode, the first pulse counting register 201 registers the data CNT _ a (N + 1), the level of the switching signal KEEP _ B is low level 0, so that the second pulse counting register 202 still operates in the counting mode, and the second pulse counting register 202 counts the electric pulse signal output by the avalanche single photon diode to generate the data CNT _ a (N + 4) corresponding to the light intensity of the counting period EXP (N + 4). In the counting period EXP (N + 4), the data CNT _ a (N + 4) is the first data, the data CNT _ B (N + 1) is the second data, and since the difference between the data CNT _ a (N + 1) and the data CNT _ B (N + 4) is greater than the second threshold CNTth2, the first pulse count register 201 is switched from the register mode to the register mode, the second pulse count register 202 is switched from the register mode to the register mode, and so on in the next counting period EXP (N + 5) adjacent to the counting period EXP (N + 4).

For example, in the register mode, when the first data register subunit in the first pulse count register 201 registers the switching signal KEEP _ a changing from low level to high level, the first data generating subunit generates data; similarly, in the register mode, the second data register subunit in the second pulse count register 202 registers the data generated by the second data generating subunit when the switching signal KEEP _ B changes from the low level to the high level.

Note that in the embodiment of the present disclosure, "a difference between a and B" indicates a difference value of a minus B, for example, "a difference between first data and second data" indicates a difference value of the first data minus the second data.

For example, in one embodiment, the levels of the switching signal KEEP _ a and the switching signal KEEP _ B are inverted every counting period, for example, each counting period may be one frame (frame).

For example, in some embodiments, the data generation unit 120 may be implemented as a counter, and the data registration unit 130 may be implemented as a register, the counter being fixed to generate the first data, and the register being fixed to register the second data.

In the present disclosure, the electric pulse signal output by the single photon avalanche diode 110 can be directly counted, and the pulse count value is used to represent the light intensity, the larger the pulse count value is, the stronger the light intensity is, and the light intensity detection can be realized only by using a simple device to count the electric pulse signal, so as to realize the event detection, thereby simplifying the hardware circuit structure and saving the pixel space. For example, in one embodiment, the data generating unit 120 is configured to count the electrical pulse signals output by the single photon avalanche diode 110 to obtain a pulse count value, i.e., the data generated by the data generating unit 120 is the pulse count value. For example, the data generating unit 120 is configured to count the electrical pulse signals output by the single photon avalanche diode 110 in a first counting period and a second counting period to obtain a first pulse count value and a second pulse count value, respectively, the first data being the first pulse count value and the second data being the second pulse count value.

For example, in one embodiment, in response to the event detection result indicating that the difference between the first data and the second data is equal to or greater than the first threshold or indicating that the difference between the second data and the first data is equal to or greater than the second threshold, after the comparison unit 140 acquires the second data from the data registration unit 130, the data generation unit 120 outputs the first data to the data registration unit 130 to update the second data to the first data.

For example, as shown in fig. 4, if the first count period is the count period EXP (N + 1), the second count period is the count period EXP (N-K). During the counting period EXP (N + 1), the first data generating sub-unit in the data generating unit 120 generates the data CNT _ a (N + 1), which is the first data, the second data registering sub-unit of the data registering unit 130 registers the data CNT _ B (N-K), which is the second data, and after the comparing unit 140 acquires the data CNT _ B (N-K) from the second data registering sub-unit of the data registering unit 130 since a difference between the data CNT _ a (N + 1) and the data CNT _ B (N-K) is greater than a first threshold CNTth1, the first data generating sub-unit in the data generating unit 120 outputs the data CNT _ a (N + 1) to the first data registering sub-unit of the data registering unit 130 such that the first data registering sub-unit registers the data CNT _ a (N + 1), thereby implementing the updating of the data CNT _ a (N + 1) (i.e., the first data) (i.e., the second data) using the data CNT _ a (N + 1) (i.e., the first data) (i.g., the second data). In the next count period EXP (N + 2) adjacent to the count period EXP (N + 1), the data CNT _ a (N + 1) serves as second data for comparison.

As mentioned above, the first data and the second data may be pulse count values (i.e. the number of photons detected by the single photon avalanche diode) directly related to the light intensity to indicate the light intensity, and may represent the light intensity in other ways than pulse count values, for example, the light intensity may be related to the frequency of the light, the stronger the light intensity, the greater the frequency of the light. Based on this, the light intensity may be indicated by generating data related to the frequency of light, for example, in another embodiment, first data and second data related to the frequency of light may be generated based on a count value of an electric pulse signal and a count value of a clock signal output by the single photon avalanche diode 110 to indicate the light intensity, and then it is determined whether an event trigger condition is satisfied based on a difference between the first data and the second data, thereby enabling event detection.

For example, in one example, the data generation unit 120 is configured to generate the data based on a clock count value of a clock signal within a period in which the single photon avalanche diode outputs the first predetermined number of electrical pulse signals. In this example, the data generation unit 120 may count the electrical pulse signals generated by the single photon avalanche diode 110 to obtain a pulse count value, and may also count the clock signals to obtain a clock count value, obtain a corresponding clock count value when the pulse count value reaches a first predetermined number, and then generate the first data or the second data based on the clock count value and the first predetermined number. In this example, each of the first and second counting periods is a period in which the single photon avalanche diode outputs the first predetermined number of electrical pulse signals, and the data generation unit 120 is configured to generate the first data or the second data based on a clock count value of the clock signal within the first counting period or the second counting period. In this example, the first and second count periods may not be equal.

For example, the first data may be a clock count value of a clock signal in a first counting period, and the second data may be a clock count value of a clock signal in a second counting period, so that a complex division circuit is avoided for calculation, the structure of the event detection pixel circuit is simplified, the pixel space is saved, and the pixel micro design is realized. When the first data or the second data is a clock count value, the smaller the first data or the second data is, the higher the frequency of light is, and thus the stronger the light intensity is.

For another example, the first data may be a ratio between the first predetermined number and a clock count value of the clock signal in the first counting period, and the second data may be a ratio between the first predetermined number and a clock count value of the clock signal in the second counting period, in which case the first data or the second data represents a frequency of the light, and the larger the first data or the second data, the higher the frequency of the light, and thus the stronger the light intensity.

For example, in another example, the data generation unit 120 is configured to generate the data based on a pulse count value of the electric pulse signal output by the single photon avalanche diode for a period in which the second predetermined number of clock signals are output. In this example, the data generation unit 120 may count the electrical pulse signals generated by the single photon avalanche diode 110 to obtain a pulse count value, and may also count the clock signals to obtain a clock count value, obtain a corresponding pulse count value when the clock count value reaches a second predetermined number, and then generate the first data or the second data based on the pulse count value and the second predetermined number. In this example, each of the first and second count periods is a period in which a second predetermined number of clock signals are output, and the data generation unit 120 is configured to generate the first data or the second data based on a pulse count value of an electric pulse signal output by the single photon avalanche diode within the first count period or the second count period. In this example, the first count period and the second count period are equal.

For example, the first data may be a pulse count value in a first counting period, and the second data may be a pulse count value in a second counting period, so that a complex division circuit is avoided for calculation, the structure of the event detection pixel circuit is simplified, the pixel space is saved, and the pixel micro-design is realized. When the first data or the second data is a pulse count value, the larger the first data or the second data is, the higher the frequency of light is, and the stronger the light intensity is.

For another example, the first data may be a ratio between a pulse count value in the first counting period and the second predetermined number, and the second data may be a ratio between a pulse count value in the second counting period and the second predetermined number, in which case, the larger the first data or the second data is, the higher the frequency of the light is, and thus the stronger the light intensity is.

It should be noted that the first predetermined number and the second predetermined number may be set according to actual situations, and the embodiment of the disclosure is not particularly limited to this.

For example, in some embodiments, the comparison unit 140 is configured to: outputting a first result when the difference between the first data and the second data is greater than or equal to a first threshold; outputting a second result when the difference between the second data and the first data is greater than or equal to a second threshold; and outputting a third result when the difference between the first data and the second data is less than the first threshold and the difference between the second data and the first data is less than the second threshold. The event detection result CMP _ OUT is one of the first result, the second result, and the third result.

In the embodiment of the present disclosure, the event camera is operated by comparing the current data (i.e., the first data) with the previously stored history data (i.e., the second data) to output the event detection result, thereby completing the event-based output.

The first result and the second result both represent results that satisfy the event-triggering condition, the first result representing an ON trigger indicating that the light intensity for the first count period is greater than the light intensity for the second count period; the first result represents an OFF trigger indicating that the light intensity of the first counting period is weaker than the light intensity of the second counting period; the third result is a result that the event triggering condition is not satisfied, and the third result indicates that Non trigger, that is, the difference in light intensity between the first counting period and the second counting period is within the threshold range, does not trigger the event.

It should be noted that, in the case where the first data or the second data is the clock count value, the first result indicates that the light intensity of the first counting period is weaker than the light intensity of the second counting period, and the second result indicates that the light intensity of the first counting period is stronger than the light intensity of the second counting period.

For example, the event detection result may include a first result value ON and a second result value OFF, the event detection result CMP _ OUT may be represented as CMP _ OUT = (OFF, ON), the first result value ON is 1 and the second result value OFF is 0 when a difference between the first data and the second data is equal to or greater than a first threshold, and at this time, the first result is represented as 01; when the difference between the second data and the first data is equal to or greater than the second threshold, the first result value ON is 0, the second result value OFF is 1, and at this time, the second result is 10; when the difference between the first data and the second data is less than the first threshold and the difference between the second data and the first data is less than the second threshold, the first result value ON and the second result value OFF are both 0, and at this time, the third result is represented as 00.

For example, the comparison unit 140 may be implemented as a comparator or the like that can implement a comparison function.

For example, in some embodiments, the first threshold and the second threshold are equal, and may not be equal. For example, the first threshold and the second threshold may be fixed values, or may be values calculated from the first data or the second data, for example, the first threshold and the second threshold may be 10%, 12.5%, 6.25%, and so on of the first data or the second data.

For example, the first threshold value and the second threshold value may be values written from outside of the event detection pixel circuit or values stored in the event detection pixel circuit.

As shown in fig. 4, in the count period EXP (N), the first data is data CNT _ a (N) and the second data is data CNT _ B (N-K), and at this time, the difference between data CNT _ a (N) and data CNT _ B (N-K) is smaller than the first threshold CNTth1, thereby outputting a third result, that is, an event detection result CMP _ OUT is 00; in the counting period EXP (N + 1), the first data is the data CNT _ a (N + 1) and the second data is the data CNT _ B (N-K), and at this time, the difference between the data CNT _ a (N + 1) and the data CNT _ B (N-K) is greater than the first threshold CNTth1, thereby outputting a first result, that is, the event detection result CMP _ OUT is 01; in the count period EXP (N + 4), the first data is the data CNT _ a (N + 4), the second data is the data CNT _ B (N + 1), and at this time, the difference between the data CNT _ a (N + 1) and the data CNT _ B (N + 4) is greater than the second threshold CNTth2, so that the second result, that is, the event detection result CMP _ OUT is 10, and so on.

For example, as shown in FIGS. 3A and 3BThe event detection pixel circuit 100 also includes a quench circuit 111, the quench circuit 111 for quenching reset of the single photon avalanche diode 110. In the example shown in fig. 3A, the quenching circuit 111 is connected to the anode of the single photon avalanche diode 110, and the cathode of the single photon avalanche diode 110 receives the bias voltage V _DD The bias voltage V _DD Is a high level voltage; in the example shown in fig. 3B, the quenching circuit 111 is connected to the cathode of the single photon avalanche diode 110, and the cathode of the single photon avalanche diode 110 receives the bias voltage V _SS The bias voltage V _SS Is a low level voltage.

It should be noted that, in a non-contradictory case, the connection mode of the quenching circuit 111 is suitable for the single photon avalanche diode shown in any one of the figures of the present disclosure.

For example, the data generation unit 120, the data registration unit 130, and/or the comparison unit 140 may be hardware, hardware and software, hardware and firmware, and any feasible combination thereof. For example, the data generating unit 120, the data registering unit 130 and/or the comparing unit 140 may be a dedicated or general circuit, a chip or a device, and may also be a combination of a processor and a memory. The embodiment of the present disclosure does not limit the specific implementation forms of the above units.

At least one embodiment of the present disclosure also provides an event image sensor. Fig. 5 is a schematic diagram of an event image sensor according to at least one embodiment of the present disclosure.

As shown in fig. 5, the event image sensor 200 may include a plurality of event detection pixel units P1 arranged in an array. For example, a plurality of event detection pixel units P1 are arranged in M rows and N columns, and fig. 5 shows 4 event detection pixel units P1 (1,1), P1 (1,N), P1 (M, 1), and P1 (M, N) respectively located in a first row and first column, a first row and N column, an M row and first column, and an M row and N column. The structures of the plurality of event detection pixel units P1 may be the same, and the event detection pixel unit P1 (1,1) is described below as an example.

For example, each event detection pixel cell P1 includes an event detection pixel circuit 100 according to any of the above embodiments of the present disclosure.

For example, as shown in fig. 5, the event image sensor 200 further includes a row decoder 210, a row arbiter 220, and a reading circuit 230, and each event detection pixel unit P1 further includes an output request circuit 2001 and an output circuit 2002.

The output request circuit 2001 is configured to output a request signal to the row arbiter 220 based on the event detection result output by the event detection pixel circuit 100 indicating that the difference between the first data and the second data is equal to or greater than the first threshold or indicating that the difference between the second data and the first data is equal to or greater than the second threshold.

The row arbiter 220 is configured to arbitrate to determine a target event detection pixel cell when receiving a request signal output from at least one of the plurality of event detection pixel cells, and control the row decoder 210 to output a row selection signal corresponding to the target event detection pixel cell. The row arbiter 220 may avoid the event detection pixel units in different rows from outputting simultaneously, and avoid errors in reading data, for example, if the event detection pixel units P1 (1,1) and P1 (M, 1) in different rows output request signals to the row arbiter 220 simultaneously, the row arbiter 220 may select through its internal judgment mechanism to determine which event detection pixel unit is to be read preferentially, and if the event detection pixel unit P1 (1,1) is to be read preferentially, the event detection pixel unit P1 (1,1) is taken as the target event detection pixel unit; if the event detection pixel cell P1 (M, 1) is preferentially read, the event detection pixel cell P1 (M, 1) serves as a target event detection pixel cell.

It should be noted that the row arbiter 220 may arbitrate a plurality of target event detection pixel units, which are located in the same row, that is, may perform data reading on a plurality of event detection pixel units located in the same row at the same time. For example, if event detection pixel units P1 (1,1) and P1 (1,N) simultaneously output request signals to row arbiter 220, since event detection pixel units P1 (1,1) and P1 (1,N) are located in the same row, row arbiter 220 can arbitrate and determine that event detection pixel units P1 (1,1) and P1 (1,N) are both target event detection pixel units, so that event detection pixel units P1 (1,1) and P1 (1,N) can be simultaneously read data.

The output circuit 2002 in the target event detection pixel cell P1 is configured to receive the row selection signal output by the row decoder 210 and output a first signal or a second signal to the reading circuit 230 under the control of the row selection signal.

For example, as shown in fig. 5, the output circuit 2002 includes a first output sub-circuit and a second output sub-circuit, the event detection result includes a first result value ON and a second result value OFF, the first output sub-circuit is connected to the event detection pixel circuit 100 to receive the first result value ON, is also connected to the row decoder 210 to receive the corresponding row selection signal, and is configured to output the first signal to the reading circuit 230 under the control of the first result value ON and the corresponding row selection signal; the second output sub-circuit is connected to the event detection pixel circuit 100 to receive the second result value OFF, and is also connected to the row decoder 210 to receive the corresponding row selection signal, and is configured to output the second signal to the read circuit 230 under the control of the second result value OFF and the corresponding row selection signal.

For example, as shown in fig. 5, the first output unit includes a first transistor T1 and a second transistor T2, the second output unit includes a third transistor T3 and a fourth transistor T4, a gate of the first transistor T1 receives the first result value ON, a first pole of the first transistor T1 receives the first signal, for example, the first pole of the first transistor T1 may be grounded to receive a grounded signal as the first signal, a second pole of the first transistor T1 is connected to a first pole of the second transistor T2, a gate of the second transistor T2 is connected to the row decoder 210 through the row selection signal line RS to receive a corresponding row selection signal, a second pole of the second transistor T2 is connected to the reading circuit 230, for example, the second pole of the second transistor T2 is connected to the reading circuit 230 through the reading line D1; the gate of the third transistor T3 receives the second result value OFF, the first pole of the third transistor T3 receives the second signal, for example, the first pole of the third transistor T3 may be grounded to receive the grounded signal as the second signal, the second pole of the third transistor T3 is connected to the first pole of the fourth transistor T4, the gate of the fourth transistor T4 is connected to the row decoder 210 through the row selection signal line RS to receive the corresponding row selection signal, the second pole of the fourth transistor T4 is connected to the readout circuit 230, for example, the second pole of the fourth transistor T4 is connected to the readout circuit 230 through the readout line D2.

For example, as shown in fig. 5, the output request circuit 2001 includes an OR gate OR whose first input terminal receives the first result value ON and whose second input terminal receives the second result value OFF, and a fifth transistor T5 whose gate terminal is connected to the output terminal of the OR gate OR; a first pole of the fifth transistor T5 receives the request signal, for example, the first pole of the fifth transistor T5 may be grounded to receive a ground signal as the request signal; the second pole of the fifth transistor T5 is connected to the row arbiter 220, for example, the second pole of the fifth transistor T5 is connected to the row arbiter 220 through the request signal line RR.

For example, the event detection pixel units P1 located in the same row are connected to the same request signal line and the same row selection signal line, and as shown in fig. 5, the event detection pixel units P1 (1,1) and P1 (1,N) are connected to the same request signal line RR and the same row selection signal line RS.

For example, the event detection pixel units P1 in the same column are connected to the same readout line, and as shown in fig. 5, the event detection pixel units P1 (1,1) and P1 (M, 1) are connected to the same readout line D1 and the same readout line D2.

In the example shown in fig. 5, the way in which the reading circuit 230 reads data is based ON performing data reading when a pixel (pixel-base) satisfies an event trigger condition (i.e., ON trigger or OFF trigger). The schematic diagram of the timing of the signals for data reading in the pixel-base mode can refer to the schematic diagram shown in fig. 4. In the data reading in the pixel-base mode, in the count period in which the event detection result CMP _ OUT output by the event detection pixel circuit in the event detection pixel unit is 00, the event detection pixel unit does not output a request signal, so that the reading circuit 230 does not read data from the event detection pixel unit, whereby power consumption can be saved.

The event image sensor 200 can achieve similar or same technical effects as the aforementioned event detection pixel circuit 100, and will not be described herein again.

At least one embodiment of the present disclosure also provides an event image sensor. Fig. 6 is a schematic diagram of another event image sensor according to at least one embodiment of the present disclosure, fig. 7A is a schematic diagram of an event detection pixel circuit according to at least one embodiment of the present disclosure, and fig. 7B is a schematic diagram of a structure of an event detection pixel circuit according to at least one embodiment of the present disclosure.

As shown in fig. 6, the event image sensor 300 may include a plurality of event detection pixel units P2 arranged in an array and a reading circuit 320. For example, the plurality of event detection pixel units P2 are arranged in M rows and N columns, that is, the plurality of event detection pixel units P2 are arranged in an array to form a plurality of event detection pixel unit rows Row, as shown in fig. 6, two event detection pixel unit rows Row1 and Row M. Fig. 6 shows 4 event detection pixel units P2 (1,1), P2 (1,N), P2 (M, 1) and P2 (M, N) respectively located in the first row and first column, the first row and N column, the M row and first column, and the M row and N column. The structures of the plurality of event detection pixel units P2 may be the same, and the following description will be given taking the event detection pixel unit P2 (1,1) as an example.

For example, each event detection pixel cell P2 includes an event detection pixel circuit 3100, which is different from the event detection pixel circuit 100 shown in fig. 2 in that: the event detection pixel circuit 3100 does not include the comparison unit 140, and the remaining elements in the event detection pixel circuit 3100 are the same as the corresponding elements in the event detection pixel circuit 100.

As shown in fig. 7A, the event detection pixel circuit 3100 may also include a single-photon avalanche diode 3101, a data generating unit 3102, and a data registering unit 3103. The single photon avalanche diode 3101 is configured to detect an optical signal and output an electrical pulse signal; the data generation unit 3102 is configured to generate first data corresponding to the light intensity based on the count of the electric pulse signal output by the single photon avalanche diode; the data registration unit 3103 is configured to register second data.

For example, the first data is data corresponding to light intensity of a first counting period, and the data generating unit 3102 is further configured to generate second data corresponding to light intensity of a second counting period, which is earlier than the first counting period, based on counting of the electric pulse signal output by the single photon avalanche diode.

For example, the data generation unit 3102 includes a first data generation subunit and a second data generation subunit; the data register unit 3103 includes a first data register sub-unit and a second data register sub-unit; the first data registering subunit is configured to register data generated by the first data generating subunit; the second data register subunit is configured to register the data generated by the second data generation subunit; the first data generation subunit and the second data generation subunit alternately work; the first data and the second data output by each event detection pixel unit P2 are respectively the first data generated by the first data generation subunit and the second data registered by the second data registration subunit, or are respectively the first data generated by the second data generation subunit and the second data registered by the first data registration subunit.

As shown in fig. 7B, the first data generating subunit and the first data registering subunit are integrated into a first pulse count register 3110; the second data generation subunit and the second data register subunit are integrated into a second pulse count register 3120. Each of the first pulse count register 3110 and the second pulse count register 3120 is configured to: switching between a counting mode and a registering mode according to the switching signal, wherein in the counting mode, the electric pulse signal is counted and first data is generated, and in the registering mode, second data is registered; and resetting at the start of each counting period in the counting mode in accordance with the reset signal.

For example, as shown in fig. 7B, the first pulse count register 3110 generates and outputs data CNT _ a, and the second pulse count register 3120 generates and outputs data CNT _ B, unlike the event detection pixel circuit shown in fig. 2, the event detection pixel circuit 3100 outputs data CNT _ a and data CNT _ B. The data CNT _ a may be the first data or the second data, and accordingly, the data CNT _ B may be the second data or the first data.

For the specific operation of the first pulse count register 3110 and the second pulse count register 3120, reference may be made to the above description of the first pulse count register 201 and the second pulse count register 202, and repeated descriptions are omitted.

Fig. 8 is a diagram illustrating light intensity and signal timing for frame-based event detection according to at least one embodiment of the present disclosure.

As shown in fig. 8, the levels of the switching signal KEEP _ a and the switching signal KEEP _ B are inverted every counting period, so that the first pulse count register 3110 and the second pulse count register count the switching of the operation mode every counting period, and the event detection based on the counting period is realized, and when each counting period is one frame, the event detection based on the frame (frame) is realized.

For example, in the case where the first pulse count register 3110 operates in the count mode for the first count period and the second pulse count register 3120 operates in the register mode for the first count period, the first pulse count register 3110 is switched from the count mode to the register mode and the second pulse count register 3120 is switched from the register mode to the register mode in the next count period adjacent to the first count period. In contrast, in the case where the first pulse count register 3110 operates in the register mode for the first count period and the second pulse count register 3120 operates in the count mode for the first count period, in the next count period adjacent to the first count period, the first pulse count register 3110 is switched from the register mode to the count mode and the second pulse count register 3120 is switched from the count mode to the register mode. Without contradiction, the description of this paragraph with respect to the first count period also applies to the second count period, i.e. the first count period of this paragraph may also be replaced by the second count period.

For example, the first data and the second data are data of two adjacent count periods, for example, as shown in fig. 8, if the first count period is a count period EXP (N), the second count period is a count period EXP (N-1), the data CNT _ a (N) is the first data, and the data CNT _ B (N-1) is the second data; if the first counting period is the counting period EXP (N + 1), the second counting period is the counting period EXP (N), the data CNT _ B (N + 1) is the first data, the data CNT _ a (N) is the second data, and so on.

For example, the data generation unit 3102 is configured to count the electric pulse signals output by the single photon avalanche diode 3101 for a first count period and a second count period to obtain a first pulse count value corresponding to the first count period and a second pulse count value corresponding to the second count period, respectively, the first data being the first pulse count value and the second data being the second pulse count value.

For example, in some embodiments, the data generation unit 3102 is configured to generate the first data based on a clock count value of a clock signal within a period in which the single photon avalanche diode 3101 outputs the first predetermined number of electric pulse signals.

For example, in some embodiments, the data generation unit 3102 is configured to generate the first data based on a pulse count value of the electric pulse signal output by the single photon avalanche diode 3101 for a period in which the second predetermined number of clock signals are output.

It should be noted that the event detection pixel circuit 3100 may also include only the single-photon avalanche diode 3101 and the data generating unit 3102, that is, the data registering unit 3103 may be shifted out of the event detection pixel circuit 3100, and the multiple event detection pixel units P2 share the same data registering unit, so that the hardware size of the pixel may be further reduced, and the pixel may be further miniaturized.

As shown in fig. 6, the reading circuit 320 includes a comparison unit 3201, and the comparison unit 3201 is configured to time-divisionally compare the first data and the second data output by each of at least two event detection pixel units of the plurality of event detection pixel units P2 to output corresponding event detection results.

In the embodiment of the disclosure, the hardware size of the pixel can be further reduced by enabling a plurality of event detection pixel units to share the same comparison unit, and the pixel is further miniaturized.

For example, the comparison unit 3201 is configured to: when the difference between the first data and the second data output by the event detection pixel unit is larger than or equal to a first threshold value, outputting a first result; when the difference between the second data and the first data output by the event detection pixel unit is larger than or equal to a second threshold value, outputting a second result; and outputting a third result when the difference between the first data and the second data output by the event detection pixel unit is smaller than a first threshold value and the difference between the second data and the first data is smaller than a second threshold value. The event detection result corresponding to the event detection pixel unit is one of the first result, the second result and the third result.

For example, after the comparing unit 3201 acquires the second data from the data registering unit in the event detection pixel circuit of the event detection pixel unit, for each of the at least two event detection pixel units, the data generating unit in the event detection pixel circuit of the event detection pixel unit outputs the first data to the data registering unit in the event detection pixel circuit of the event detection pixel unit to update the second data to the first data, and the value of the updated second data is the value of the first data.

For example, in some embodiments, the at least two event detection pixel units are located in the same column, e.g., all event detection pixel units located in the same column share the same comparison unit, as shown in fig. 6, the comparison unit 3201 is configured to compare data output by each event detection pixel unit P2 located in the first column in a time-sharing manner.

Taking the event detection pixel unit P2 (1,1) as an example, in conjunction with fig. 6, 7B and 8, if the count period EXP (N) is the current count period, i.e., the first count period is the count period EXP (N), and the second count period is the count period EXP (N-1), in the count period EXP (N), since the level of the switching signal KEEP _ a is the low level 0 and the level of the switching signal KEEP _ B is the high level 1, the first pulse count register 3110 operates in the count mode, the first pulse count register 3110 counts the electric pulse signal of the single photon avalanche diode output 3101 to generate data CNT _ a (N) corresponding to the light intensity of the count period EXP (N), and the second pulse count register 3120 operates in the register mode and is configured to register the data CNT _ B (N-1) corresponding to the light intensity of the count period EXP (N-1). In the count period EXP (N), the data CNT _ a (N) is the first data, the data CNT _ B (N-1) is the second data, the event detection pixel unit P2 (1,1) outputs the data CNT _ a (N) and the data CNT _ B (N-1) to the comparison unit 3201, and since the difference between the data CNT _ a (N) and the data CNT _ B (N-1) is smaller than the first threshold CNTth1, the comparison unit 3201 outputs the event detection result CMP _ OUT as 00. If the counting period EXP (N + 1) is the current counting period, i.e. the first counting period is the counting period EXP (N + 1), and the second counting period is the counting period EXP (N), during the counting period EXP (N + 1), since the level of the switching signal KEEP _ a is high level 1 and the level of the switching signal KEEP _ B is low level 0, the first pulse counting register 3110 operates in the register mode to register the data CNT _ a (N) generated by the first pulse counting register 3110 during the counting period EXP (N), and the second pulse counting register 3120 operates in the counting mode and is configured to avalanche count the electrical pulse signal output by the single photon diode 3101 to generate the data CNT _ B (N + 1) corresponding to the light intensity of the counting period EXP (N + 1). In the count period EXP (N + 1), the data CNT _ B (N + 1) is the first data, the data CNT _ a (N) is the second data, the event detection pixel unit P2 (1,1) outputs the data CNT _ B (N + 1) and the data CNT _ a (N) to the comparison unit 3201, and since the difference between the data CNT _ B (N + 1) and the data CNT _ a (N) is greater than the first threshold CNTth1, the comparison unit 3201 outputs the event detection result CMP _ OUT of 01; by analogy, in the count period EXP (N + 4), the data CNT _ a (N + 4) is the first data, the data CNT _ B (N + 3) is the second data, the event detection pixel unit P2 (1,1) outputs the data CNT _ a (N + 4) and the data CNT _ B (N + 3) to the comparison unit 3201, and since the difference between the data CNT _ B (N + 3) and the data CNT _ a (N + 4) is greater than the second threshold CNTth2, the comparison unit 3201 outputs the event detection result CMP _ OUT of 10.

For example, as shown in fig. 6, the event image sensor 300 further includes a row decoder 330, each event detection pixel unit P2 further includes an output circuit 3104, and the row decoder 330 is configured to time-divisionally output at least two row selection signals to at least two event detection pixel units sharing the same comparison unit, respectively; for each of the at least two event detection pixel cells: the output circuit 3104 of the event detection pixel unit is configured to output the first data and the second data of the event detection pixel unit to the comparison unit 3201 under the control of the row selection signal corresponding to the event detection pixel unit.

As shown in fig. 6, in one embodiment, the output circuit 3104 may include a first switch S1 and a second switch S2, a control terminal of the first switch S1 and a control terminal of the second switch S2 being configured to be connected to the row decoder 330 through a corresponding row selection signal line RS to receive a corresponding row selection signal; the output end of the first switch S1 is connected to the first input end of the corresponding comparing unit, for example, the output end of the first switch S1 is connected to the comparing unit 3201 through the reading line D3; the output end of the second switch S2 is connected to the second input end of the corresponding comparing unit, for example, the output end of the second switch S2 is connected to the comparing unit 3201 through the reading line D4; the input terminal of the first switch S1 receives data CNT _ a, and the input terminal of the second switch S2 receives data CNT _ B.

For example, the event detection pixel units P2 located in the same row are connected to the same row selection signal line, and as shown in fig. 6, the event detection pixel units P2 (1,1) and P2 (1,N) are connected to the same row selection signal line RS.

For example, the event detection pixel cells P2 in the same column are connected to the same read line, and as shown in fig. 6, the event detection pixel cells P2 (1,1) and P2 (M, 1) are connected to the same read line D3 and the same read line D4.

In the example shown in fig. 6, the manner in which the read circuit 320 reads data is performed on a frame-base basis. The schematic diagram of the signal timing for reading data in the frame-base mode can refer to the schematic diagram shown in fig. 8. In the frame-base mode, reading data is achieved by sequentially scanning each event detection pixel cell row line by line in the event image sensor 300. In the frame-base mode, a line arbiter is not required, so that the hardware circuit configuration can be simplified.

The event image sensor 300 can achieve similar or identical technical effects to the event detection pixel circuit, and will not be described in detail herein.

The event image sensor 200 or 300 is an event camera.

The event image sensor 200 or 300 may sense light reflected by an object to be measured to perform event detection. For example, the object to be measured may be a person, an animal, a plant (e.g., a tree), an automobile, a home appliance, furniture (e.g., a table, a chair, etc.), or the like. Pixels in the event image sensor 200 or 300 may sense light reflected or emitted from an object to be detected to perform event detection, and when the light reflected or emitted from the object to be detected satisfies an event trigger condition, an image output by the event image sensor may embody a profile of the object to be detected, thereby sensing the object.

The event image sensor 200 or 300 described above may be provided on a monitoring device, an electric vehicle, or the like.

At least one embodiment of the present disclosure also provides an electronic device. Fig. 9 is a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure.

As shown in fig. 9, the electronic device 400 includes an event image sensor 401, the event image sensor 401 may be an event image sensor according to any embodiment of the present disclosure, for example, the event image sensor 200 or 300, and reference may be made to the above description of the event image sensor 200 or 300 for specific description of functions implemented by the event image sensor 401. The components and structures of the electronic device 400 shown in fig. 9 are exemplary only, and not limiting, and the electronic device 400 may include other components and structures as desired.

For example, the electronic apparatus 400 may be a digital camera, an electro-optical device, or the like.

The electronic device 400 can achieve similar or identical technical effects to those of the event image sensor, and therefore, the detailed description thereof is omitted.

At least one embodiment of the present disclosure provides an event detection pixel circuit, an event image sensor, and an electronic device, which utilize the light sensing characteristics of a single photon avalanche diode to achieve event detection output by comparing the difference of data generated by counting of electric pulse signals output by the single photon avalanche diode in different counting periods, so as to implement event detection, and the event image sensor performs imaging based on detected events, thereby implementing imaging based on events. The single photon avalanche diode can detect single photon, so that the sensitivity of light detection can be improved; because the data corresponding to the light intensity is generated by counting the electric pulse signals to detect the event, the counting range can be expanded by increasing the number of counted bits, thereby expanding the dynamic range of light intensity sensing and achieving a higher dynamic range of image operation; in addition, the electric pulse signals output by the single photon avalanche diode can be counted through a simple device, so that event detection is realized, the structure of a sensing pixel circuit can be simplified, the pixel area is reduced, the resolution is increased, and the cost is reduced; in addition, because the digital counting device is adopted to count the electric pulse signals output by the single photon avalanche diode, and the digital registering device is adopted to register the counted data, the digital counting device and the digital registering device can be reduced along with the reduction of the manufacturing process technology, thereby realizing the pixel micro-scale design and reducing the pixel area; by enabling a plurality of event detection pixel units to share the same comparison unit, the hardware size of the pixel can be further reduced, and the micro design of the pixel is further realized.

For the present disclosure, there are also the following points to be explained:

(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. An event detection pixel circuit, comprising: a single photon avalanche diode, a data generating unit, a data registering unit and a comparing unit, wherein,

the single photon avalanche diode is configured to detect an optical signal and output an electrical pulse signal;

the data generation unit is configured to generate first data corresponding to light intensity based on a count of electric pulse signals output by the single photon avalanche diode;

the data registering unit is configured to register second data;

the comparison unit is configured to compare the first data and the second data to output an event detection result.

2. The event detection pixel circuit according to claim 1, wherein the first data is data corresponding to light intensity of a first count period,

the data generation unit is further configured to generate the second data corresponding to light intensity of a second counting period based on a count of the electric pulse signal output by the single photon avalanche diode;

the second count period is earlier than the first count period.

3. The event detection pixel circuit according to claim 2,

the data generation unit comprises a first data generation subunit and a second data generation subunit;

the data register unit comprises a first data register subunit and a second data register subunit;

the first data registering subunit is configured to register data generated by the first data generating subunit;

the second data registering subunit is configured to register the data generated by the second data generating subunit;

the first data generation subunit and the second data generation subunit alternately work; and is

The comparison unit is configured to compare the first data generated by the first data generation subunit with the second data registered by the second data registration subunit, or compare the first data generated by the second data generation subunit with the second data registered by the first data registration subunit.

4. The event detection pixel circuit of claim 3,

the first data generating subunit and the first data registering subunit are integrated into a first pulse counting register; and is provided with

The second data generating subunit and the second data registering subunit are integrated into a second pulse counting register.

5. The event detection pixel circuit of claim 4, wherein each of the first and second pulse count registers is configured to:

switching between a count mode in which the electric pulse signals are counted and the first data is generated and a register mode in which the second data is registered, according to a switching signal; and

resetting at the beginning of each counting period in the counting mode in accordance with a reset signal.

6. The event detection pixel circuit of claim 5,

in a case where the first pulse count register operates in the count mode in the first count period or the second count period and the second pulse count register operates in the register mode in the first count period or the second count period, in response to the event detection result indicating that a difference between the first data and the second data is equal to or greater than a first threshold value or indicating that a difference between the second data and the first data is equal to or greater than a second threshold value, in a next count period adjacent to the first count period or the second count period, the first pulse count register switches from the count mode to the register mode, and the second pulse count register switches from the register mode to the count mode.

7. The event detection pixel circuit according to any one of claims 1 to 6,

the data generation unit is configured to count electric pulse signals output by the single photon avalanche diode to obtain a first pulse count value; and is

The first data is the first pulse count value.

8. The event detection pixel circuit according to any one of claims 1 to 6, wherein in response to the event detection result indicating that the difference between the first data and the second data is equal to or greater than a first threshold or indicating that the difference between the second data and the first data is equal to or greater than a second threshold, the data generation unit outputs the first data to the data registration unit to update the second data to the first data after the comparison unit acquires the second data from the data registration unit.

9. The event detection pixel circuit according to any one of claims 1 to 6,

the data generation unit is configured to generate the first data based on a clock count value of a clock signal within a period in which the single photon avalanche diode outputs a first predetermined number of electric pulse signals.

10. The event detection pixel circuit according to any one of claims 1 to 6,

the data generation unit is configured to generate the first data based on a pulse count value of an electric pulse signal output by the single photon avalanche diode for a period in which a second predetermined number of clock signals are output.

11. The event detection pixel circuit according to any one of claims 1 to 6, wherein the comparison unit is configured to:

when the difference between the first data and the second data is larger than or equal to a first threshold value, outputting a first result;

when the difference between the second data and the first data is larger than or equal to a second threshold value, outputting a second result;

outputting a third result when a difference between the first data and the second data is less than the first threshold and a difference between the second data and the first data is less than the second threshold;

the event detection result is one of the first result, the second result, and the third result.

12. An event image sensor includes a plurality of event detection pixel units arranged in an array,

wherein each event detection pixel cell comprises an event detection pixel circuit according to any one of claims 1 to 11.

13. The event image sensor of claim 12, further comprising: a row decoder and a row arbiter,

wherein each event detection pixel unit further comprises an output request circuit,

the output request circuit is configured to output a request signal to the row arbiter based on an event detection result output by the event detection pixel circuit indicating that a difference between the first data and the second data is equal to or greater than a first threshold or indicating that a difference between the second data and the first data is equal to or greater than a second threshold;

the row arbiter is configured to arbitrate to determine a target event detection pixel unit upon receiving a request signal output from at least one of the plurality of event detection pixel units, and control the row decoder to output a row selection signal corresponding to the target event detection pixel unit.

14. An event image sensor includes a plurality of event detection pixel units arranged in an array and a reading circuit, wherein,

each event detection pixel unit comprises an event detection pixel circuit which comprises a single photon avalanche diode, a data generation unit and a data register unit,

the data registering unit is configured to register second data;

the read circuit comprises a comparison unit which is provided with a comparator,

the comparison unit is configured to compare the first data and the second data output by each of at least two of the plurality of event detection pixel units in a time-sharing manner to output a corresponding event detection result.

15. The event image sensor according to claim 14, wherein the first data is data corresponding to light intensity of a first count period,

the second count period is earlier than the first count period.

16. The event image sensor according to claim 15, wherein the data generation unit comprises a first data generation subunit and a second data generation subunit;

The first data and the second data output by each event detection pixel unit are respectively the first data generated by the first data generation subunit and the second data registered by the second data registration subunit, or are respectively the first data generated by the second data generation subunit and the second data registered by the first data registration subunit.

17. Event image sensor according to claim 16,

the first data generation subunit and the first data register subunit are integrated into a first pulse count register; and is

18. The event image sensor according to claim 17, wherein each of the first and second pulse count registers is configured to:

switching between a count mode in which the electric pulse signals are counted and the first data are generated and a register mode in which the second data are registered, according to a switching signal; and

19. The event image sensor according to claim 18,

in a case where the first pulse count register operates in the counting mode for the first counting period or the second counting period and the second pulse count register operates in the registering mode for the first counting period or the second counting period, the first pulse count register is switched from the counting mode to the registering mode and the second pulse count register is switched from the registering mode to the counting mode in a next counting period adjacent to the first counting period or the second counting period.

20. The event image sensor according to any one of claims 14 to 19,

the data generation unit is configured to count the electric pulse signals output by the single photon avalanche diode to obtain a first pulse count value; and is provided with

The first data is the first pulse count value.

21. The event image sensor according to any one of claims 14 to 19, wherein, for each of the at least two event detection pixel units, after the comparison unit acquires the second data from the data register unit in the event detection pixel circuit of the event detection pixel unit, the data generation unit in the event detection pixel circuit of the event detection pixel unit outputs the first data to the data register unit in the event detection pixel circuit of the event detection pixel unit to update the second data to the first data.

22. The event image sensor according to any one of claims 14 to 19,

23. The event image sensor according to any one of claims 14 to 19,

24. The event image sensor according to any one of claims 14 to 19, wherein for each event detection pixel cell of the at least two event detection pixel cells, the comparison unit is configured to:

outputting a first result when a difference between the first data and the second data output by the event detection pixel unit is greater than or equal to a first threshold;

outputting a second result when the difference between the second data and the first data output by the event detection pixel unit is greater than or equal to a second threshold;

outputting a third result when a difference between the first data and the second data output by the event detection pixel unit is smaller than the first threshold and a difference between the second data and the first data is smaller than the second threshold;

the event detection result corresponding to the event detection pixel unit is one of the first result, the second result and the third result.

25. The event image sensor according to any one of claims 14 to 19, wherein the at least two event detection pixel cells are located in the same column.

26. The event image sensor of claim 25, further comprising: a row decoder, wherein,

each event detection pixel cell further comprises an output circuit,

the row decoder is configured to time-divisionally output at least two row selection signals to the at least two event detection pixel units, respectively;

for each of the at least two event detection pixel cells: the output circuit of the event detection pixel unit is configured to output the first data and the second data of the event detection pixel unit to the comparison unit under the control of the row selection signal corresponding to the event detection pixel unit.

27. An electronic device, comprising: the event image sensor according to any one of claims 12 to 26.