JP2024004564A - Signal processing device and signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing device and a signal processing method, capable of easily acquiring a video signal and a differential signal indicating that there has been a predetermined change in the video signal.

SOLUTION: A signal processing device includes: an acquisition section acquiring a value that changes with lapse of time; a counter section counting up or counting down depending on whether it is a first period or a second period in a cycle including the first period and the second period; and an output section outputting a first signal according to a value counted up by the counter section and a second signal according to a difference between a value counted up by the counter section and a value counted down by the counter section.

SELECTED DRAWING: Figure 2

COPYRIGHT: (C)2024,JPO&INPIT

Description

The present invention relates to a signal processing device and a signal processing method.

Conventionally, instead of continuously monitoring sensor values expressed as analog values, by acquiring a trigger signal when the amount of change in analog values exceeds a threshold, communication traffic can be reduced and faster response possible. There are known techniques to do this. An example of the analog value used in this technique is the amount of light detected by a photodiode. Moreover, a moving image sensor or the like can be exemplified as a sensor that handles such analog values.

In recent years, in the technical field of moving image sensors, instead of a video signal that continuously acquires multiple frame images at high speed, a signal corresponding to a change in pixel value (hereinafter referred to as a difference signal) is output. Event-based sensors that detect the movement of objects are being developed. Sensors using such technology are also called dynamic vision sensors.

According to the technology described in Non-Patent Document 1, a pixel is equipped with a logarithmic response current-voltage conversion circuit and a difference detection circuit, an event trigger is generated, and information about pixels whose values change over time is output. . Therefore, the sensor described in Non-Patent Document 1 is capable of high-speed response, can save power, and is expected to be applied to vehicles. However, such a sensor outputs only a differential signal, and requires the use of another camera in order to output a video signal. Therefore, when attempting to construct a system using a video signal and a differential signal, there is a problem in that the system becomes large. Furthermore, according to the technology described in Non-Patent Document 1, the signal obtained by the photodiode is logarithmically compressed in order to fit it within the input range of the difference detection circuit, and the information is compressed and linearity is lost. There was a problem with the problem.

As an example of a device for acquiring both a difference signal and a video signal, the technique described in Non-Patent Document 2 can be exemplified. According to the technology described in Non-Patent Document 2, in addition to the event trigger generation function using the difference detection circuit, each pixel also has a readout function using the normal APS (Active Pixel Sensor) method, and can detect difference signals and It can output both video signals.

T. Finateu et al., “A 1280×720 Back-Illuminated Stacked Temporal Contrast Event-Based Vision Sensor with 4.86μm Pixels, 1.066GEPS Readout, Programmable Event-Rate Controller and Compressive Data-Formatting Pipeline”ISSCC, 5.10, pp. 112-113 (2020) G. Taverni et al., “Front and Back Illuminated Dynamic and ActivePixel Vision Sensors Comparison”IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 65, No. 5 pages 677-681, (2018)

Here, the difference signal output by the technique described in Non-Patent Document 2 is a digital signal, whereas the video signal is output as an analog value. In order to extract the video signal as a digital signal, A/D conversion may be performed outside the pixel area (for example, in the periphery of the same layer or in a different layer) or outside the sensor chip (for example, in a different chip). Regardless of which configuration is adopted, the system becomes larger and must be synchronized with the differential signal. That is, when using the technology described in Non-Patent Document 2 to use both the difference signal and the video signal as digital values, there were problems such as the system becoming larger and the control for synchronizing with the difference signal becoming complicated. . Furthermore, the technique described in Non-Patent Document 2, similar to the technique described in Non-Patent Document 1, logarithmically compresses the signal obtained by the photodiode in order to fit it within the input range of the difference detection circuit. , there was a problem that the information was compressed and linearity was lost.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a signal processing device and a signal processing method that can easily obtain a video signal and a difference signal indicating that a predetermined change has occurred in the video signal as digital values.

[1] In order to solve the above problem, a signal processing device according to one aspect of the present invention includes an acquisition unit that acquires a value that changes over time, and a signal processing device that acquires a value that changes over time, and a counter section that counts up or down depending on whether it is the first period or the second period; a first signal corresponding to the value counted up by the counter section; and a value counted up by the counter section. and an output section that outputs a second signal corresponding to the difference from the down-counted value.

[2] Further, one aspect of the present invention is that in the signal processing device according to [1] above, the counter section includes a first counter section that counts up in the first period and counts down in the second period. and a second counter section that counts down in the first period and counts up in the second period, and the output section is configured to count up according to the value counted up by the first counter section in the first period. or a value corresponding to the value up-counted by the second counter unit in the second period, as the first signal, and the value up-counted by the first counter unit in the first period. A value corresponding to a difference between the value counted down by the first counter unit in the second period, or a value corresponding to the difference between the value counted up by the second counter unit in the second period and the value counted up by the second counter unit in the first period. At least one of the values corresponding to the difference from the down-counted value is outputted as the second signal.

[3] Further, one aspect of the present invention is the signal processing device according to [1] or [2] above, wherein the counter section includes a multi-bit counter element, and the second signal includes a trigger signal that is output depending on whether the output value of any of the counter elements included in the counter element is 0 or 1.

[4] Moreover, one aspect of the present invention is that in the signal processing device according to [3] above, the second signal is a signal of the most significant bit of the counter element among the counter elements included in the counter section. It includes a code signal which is an output value.

[5] Moreover, one aspect of the present invention is that in the signal processing device according to [3] or [4] above, among the counter elements included in the counter section, the least significant bit of the counter element is It has an enable terminal that determines whether the signal is valid or not.

[6] Further, one aspect of the present invention is the signal processing device according to any one of [1] to [5] above, in which the acquisition unit generates a pulse signal whose value changes over time to a digital value of 1 or 0. It is something to be acquired.

[7] Further, one aspect of the present invention is the signal processing device according to any one of [1] to [5] above, in which the acquisition unit acquires an analog value whose value changes continuously, and The device further includes an A/D converter that converts into a digital value according to a comparison result with a predetermined threshold value.

[8] Moreover, one aspect of the present invention is the signal processing device according to the above [7], in which the acquisition unit acquires a voltage value according to a result of light incident on the photodiode.

[9] Furthermore, in the signal processing device according to [8] above, one aspect of the present invention is to apply a reset voltage to the photodiode depending on the digital value output by the A/D converter. The present invention further includes a reset transistor that determines whether or not the current state has occurred.

[10] Further, in the signal processing method according to one aspect of the present invention, in a period including an acquisition step of acquiring a value that changes over time, and a first period and a second period, the first period or the second period is provided. a counter process that counts up or counts down depending on which period it is in; a first signal that corresponds to the value counted up by the counter process; and a value that counts up and counts down by the counter process. and an output step of outputting a second signal according to the difference.

According to the present invention, it is possible to easily obtain a video signal and a difference signal indicating that a predetermined change has occurred in the video signal as digital values.

FIG. 2 is a schematic diagram showing an example of a three-dimensional structure of the solid-state image sensor according to the first embodiment. FIG. 2 is a circuit diagram showing an example of a circuit configuration of a pixel circuit according to the first embodiment. 2 is a timing chart illustrating pulse generation timing when light is incident on a photodiode according to the first embodiment. 2 is a timing chart illustrating the output timing of a first signal and a second signal outputted by the signal processing device according to the first embodiment, and changes in a counter value. FIG. 3 is a circuit diagram showing an example of a circuit configuration of a pixel circuit according to a second embodiment. 12 is a timing chart illustrating output timings of a first signal and a second signal output by a signal processing device according to a second embodiment, and changes in a counter value.

[Embodiment]
First, the premises of the embodiment will be explained. The signal processing device and signal processing method according to this embodiment perform processing on signals whose values change over time. Signals whose values change over time include both analog values whose values change continuously and digital values whose values change discretely. Digital values whose values change discretely include digital values whose values are expressed as multiple discrete values (for example, 8 bits = 256), as well as pulse signals whose values are expressed as binary values of 0 or 1. .

In the following description, the signal processing device and signal processing method according to the present embodiment will be described, as an example, in a case where signals output from a sensor are targeted. The sensor may be, for example, an image sensor used in an imaging device, a tactile sensor used in robot control, or the like. Other examples include pressure sensors, acceleration sensors, optical sensors, humidity sensors, temperature sensors, and Hall sensors. Furthermore, the signal processing device and signal processing method according to this embodiment can be applied to sensors and measurement devices that capture temporal fluctuations, and can be widely applied to logic circuits, drive circuits, communication circuits, recording elements, displays, actuators, etc. can do.
In the following example, an example in which the signal processing device and signal processing method according to the present embodiment are applied to a solid-state image sensor that processes signals output using the photoelectric effect of a photodiode will be described. The solid-state imaging device is used in an imaging device or the like.

[First embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram showing an example of a three-dimensional structure of the solid-state image sensor according to the first embodiment. The solid-state image sensor 5 has a plurality of hierarchical structures. In the example shown in the figure, an example is illustrated in which the device has a three-layer structure of a first layer L1, a second layer L2, and a third layer L3. At each level, circuit elements are formed using semiconductor structures. Each layer is insulated by an interlayer insulating film. By forming via holes (contact holes) in the interlayer insulating film, circuit elements formed in each layer are connected.

A plurality of photodiodes (pixels) are formed in the first layer L1. A photodiode converts incident light into an electrical signal. Specifically, the photodiode outputs an electrical signal according to the intensity of incident light due to the photoelectric effect. Here, in order to extract the electrical signal output by the photodiode, a predetermined electrical circuit such as an A/D conversion circuit is required. If a single layer structure is used instead of a hierarchical structure as shown in Figure 1, the predetermined electric circuit will be formed on the same surface as the photodiode, so the spacing between the multiple photodiodes will be large. turn into. However, by adopting a hierarchical structure as shown in FIG. 1, it is not necessary to provide a predetermined electric circuit between the plurality of photodiodes, and the arrangement interval between the plurality of photodiodes can be reduced. Therefore, by employing a hierarchical structure, photodiodes can be arranged with higher density. In other words, a high-resolution solid-state image sensor 5 can be provided.

A circuit for converting the electrical signal output by the photodiode into a pulse signal is formed in the second level L2. Therefore, the circuit formed in the second layer L2 can also be described as an A/D conversion circuit. The circuit formed in the second level L2 may be, for example, an inverter chain circuit in which a plurality of inverters are connected in series. The inverter chain circuit outputs an H level or L level voltage depending on the input threshold voltage of the inverter element connected to the photodiode.
Note that a comparator circuit may be formed in the second layer L2 instead of the example in which an inverter chain circuit is formed. The comparator circuit compares the electrical signal output by the photodiode with a predetermined reference voltage, and outputs an H level or L level voltage depending on the comparison result.
Note that the second layer L2 may include a predetermined delay circuit.

A counter circuit is formed in the third layer L3. The counter circuit counts the number of pulse signals output by the circuit formed in the second layer L2. The counter circuit has, for example, an 8-bit counter element and counts values from 0 to 255. When the solid-state image sensor 5 outputs a video signal, the counter circuit counts the number of pulses input within a predetermined period and outputs the counted value to a control circuit (not shown). When the solid-state image sensor 5 outputs an activation signal, the counter circuit detects whether the number of input pulse signals exceeds a predetermined threshold, and disables the trigger signal when it is detected that the number exceeds the threshold. Output to the illustrated control circuit.

Note that when the solid-state image sensor 5 has a plurality of counter circuits, there may be a plurality of layers in which the counter circuits are formed. For example, when one pixel has two counters, a counter circuit may be formed in the fourth layer L4 in addition to the third layer L3. That is, the solid-state image sensor 5 is not limited to the example of having the three-layer structure shown in the figure, but may have a hierarchical structure of four or more layers, or may have no hierarchical structure. (that is, each element may be formed on a single-phase substrate).

In the following description, a configuration including one pixel and a peripheral circuit (for example, an A/D conversion circuit or a counter circuit) corresponding to the pixel will be referred to as a pixel circuit 1. In the example shown in FIG. 1, the pixel circuit 1 has a three-layer structure including parts of the first layer L1 to the third layer L3. The pixel circuit 1 may have a plurality of hierarchical structures as shown in the figure, or may be formed on a single layer substrate.

FIG. 2 is a circuit diagram showing an example of the circuit configuration of the pixel circuit according to the first embodiment. An example of the circuit configuration of the pixel circuit 1 will be described with reference to the same figure. The pixel circuit 1 includes a signal processing device 10 and a light amount detection device 20. The signal processing device 10 may be formed on the third level L3, and the light amount detection device 20 may be formed on the first level L1 and the second level L2.
Note that in the following description, for convenience, the functions of the pixel circuit 1 will be explained separately as the signal processing device 10 and the light amount detection device 20; however, some or all of the configuration of the light amount detection device 20 May be included.

First, the configuration of the light amount detection device 20 will be explained. The light amount detection device 20 includes a photodiode 21, an inverter chain 22, and a reset transistor 23. The photodiode 21 may be formed on the first level L1, and the inverter chain 22 and the reset transistor 23 may be formed on the second level L2. The light amount detection device 20 outputs a pulse signal according to the amount of light incident on the photodiode 21. Therefore, by counting the number of pulse signals output within a predetermined period of time, the amount of light incident on the light amount detection device 20 can be detected.

Photodiode 21 has an anode terminal and a cathode terminal. The anode terminal is grounded and the cathode terminal is connected to the input terminal of the inverter chain 22. A photodiode generates a charge depending on the amount of light that enters it. The charges generated by the photodiodes are input to the inverter chain 22 as a voltage value depending on the amount of generated charges. Specifically, the charge generated by the photodiode is accumulated in a capacitance component (not shown) that exists between the cathode terminal of the photodiode 21 and the input terminal of the inverter chain 22. The accumulated charge appears as a voltage depending on the magnitude of the capacitance component, and is input to the input terminal of the inverter chain 22. The capacitive component is also referred to as a floating diffusion. Further, the voltage at the cathode terminal of the photodiode 21 is also referred to as a voltage _VPD .

The inverter chain 22 includes a plurality of inverter elements connected in series. Specifically, the inverter element may be a complementary metal-oxide-semiconductor (CMOS) inverter. In the example shown in FIG. 2, the inverter chain 22 includes an inverter 221, an inverter 222, . . . , an inverter 22n (n is a natural number of 1 or more). Each inverter element has an input terminal and an output terminal, and a voltage level opposite to the voltage level of the input terminal is outputted to the output terminal. For example, when 1 (high level) is input to the input terminal of each inverter element, 0 (low level) is output to the output terminal of the inverter element. Furthermore, when 0 is input to the input terminal of an inverter element, 1 is output to the output terminal of the inverter element. Each inverter element has an input threshold voltage and outputs a value according to the voltage value input to the input terminal and the threshold value.

Here, the number of inverter elements provided in the inverter chain 22 is an odd number. That is, the inverter chain 22 as a whole inverts the voltage level input to the input terminal of the inverter chain 22 and outputs it to the output terminal. The voltage output by the inverter chain 22 is also referred to as an output voltage V _OUT .

Furthermore, the number of inverter elements included in the inverter chain 22 may be set depending on the pulse width of the pulse signal that the light amount detection device 20 wants to output. For example, by increasing the number of inverter elements included in the inverter chain 22, the pulse width can be increased. Further, by reducing the number of inverter elements included in the inverter chain 22, the pulse width can be shortened.

Further, by adjusting the input threshold voltage of the inverter element (particularly the inverter 221), the amount of light corresponding to one pulse output by the light amount detection device 20 can be adjusted. For example, by reducing the input threshold voltage, more light enters the photodiode 21 before a pulse is output. Further, by increasing the input threshold voltage, a pulse is outputted after less light is incident on the photodiode 21.

Note that a comparator circuit (not shown) may be used instead of the first-stage inverter element (the inverter near the photodiode 21, that is, the inverter 221) connected to the inverter chain 22. A cathode terminal of the photodiode 21 is connected to one end of the input terminal of the comparator circuit. Further, a predetermined reference voltage is input to the other end of the input terminal of the comparator circuit. The comparator circuit outputs a voltage corresponding to the voltage at the input terminal connected to the cathode terminal of the photodiode 21 and the reference voltage to the output terminal. A predetermined delay circuit may be provided after the comparator circuit.

The reset transistor 23 resets the photodiode 21 by supplying a reset voltage V _RST to the photodiode 21 according to the output voltage of the inverter chain 22 . In other words, the reset transistor 23 determines whether or not to apply the reset voltage to the photodiode 21 according to the digital value output by the inverter chain 22 . The reset transistor 23 may be, for example, an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor). If the reset transistor 23 is an N-channel MOSFET, its gate terminal is connected to the output terminal of the inverter chain 22 . The source terminal is connected to a power supply that provides a reset voltage V _RST . The drain terminal is connected to the cathode terminal of the photodiode 21.
Here, when the reset transistor 23 is an enhancement type N-channel MOSFET, the reset voltage V _RST is reduced by the threshold value of the reset transistor 23 and transmitted to the photodiode 21 . Therefore, the reset transistor 23 may be a depletion type N-channel MOSFET.
Note that it is also possible to use a P-channel MOSFET as the reset transistor 23. In this case, an inverter circuit is inserted into the gate terminal of the reset transistor 23. By using a P-channel MOSFET, it is possible to prevent the reset voltage V _RST from decreasing by the threshold value of the reset transistor 23 and being transmitted to the photodiode 21.

In normal times, that is, when no light is incident on the photodiode 21, the voltage _VPD of the photodiode 21 is at a high level. When the voltage V _PD of the photodiode 21 decreases due to light incidence and reaches the input threshold voltage of the inverter 221, the output voltage V _OUT of the inverter chain 22 is inverted and goes from a low level to a high level. When the inverter chain 22 outputs a high level, the source-drain of the reset transistor 23 is turned on, the reset voltage V _RST is supplied to the photodiode 21, and the voltage V _PD of the photo diode 21 is equal to the reset voltage V _RST . Become. When the inverter chain is inverted again and the output voltage V _OUT of the inverter chain 22 becomes low level, the source-drain of the reset transistor 23 is turned off. By repeating this operation, a pulse signal appears at the output terminal of the inverter chain 22.

Note that the photodiode 21 may be a buried photodiode. When the photodiode 21 is a buried photodiode, a transfer transistor (not shown) may be provided between the photodiode 21 and the inverter chain 22. The transfer transistor is controlled by a control unit (not shown) and transfers the charge generated by the photodiode 21 to the inverter chain 22 (specifically, a floating diffusion provided between the transfer transistor and the inverter chain 22). .

Next, the configuration of the signal processing device 10 will be explained. A signal whose value changes over time is input to the signal processing device 10 . Regarding the input signal, the signal processing device 10 generates a counter value corresponding to the input signal (for example, an output value of a sensor) and a difference signal that is output when the counted counter value exceeds a predetermined threshold value. Output. In the example shown in FIG. 2, an example in which the signal processing device 10 counts pulse signals output by the light amount detection device 20 will be described.
The signal processing device 10 includes a pulse signal acquisition section 11, a counter section 12, and a trigger signal generation circuit 13.

The pulse signal acquisition unit 11 acquires values that change over time. In the example shown in FIG. 2, the pulse signal acquisition unit 11 receives a pulse signal (output voltage V OUT ) which is a signal _output from the light amount detection device 20 and whose value changes over time to a digital value of 1 or 0. is input. In the following description, the pulse signal acquisition section 11 may be simply referred to as an acquisition section.

Note that when the signal processing device 10 includes part or all of the configuration of the light amount detection device 20, the connection portion between the photodiode 21 and the inverter chain 22 may be used as the acquisition portion. In this case, the acquisition unit acquires analog values whose values change continuously. Furthermore, in this case, the signal processing device 10 also includes an inverter chain 22. The inverter chain 22 has a role as an A/D converter that converts analog values into digital values. The inverter chain 22 as an A/D converter converts the analog value into a digital value according to the comparison result between the analog value corresponding to the output of the photodiode 21 and a predetermined threshold value (for example, the input threshold voltage of an inverter element). Convert.

Further, in this embodiment, the acquisition unit is capable of acquiring various values that change over time, but since the example shown below is an example of the pixel circuit 1 used in the solid-state image sensor 5, the acquisition unit is capable of acquiring various values that change over time. , a voltage value corresponding to the result of light incident on the photodiode 21 is acquired.

The counter section 12 includes an asynchronous counter circuit that counts the number of pulse signals input during a predetermined period. The counter circuit includes a multi-bit counter element. With reference to FIG. 2, an example in which 9-bit counter elements 121 to 129 are included as an example of a multi-bit counter element will be described. The number of bits of the counter element provided in the counter section 12 may be the maximum value that can be counted plus one bit. That is, when a 9-bit counter element is provided, it is possible to count from 0 to 255 using an 8-bit counter element obtained by subtracting 1 bit from 9 bits.

A configuration common to multiple-bit counter elements will be described using the counter element 121 as an example. The counter section 12 can be arbitrarily designed using existing technology, but in the following description, an example will be described in which a T flip-flop (T-FF) is used as the counter element. Note that a T flip-flop configuration may be realized using a D flip-flop or the like.

Counter element 121 includes an input terminal 1211, a first output terminal 1212, and a second output terminal 1213. A pulse signal is input to the input terminal 1211. The output signal of the light amount detection device 20 is input to the counter element 121 which is the least significant bit. The output signals of the preceding counter elements are input to the input terminals of the counter elements 122 to 129, respectively. The first output terminal 1212 and the second output terminal 1213 output signals from either the non-inverting output terminal or the inverting output terminal of the T flip-flop. The first output terminal 1212 is a terminal for outputting to the next stage counter element, and the second output terminal 1213 is a terminal for outputting the counter value. The first output terminal 1212 and the second output terminal 1213 may be a common terminal.

A U/D signal is input to each counter element. The U/D signal is a signal for controlling whether to perform up-counting or down-counting. Each counter element counts up or down depending on whether the U/D signal is 1 or 0. The U/D signal is a signal commonly input to multiple bit counter elements. Each counter element switches whether to output the output signal from the non-inverting output terminal or the inverting output terminal to the next stage counter element depending on whether the U/D signal is 1 or 0. Good too.

Among the 9-bit counter elements 121 to 129, the least significant bit, the counter element 121, is provided with an enable terminal 1214. Enable terminal 1214 determines whether the input signal is valid. Specifically, the enable terminal 1214 can control the input of the input terminal 1211 to be enabled or disabled depending on the input voltage level. By invalidating only the least significant bit, the least significant bit no longer performs counting, so that the counting of other counter elements included in the counter section 12 can also be invalidated.

Further, a counter reset signal CRST (not shown) may be input to each counter element. When the counter reset signal CRST is at a high level, the counter value of each counter element is set to an initial value, and when it is at a low level, each counter element performs a normal counter operation.

The trigger signal generation circuit 13 generates a trigger signal T and a code signal S based on the up-counted value and the down-counted value by the counter section 12.
The trigger signal T is a signal indicating whether the number of pulse signals input to the counter section 12 during a predetermined period is equal to or greater than a predetermined threshold. That is, the trigger signal T is a differential signal. Here, the threshold value for detecting the difference as the trigger signal T may be set as the number of bits. For example, if 4 bits is used as the threshold, look at the absolute value of the difference between the up-counted value and the down-counted value by the counter unit 12 during a predetermined period, starting from the most significant bit, and determine at which bit 1 appears for the first time. is detected, and if it is the fourth bit or higher, the trigger signal T is set to 1. Specifically, if any of the bits higher than the fourth bit, which is the threshold value, is 1, the trigger signal T is set to 1. In other words, the trigger signal T is output depending on whether the output value of one of the counter elements of a bit higher than the threshold bit among the plurality of counter elements included in the counter section 12 is 0 or 1. may be done.

The threshold value for determining whether or not to output the trigger signal T can be set based on the requirement of how much difference in light amount should be used to generate a trigger. For example, by bringing the threshold value closer to the least significant bit, the trigger signal T is output with less light intensity (in other words, more sensitively). Furthermore, by bringing the bit used as the threshold closer to the most significant bit, the trigger signal T is output with a larger amount of light (in other words, with less sensitivity).

Here, since the counter section 12 includes a 9-bit counter element, it is possible to count from 0 to 512. However, since the counter section 12 performs up-counting and down-counting, it will be described as performing up-counting and down-counting in the range of -255 to 255 with 0 as the initial value. That is, the 1st to 8th bits (counter element 121 to counter element 128) determine the absolute value of the value counted by the counter section 12 (hereinafter referred to as counter value), and the 9th bit (counter element 128) Element 129) determines the sign. The code signal S is a signal indicating the sign of the counter value. Specifically, as for the code signal S, the output of the 9th bit is output as is. That is, the code signal S is the output value of the most significant bit counter element among the plurality of counter elements included in the counter section 12. When the code signal S is 1, the counter value is positive, and when the code signal S is 0, the counter value is negative. If the counter value is positive, it indicates that the up-counted value is greater than the down-counted value. If the counter value is negative, it indicates that the up-counted value is smaller than the down-counted value.

Note that the signal output according to the value up-counted by the counter section 12 may be referred to as a first signal S1. Specifically, the first signal S1 may be a 9-bit signal output from the second output terminal 1213 of the counter element 121 to the second output terminal 1293 of the counter element 129.
Furthermore, the output signal output by the trigger signal generation circuit 13 may be referred to as a second signal S2. The second signal S2 includes a trigger signal T and a code signal S.
The configuration that outputs the first signal S1 and the second signal S2 may be referred to as an output section. That is, the output section outputs a first signal S1 corresponding to the value counted up by the counter section 12 and a second signal S2 corresponding to the difference between the value counted up and the value counted down by the counter section 12.

FIG. 3 is a timing chart illustrating pulse generation timing when light is incident on the photodiode according to the first embodiment. Referring to the figure, the pulse generation timing of the output voltage V _OUT output by the inverter chain 22 when light is incident on the photodiode 21 will be described. In the figure, the horizontal axis represents time, and the change in the voltage _VPD of the photodiode 21 is shown as a waveform W11. Further, the output voltage V _OUT of the inverter chain 22 is shown as a waveform W12. In the figure, an example in which a constant amount of light continues to enter the photodiode 21 will be described.
Note that the voltage supplied by the reset transistor 23 will be referred to as a reset voltage _VRST , and the input threshold voltage of the inverter chain 22 will be referred to as a threshold voltage _VTH . Further, the output voltage V _OUT outputted by the inverter chain 22 is expressed as a binary value of L or H.

Since no light is incident on the photodiode 21 before time t0, the voltage V _PD of the photodiode 21 is the reset voltage V _RST . Furthermore, in this state, since H is input to the inverter chain 22, the output voltage V _OUT is L.
Light enters the photodiode 21 from time t0 to time t11. In the example shown in FIG. 3, a constant amount of light continues to enter the photodiode 21, so the voltage _VPD of the photodiode 21 decreases linearly.
When the voltage V _PD of the photodiode 21 drops to the threshold voltage V _TH at time t11, the output voltage V _OUT of the inverter chain 22 is inverted and outputs H. When the output voltage V _OUT of the inverter chain 22 becomes H, the reset transistor 23 is turned on, and the voltage V _PD of the photodiode 21 becomes the reset voltage V _RST . When the voltage V _PD becomes the reset voltage V _RST , H is input to the inverter chain 22, and the output voltage V _OUT is inverted again and becomes L.

This operation is repeated from time t11 to time 14, and as a result, the output voltage V _OUT of the inverter chain 22 outputs a pulse signal.
The pulse width of the output voltage V _OUT of the inverter chain 22 is determined by the response time (delay time) from when the inverter chain starts inverting until the voltage V _PD becomes the reset voltage V _RST . Therefore, the sum of the delay times of the respective inverter elements included in the inverter chain 22 becomes the pulse width.

FIG. 4 is a timing chart illustrating the output timing of the first signal and the second signal output by the signal processing device according to the first embodiment and changes in the counter value. With reference to the figure, the output timing of the first signal S1 and second signal S2 output by the signal processing device 10 and changes in the counter value output by the counter section 12 will be explained.

Here, the period during which the counter section 12 performs up-counting may be referred to as a first period T1, and the period during which the counter section 12 performs down-counting may be referred to as a second period T2. The first period T1 and the second period T2 may have the same length. The first period T1 and the second period T2 are repeated and alternated. For example, the first period T1 may be an odd frame, and the second period T2 may be an even frame.
Note that since this embodiment describes an example in which the signal processing device 10 is applied to the solid-state image sensor 5, each period may be referred to as a frame. Specifically, the first period T1 may be referred to as a first frame, and the second period T2 may be referred to as a second frame.

FIG. 4 shows changes in the counter value output by the counter section 12, with the horizontal axis representing time. In the example shown in the figure, of the 9-bit counter element included in the counter section 12, the 1st to 8th bits are treated as the absolute value of the counter, and the 9th bit of the counter value is treated as a sign. In the figure, the counter values counted by the counter section 12 are shown as 0 to 512.

Further, in the figure, the values of the U/D signal, counter reset signal CRST, and enable signal EN input to the counter section 12 are shown as two values, L or H. The counter section 12 counts up when the U/D signal is L, and counts down when the U/D signal is H. The level of the U/D signal is switched in conjunction with switching to the first period T1 or the second period T2. That is, the counter unit 12 counts up or down depending on whether the period is the first period T1 or the second period T2 in a period including the first period T1 and the second period T2.
While the counter reset signal CRST is at H, the output value of each bit is fixed to 0, and during the period when the counter reset signal CRST is at L, the counter section 12 performs a counting operation. During the period when the enable signal EN is L, the counter section 12 does not perform a counting operation even if a pulse signal is input, and during the period when the enable signal EN is H, the counter section 12 performs a counting operation according to the pulse signal.

Further, in the figure, the reading timing of the first signal S1 is described as the video signal reading timing V_READ, and the reading timing of the second signal is described as the differential signal reading timing T_READ. The video signal read timing V_READ and the differential signal read timing T_READ are both indicated by two values, L or H, with H as the read timing.

At time t21, the enable signal EN is turned off, the counter value is reset (that is, one pulse is input as the counter reset signal CRST), and then the enable signal EN is turned on (that is, switched from L to H). Thereafter, the counter value performs an up-count operation according to the amount of light incident on the photodiode 21.
The period from time t21 to time t22 is a first period T1 in which the counter section 12 performs up-counting. That is, from time t21 to time t22, the U/D signal is fixed at L indicating up-counting.

From time t21 to time t22, the counter section 12 sequentially counts up from 256. At time t22, the first signal S1 is read out. That is, the video signal read timing V_READ becomes H, and the counter value at time t22 is read. In the example shown in FIG. 4, the counter value at time t22 is approximately 500. Here, the counter unit 12 holds a value obtained by adding 256 to the value counted in the first period T1. In order to output a value obtained by subtracting 256 from the counter value, it is sufficient to output the counter value from the 1st bit to the 8th bit (that is, the value excluding the 9th bit, which is the sign bit).
In order to prevent malfunction during the reading period of the counter value, the counting operation may be set to be disabled. That is, the enable signal EN may be set to L.

Here, when the pixel circuit 1 is included in the solid-state image sensor 5, it is necessary to read the counter values from the plurality of pixel circuits 1 included in the solid-state image sensor 5. For example, the output from the counter section 12 provided in each pixel circuit 1 may use an XY address method or the like. When using an XY addressing method, pixels are sequentially selected and read out. Further, instead of reading the counter values (that is, video signals) for all pixels, only the counter values (that is, video signals) for pixels that have a difference may be read using a trigger signal, which will be described later.

The period from time t22 to time t23 is a second cycle T2 in which the counter section 12 counts down. That is, from time t22 to time t23, the U/D signal is fixed at H, indicating a down count. The counter unit 12 counts down starting from the counter value read out at time t22. Since the length of the first period T1 and the length of the second period T2 are the same, if the amount of light incident on the photodiode 21 is the same, the counter value at time t23 is theoretically 0 (expressed in 9 bits). If so, it becomes 256). If the amount of light incident on the photodiode 21 during the first period T1 is greater than that during the second period T2, the counter value at time t23 will be positive (that is, greater than 256 when expressed in 9 bits). If the amount of light incident on the photodiode 21 during the first period T1 is smaller than that during the second period T2, the counter value at time t23 becomes negative (ie, smaller than 256 when expressed in 9 bits).

At time t23, the second signal S2 is read out. That is, the differential signal reading timing T_READ becomes H, and the trigger signal T, which is the output signal of the counter element of the bit set as the threshold value, and the code signal S, which is the output signal of the 9th bit, are read out. During the reading period of the second signal S2, the counting operation may be set to be disabled in order to prevent malfunction. That is, the enable signal EN may be set to L. Since the output from the counter section 12 requires a certain amount of time, if that time is longer than the period of pulse output, the counter value may change. Therefore, by setting the enable signal EN to L, it is possible to prevent the counter value from changing. In the example shown in FIG. 4, the counter value at time t23 is approximately 350, which is greater than 256 when expressed in 9 bits.

Note that when the pixel circuit 1 is used in the solid-state image sensor 5, the trigger signal T may be sent to an address generation circuit provided around the pixel array or within the pixel. The address generation circuit may output the address information (XY coordinates) of the pixel for which the trigger signal T is 1, together with the code S.
Further, the code signal S is not necessarily essential, and only the trigger signal T may be generated and output.

When the cycle including the first cycle T1 and the second cycle T2 ends, the counter value is reset to 0 (ie, 256) (ie, the counter reset signal CRST becomes H).

The first cycle T1 starts again from time t23 to time t24. The U/D signal is fixed at L again. At time t23, enable signal EN is turned off and the counter value is reset. After that, the enable signal EN is turned on, and the counter value performs an up-count operation according to the amount of light incident on the photodiode 21. At time t24, the first signal S1 is read out. In the example shown in FIG. 4, the counter value at time t24 is about 400.

The second period T2 starts again from time t24 to time t25. The U/D signal is fixed at H again. The counter unit 12 performs a down-count operation starting from the counter value read at time t24. At time t25, the second signal S2 is read out. In the example shown in FIG. 4, the counter value at time t23 is about 200, which is smaller than 256 when expressed in 9 bits.

Note that the image information may be read out in the first period T1 using the address information of the pixel for which the trigger signal T was 1 in the second period T2 immediately before the first period T1. With this configuration, only the video information that has changed can be read out, and data can be reduced without reducing effective information.

[Summary of the first embodiment]
According to the embodiment described above, the signal processing device 10 includes the pulse signal acquisition unit 11 to acquire a value that changes over time, and includes the counter unit 12 to enable the first period T1 and the second period T2. In a period including , the first signal is counted up or down depending on whether it is the first period T1 or the second period T2, and is provided with an output section to generate a first signal according to the value counted up by the counter section 12. S1 and a second signal S2 corresponding to the difference between the up-counted value and the down-counted value by the counter section 12. The first period T1 and the second period T2 are repeated and alternated. In the first period T1 (i.e., an odd frame), a video signal is output by up-counting the pulses, and in the second period T2 (i.e., an even-numbered frame), a difference signal is output using the results of up-counting and down-counting the pulses. . Therefore, according to this embodiment, the video signal and the difference signal can be easily obtained as digital values.

Further, according to the embodiment described above, the counter section 12 includes a multi-bit counter element, and the trigger signal T included in the second signal S2 is determined by the output value of one of the counter elements included in the counter section 12. It is output depending on whether it is 0 or 1. Specifically, the counter unit 12 outputs the trigger signal T depending on whether the output value of any counter element of the bit higher than the bit set as the threshold value is 0 or 1. That is, according to the present embodiment, it is possible to determine which bit of the counter is to be used as the threshold, and to change the threshold of the difference signal depending on whether or not there is a change in the higher-order bits. Therefore, according to this embodiment, the threshold value of the difference signal can be easily set.

Further, according to the embodiment described above, the code signal S included in the second signal S2 includes a plurality of bits of counter elements, and the code signal S included in the counter element included in the counter section 12 is the most significant bit counter element (FIG. In the example shown in , it is the output value of the counter element 129). That is, according to the present embodiment, it is possible to detect which of the value counted in the first period T1 and the value counted in the second period T2 is larger based on the output value of the counter element of the most significant bit. Can be done. Further, according to the present embodiment, the first to eighth bits are treated as absolute values, and the ninth bit is treated as a sign. In the case of down counting, it is possible to count from 512 to 0 with 256 as the center. Therefore, according to this embodiment, even if the incident amount in the second period T2 is larger than the incident amount in the first period T1, it is possible to count without overflowing.

Further, according to the embodiment described above, among the plurality of counter elements included in the counter section 12, the least significant bit counter element (in the example shown in FIG. 2, the counter element 121) receives a valid input signal. It has an enable terminal 1214 for determining whether or not. Counter element 121 determines whether the input pulse signal is valid or not depending on the voltage level input to enable terminal 1214. Unless the input signal of the counter element of the least significant bit is enabled, no signal is input to the counter element of the subsequent stage, so that the counter section 12 as a whole cannot perform a counting operation. Therefore, according to the present embodiment, by disabling only the least significant bit, it is possible to disable the counting operation of the other counter elements (counter element 122 to counter element 129) included in the counter section 12. .

Further, according to the embodiment described above, the pulse signal acquisition unit 11 acquires a pulse signal whose value changes over time to a digital value of 1 or 0. Therefore, according to the present embodiment, the signal processing device 10 can output a value obtained by counting the number of pulses for the output value of the sensor which is output in binary form, and a difference signal.

Further, according to the embodiment described above, when the signal processing device 10 includes the light amount detection device 20, the acquisition unit acquires an analog value whose value changes continuously. Further, the inverter chain 22 functions as an A/D converter that converts the analog value into a digital value according to the comparison result between the analog value and a predetermined threshold value. Therefore, according to the present embodiment, by providing the inverter chain 22, even a sensor that outputs an analog value can be converted into a pulse signal, and a value obtained by counting the number of pulses and a difference signal can be output.

Further, according to the embodiment described above, the acquisition unit acquires the voltage value according to the result of light incident on the photodiode 21. Therefore, according to this embodiment, it is possible to provide the solid-state image sensor 5 that can output a video signal and a difference signal.

Further, according to the embodiment described above, when the signal processing device 10 includes the light amount detection device 20, the signal processing device 10 includes the reset transistor 23, so that the output from the inverter chain 22 as an A/D conversion section is It is possible to control whether or not to apply the reset voltage V _RST to the photodiode 21 according to the digital value. Therefore, even if the photodiode 21 is saturated, the photodiode 21 can be reset.

Further, according to the embodiment described above, the signal processing device 10 employs a simple circuit configuration consisting of a relatively small number of transistors, including the inverter chain 22 and the counter section 12 (1-bit counter connected in series). . According to this embodiment, two types of digital signals can be output despite such a simple circuit configuration. Further, since the signal processing device 10 has a simple circuit configuration, it is possible to suppress an increase in pixel size, and it is possible to provide a solid-state image sensor 5 that outputs a high-resolution video signal and difference information.

Furthermore, by applying the solid-state image sensor 5 equipped with the signal processing device 10 according to the present embodiment to an imaging device, depending on the application, a mode in which only difference information is output at all times, and a mode in which video signals of all pixels are output in addition to difference information can be created. It is possible to provide an imaging device that can switch between an output mode and a mode that outputs only the video signal that has changed from the difference information. Since the imaging device can output difference information compared to a normal imaging device, it becomes possible to detect motion information. Furthermore, in modes other than the mode in which video signals of all pixels are output, the amount of data can be reduced without reducing effective information.

Furthermore, according to the present embodiment, the signal obtained by the photodiode 21 is not subjected to logarithmic compression or the like, so the relationship between the amount of light and the number of pulses is linear. Therefore, according to this embodiment, it is possible to obtain accurate video information and difference information that reflect the subject to be photographed.

[Second embodiment]
Next, a second embodiment will be described. First, an overview of the problem that the second embodiment attempts to solve will be explained. According to the pixel circuit 1 according to the first embodiment, the video signal and the difference signal can be output as digital values. However, according to the pixel circuit 1 according to the first embodiment, the video signal is output in the first period T1 (even frame) and the difference signal is output in the second period T2 (odd frame). There was a problem that the video signal was lost (that is, the amount of information was halved). Therefore, the second embodiment aims to obtain a video signal also in the second period T2.

FIG. 5 is a circuit diagram showing an example of a circuit configuration of a pixel circuit according to the second embodiment. An example of the circuit configuration of a pixel circuit 1A according to the second embodiment will be described with reference to the same figure. In the description of the pixel circuit 1A, the same components as the pixel circuit 1 may be given the same reference numerals and the description thereof may be omitted. The pixel circuit 1A is similar to the pixel circuit 1 in that it includes a light amount detection device 20. The pixel circuit 1A differs from the pixel circuit 1 in that it includes a signal processing device 10A instead of the signal processing device 10. The signal processing device 10A includes two sets of the same configuration as the signal processing device 10. That is, the signal processing device 10A includes a first signal processing section 110 and a second signal processing section 120. The first signal processing unit 110 and the second signal processing unit 120 may have the same configuration, and each may have the same configuration as the signal processing device 10 described in the first embodiment. .

The first signal processing section 110 includes a first counter section 111. The second signal processing section 120 includes a second counter section 112. In the configuration of the signal processing device 10A, the first counter section 111 and the second counter section 112 are collectively referred to as a counter section 12. That is, in the signal processing device 10A, the counter section 12 includes a first counter section 111 and a second counter section 112. The first counter section 111 counts up in the first period T1 and counts down in the second period T2. The second counter section 112 counts down during the first period T1 and counts up during the second period T2. That is, the configuration may be such that a signal obtained by inverting the signal input to the U/D terminal of the first counter section 111 is input to the U/D terminal of the second counter section 112.

The output section of the signal processing device 10A outputs a value corresponding to the value up-counted by the first counter section 111 in the first period T1, or a value corresponding to the value up-counted by the second counter section 112 in the second period T2. At least one of them is output as the first signal S1.
Further, the output unit of the signal processing device 10A outputs a value corresponding to the difference between the value counted up by the first counter unit 111 in the first period T1 and the value counted down by the first counter unit 111 in the second period T2, Alternatively, at least one of the values corresponding to the difference between the value counted up by the second counter unit 112 in the second period T2 and the value counted down by the second counter unit 112 in the first period T1 is output as the second signal S2. .

That is, the pixel circuit 1A includes the second signal processing section 120 in addition to the first signal processing section 110, so that the operation in the first period T1 and the second period T2 is reversed to that described with reference to FIG. Make it phase. By employing such a configuration, the first signal S1 is obtained from the first signal processing section 110 and the second signal S2 is obtained from the second signal processing section 120 in the first period T1. Further, in the second period T2, the second signal S2 is obtained from the first signal processing section 110, and the first signal S1 is obtained from the second signal processing section 120. That is, in the second embodiment, by providing two systems, the first signal processing section 110 and the second signal processing section 120, the two systems can output a video signal and a difference signal for each frame in total. .

FIG. 6 is a timing chart illustrating the output timing of the first signal and the second signal output by the signal processing device according to the second embodiment, and changes in the counter value. With reference to the figure, the output timing of the first signal S1 and second signal S2 output by the signal processing device 10A and changes in the counter value output by the counter section 12 will be explained.

In the second embodiment, in the first period (first frame) T1, the first counter section 111 performs up-counting, and the second counter section 112 performs down-counting. Further, in the second period (second frame) T2, the first counter section 111 performs down counting, and the second counter section 112 performs up counting. The first period T1 and the second period T2 may have the same length. The first period T1 and the second period T2 are repeated and alternated. For example, the first period T1 may be an odd frame, and the second period T2 may be an even frame.

FIG. 6 shows changes in the counter value output by the second counter section 112, with the horizontal axis representing time. Changes in the counter value output by the first counter section 111 are similar to the example described with reference to FIG. 4.
Further, the U/D signal, counter reset signal CRST, and enable signal EN shown in FIG. is the timing at which the second signal processing section 120 outputs the signal. The input/output signals by the first signal processing section 110 are the same as the example described with reference to FIG. 4. Further, the definition of the input/output signal by the second signal processing unit 120 is the definition of the input/output signal by the corresponding first signal processing unit 110, and therefore the description thereof will be omitted.

The period from time t31 to time t32 is a second cycle T2 in which the second counter section 112 performs down-counting. That is, from time t31 to time t32, the U/D signal is fixed at H, indicating a down count. The counter unit 12 counts down starting from the counter value read in the immediately preceding first period T1 (not shown). The counter value in the immediately preceding first period T1 is approximately 400 when expressed in 9 bits.

At time t32, the second signal S2 is read out. That is, the differential signal reading timing T_READ becomes H, and the trigger signal T, which is the output signal of the counter element of the bit set as the threshold value, and the code signal S, which is the output signal of the 9th bit, are read out. During the reading period of the second signal S2, the enable signal EN is set to L and the counting operation is disabled in order to prevent malfunction. In the example shown in FIG. 6, the counter value at time t32 is about 200, which is smaller than 256 when expressed in 9 bits.

At time t32, after the enable signal EN is turned off and the counter value is reset (that is, one pulse is input as the counter reset signal CRST), the enable signal EN is turned on (that is, switched from L to H). Thereafter, the counter value performs an up-count operation according to the amount of light incident on the photodiode 21.
The period from time t32 to time t33 is a first period T1 in which the counter section 12 performs up-counting. That is, from time t32 to time t33, the U/D signal is fixed at L indicating up-counting.

From time t32 to time t33, the second counter section 112 sequentially counts up from 256. At time t33, the first signal S1 is read out. That is, the video signal read timing V_READ becomes H, and the counter value at time t32 is read. In the example shown in FIG. 6, the counter value at time t33 is approximately 500 when expressed in 9 bits. During the reading period of the counter value, in order to prevent malfunction, the count operation is disabled by setting the enable signal EN to L.

The second period T2 starts again from time t33 to time t34. The U/D signal is fixed at H again. The counter unit 12 performs a down-count operation using the counter value read at time t33 as a starting point. At time t34, the second signal S2 is read out. In the example shown in FIG. 6, the counter value at time t34 is approximately 350, which is greater than 256 when expressed in 9 bits.

The first cycle T1 starts again from time t34 to time t35. The U/D signal is fixed at L again. At time t34, enable signal EN is released and the counter value is reset. Thereafter, the counter value performs an up-count operation according to the amount of light incident on the photodiode 21. At time t35, the first signal S1 is read out. In the example shown in FIG. 6, the counter value at time t35 is approximately 400 when expressed in 9 bits.

[Summary of second embodiment]
According to the embodiment described above, the counter unit 12 included in the pixel circuit 1A includes the first counter unit 111 that counts up in the first period T1 and counts down in the second period T2, and the counter unit 111 that counts down in the first period T1. A second counter section 112 that counts up during the second period T2 is provided. The output section of the pixel circuit 1A outputs a value corresponding to the value counted up by the first counter section 111 in the first period T1, or a value corresponding to the value counted up by the second counter section 112 in the second period T2. A value corresponding to the difference between the value counted up by the first counter unit 111 in the first period T1 and the value counted down by the first counter unit 111 in the second period T2, outputting at least one as the first signal S1; Alternatively, at least one of the values corresponding to the difference between the value counted up by the second counter unit 112 in the second period T2 and the value counted down by the second counter unit 112 in the first period T1 is output as the second signal S2. . That is, according to the signal processing device 10A, the second counter section 112 moves in opposite phase to the first counter section 111, so that each counter section outputs a video signal and a difference signal in one cycle. do. Therefore, according to this embodiment, both the video signal and the difference signal can be acquired in both odd-numbered frames and even-numbered frames.

Note that the pixel circuit 1A according to the second embodiment has a drawback that the circuit scale is larger than that of the pixel circuit 1. Therefore, by adopting the three-dimensional structure as shown in FIG. 1, even if the signal processing device 10A is mounted with a counter for each pixel, an increase in pixel size can be avoided, and high-resolution imaging can be realized.

Note that in the second embodiment, two counters are provided in opposite phases, but without increasing the number of counters (that is, by using the same hardware configuration as in the first embodiment), both odd and even frames can be processed. There may also be a desire to obtain both a video signal and a difference signal. In this case, this can be achieved by driving the counters of adjacent pixels in opposite phases. That is, by using any of the adjacent pixels, it is possible to increase the temporal resolution instead of decreasing the spatial resolution. In this case, existing image interpolation processing techniques may be applied between adjacent pixels to improve the lost spatial resolution.

The effects described herein are merely illustrative or exemplary, and are not limiting. In other words, the technology according to the present disclosure can have other effects that are obvious to those skilled in the art from the description of this specification, in addition to or in place of the above effects. Further, the present invention is not limited to these embodiments in any way, and various modifications and substitutions can be made without departing from the spirit of the present invention.

5 Solid-state image sensor 1 Pixel circuit 10 Signal processing device 11 Pulse signal acquisition section 12 Counter section 13 Trigger signal generation circuit 20 Light amount detection device 21 Photodiode 22 Inverter chain 23 Reset transistor S1 First signal S2 Second signal 110 First signal processing Section 120 Second signal processing section 111 First counter section 112 Second counter section T1 First period T2 Second period

Claims (10)

an acquisition unit that acquires a value that changes over time;
a counter unit that counts up or down depending on whether the period is the first period or the second period in a period including a first period and a second period;
A signal processing device comprising: an output section that outputs a first signal corresponding to a value counted up by the counter section and a second signal corresponding to a difference between a value counted up and a value counted down by the counter section. . The counter section is
a first counter unit that counts up during the first period and counts down during the second period;
a second counter unit that counts down in the first period and counts up in the second period;
The output section is
Output as the first signal at least one of a value according to the value up-counted by the first counter section in the first period, or a value according to the value up-counted by the second counter section during the second period. death,
A value corresponding to the difference between the value counted up by the first counter unit in the first period and the value counted down by the first counter unit in the second period, or the value counted up by the second counter unit in the second period. The signal processing device according to claim 1, wherein at least one of a value corresponding to a difference between a value counted up by the second counter unit and a value counted down by the second counter unit in the first period is outputted as the second signal. The counter section includes a multi-bit counter element,
The signal processing device according to claim 1, wherein the second signal includes a trigger signal that is output depending on whether an output value of one of the counter elements included in the counter section is 0 or 1. The signal processing device according to claim 3, wherein the second signal includes a code signal that is an output value of the most significant bit of the counter element included in the counter unit. The signal processing device according to claim 3, wherein the least significant bit of the counter elements included in the counter section has an enable terminal that determines whether the input signal is valid. The signal processing device according to any one of claims 1 to 5, wherein the acquisition unit acquires a pulse signal whose value changes over time to a digital value of 1 or 0. The acquisition unit acquires an analog value whose value changes continuously,
The signal processing device according to any one of claims 1 to 5, further comprising an A/D conversion unit that converts the analog value into a digital value according to a comparison result between the analog value and a predetermined threshold. The signal processing device according to claim 7, wherein the acquisition unit acquires a voltage value according to a result of light incident on the photodiode. The signal processing device according to claim 8 , further comprising a reset transistor that determines whether to apply a reset voltage to the photodiode depending on the digital value output by the A/D conversion section. an acquisition step of acquiring values that change over time;
In a cycle including a first period and a second period, a counter step of counting up or down depending on whether it is the first period or the second period;
A signal processing method comprising: an output step of outputting a first signal corresponding to the value counted up in the counter step and a second signal corresponding to the difference between the value counted up and the value counted down in the counter step. .

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