CN220709657U

CN220709657U - Airborne bus data transmission device with different transmission protocols

Info

Publication number: CN220709657U
Application number: CN202322258313.4U
Authority: CN
Inventors: 马真安; 许少尉; 董延军; 陈思宇; 杨敬宝; 崔西宁
Original assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Current assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Priority date: 2023-08-22
Filing date: 2023-08-22
Publication date: 2024-04-02
Anticipated expiration: 2033-08-22

Abstract

The utility model provides an airborne bus data transmission device with different transmission protocols, which comprises a data conversion structure. The data conversion structure comprises a transceiver, a conversion unit and a register which are sequentially connected, wherein the input end of the transceiver is connected with a first bus module, the output end of the register is connected with a second bus module, and the data type of the first bus module is different from the data type of the second bus module. The airborne bus data transmission device disclosed by the utility model can solve the problems that the CPU working speed is influenced and error codes or missing errors occur due to the fact that memory occupation exists when airborne bus data are transmitted through different transmission protocols in the prior art, and the device can improve the working efficiency on one hand and can realize the interaction of the airborne bus data among different protocols rapidly, efficiently and accurately on the other hand.

Description

Airborne bus data transmission device with different transmission protocols

Technical Field

The utility model belongs to the field of electronic information, relates to a data transmission design technology, and particularly relates to an airborne bus data transmission device with different transmission protocols.

Background

With the continuous development of electronic communication technology, the speed and accuracy of transmitting on-board data between two independent peripheral modules/devices through buses with the same or different transmission protocols in a traditional chip are increasingly required. For example: when the onboard data is transmitted through buses of different types of transmission protocols, the transmission data formats and rates are different due to different protocols, and the number of bits of the transmission data is also different, so that the bus data transmission has higher complexity.

At present, for the transmission of the onboard bus data by adopting different protocols, the general method adopts units such as RAM, interrupt and CPU, firstly, the data to be transmitted is cached in a memory, then the CPU controls the transmission of the data through a data control bus, and the transmission mode occupies a memory to influence the working speed of the CPU, and the problems of data error code and loss to generate errors are easy to occur.

Disclosure of Invention

In order to solve the problems that the occupied memory influences the CPU working speed and error code or missing error occurs when the airborne bus data are transmitted through different transmission protocols in the prior art, the utility model discloses an airborne bus data transmission device of different transmission protocols, which can improve the working efficiency on one hand and can realize the interaction of the airborne bus data among different protocols rapidly, efficiently and accurately on the other hand.

The technical scheme for realizing the aim of the utility model is as follows: an on-board bus data transmission device with different transmission protocols comprises a data conversion structure.

The data conversion structure comprises a transceiver, a conversion unit and a register which are sequentially connected, wherein the input end of the transceiver is connected with a first bus module, the output end of the register is connected with a second bus module, and the data type of the first bus module is different from the data type of the second bus module.

Further, the first bus module is connected with the data conversion structure through a first bus, the second bus module is connected with the data conversion structure through a second bus, and the protocols of the first bus and the second bus are different.

Further, a selector is provided between the first bus module and the transceiver.

Still further, the selector includes a plurality of logic gates, each of the logic gates including an and gate, an or gate, and a nand gate.

Further, the conversion unit comprises a receiving buffer area, a decoding filtering area, an asynchronous FIFO area, an encoding control area and a sending buffer area, wherein the receiving buffer area is connected with the transceiver and receives the data of the first bus module output by the transceiver.

Further, the register is a shift register, and the model of the shift register is SN74HC166DRG4.

Compared with the prior art, the utility model has the beneficial effects that: according to the airborne bus data transmission device, the data exchange between the bus modules of two different protocols can be accurately and efficiently realized through designing the data conversion structure.

Meanwhile, the data which are not used for filtering can be shielded according to the requirements of a user through the arrangement of the selector, so that the data processing pressure of a decoding filtering area, an asynchronous FIFO area and an encoding control area can be reduced, and the data transmission efficiency is greatly improved.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described.

Fig. 1 is a schematic diagram of an on-board bus data transmission device with different transmission protocols according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of a selector in an embodiment of the utility model;

FIG. 3 is a schematic diagram of a converting unit according to an embodiment of the present utility model;

100, a data conversion structure; 101. a transceiver; 102. a conversion unit; 103. a register; 104. a selector; 200. a first bus module; 201. a first bus; 300. a second bus module; 301. a second bus; 1021. a receive buffer; 1022. decoding the filtering area; 1023. an asynchronous FIFO area; 1024. a coding control region; 1025. the buffer is sent.

Detailed Description

The utility model will be further described with reference to specific embodiments, and advantages and features of the utility model will become apparent from the description. These examples are merely exemplary and do not limit the scope of the utility model in any way. It will be understood by those skilled in the art that various changes and substitutions of details and forms of the technical solution of the present utility model may be made without departing from the spirit and scope of the present utility model, but these changes and substitutions fall within the scope of the present utility model.

An embodiment of the present utility model provides an on-board bus data transmission device with different transmission protocols, and referring to fig. 1, the on-board bus data transmission device includes a data conversion structure 100.

As shown in fig. 1, the data conversion structure 100 includes a transceiver 101, a conversion unit 102, and a register 103 connected in sequence, where an input end of the transceiver 101 is connected to a first bus module 200, an output end of the register 103 is connected to a second bus module 300, and a data type of the first bus module 200 is different from a data type of the second bus module 300.

Further, referring to fig. 1, the first bus module 200 is connected to the data conversion structure 100 via a first bus 201, the second bus module 300 is connected to the data conversion structure 100 via a second bus 301, and the protocols of the first bus 201 and the second bus 301 are different.

In a modified embodiment of the present utility model, a selector 104 is provided between the first bus module 200 and the transceiver 101.

Still further, referring to fig. 2, the selector 104 includes a plurality of logic gates, each including an and gate, an or gate, and a nand gate. The purpose of the selector 104 is to receive only data according to the intended bus protocol according to the user's needs, mask out unused data, and control the identifier ID of the received message itself according to the register 103, acpt indicating the received information, LAM bits being mask bits which are AME bits to achieve selective masking. The required bus protocol data selection can be achieved by the logic gates shown in fig. 2.

Further, referring to fig. 3, the converting unit 102 includes a receiving buffer 1021, a decoding filtering area 1022, an asynchronous FIFO area 1023, a coding control area 1024, and a transmitting buffer 1025, where the receiving buffer 1021 is connected to the transceiver 101, and receives the data of the first bus module 200 output by the transceiver 101; the decoding filtering area 1022 decodes the data outputted from the transceiver 101 to restore the encoded information of the data conforming to the protocol of the first bus module 200 to the original signal, so that it can be recognized and understood in the subsequent operation, and transfers the synchronous clock information and outputs it to the asynchronous FIFO area 1023; the asynchronous FIFO 1023 encodes the decoded and filtered data according to the data protocol type of the second bus module 300 and sends the encoded data to the encoding control 1024; the encoding control section 1024 compiles and converts the decoded data into a signal format that conforms to the available communication, transmission and storage of the second bus module 300; the transmission buffer 1025 outputs the encoded data to the register 103.

Further, the register 103 is a shift register with a shift function, for example, a shift register with a model SN74HC166DRG4 is selected, and the shift register has a function of converting 16-bit data into 32-bit data and also has a temporary storage function.

According to the airborne bus data transmission device, the data exchange between the bus modules of two different protocols can be accurately and efficiently realized through designing the data conversion structure.

Meanwhile, the arrangement of the selector can shield and filter unused data according to the user demands, so that the processing pressures of the decoding filtering area 1022, the asynchronous FIFO area 1023 and the coding control area 1024 can be reduced, and the data transmission efficiency can be greatly improved.

The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the utility model.

Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.

Claims

1. An airborne bus data transmission device with different transmission protocols is characterized in that: the data conversion structure comprises a selector, a transceiver, a conversion unit and a register which are sequentially connected, wherein the input end of the transceiver is connected with a first bus module through the selector, the output end of the register is connected with a second bus module, and the data type of the first bus module is different from the data type of the second bus module;

the selector includes a plurality of logic gates, each of the logic gates including an AND gate, an OR gate, and a NAND gate.

2. The on-board bus data transmission device of claim 1, wherein: the first bus module is connected with the data conversion structure through a first bus, the second bus module is connected with the data conversion structure through a second bus, and the protocols of the first bus and the second bus are different.

3. The on-board bus data transmission device of claim 1, wherein: the conversion unit comprises a receiving buffer area, a decoding filtering area, an asynchronous FIFO area, an encoding control area and a sending buffer area, wherein the receiving buffer area is connected with the transceiver and receives data of the first bus module output by the transceiver.

4. The on-board bus data transmission device of claim 1, wherein: the register is a shift register, and the model of the shift register is SN74HC166DRG4.