CN220569662U - Integrated circuit package product - Google Patents

Abstract

An integrated circuit package product. The integrated circuit packaging product comprises a substrate, an insulating medium layer and an isolation groove. The insulating medium layer is arranged on the substrate. The isolation groove is arranged on the substrate. The isolation trench is disposed around the integrated circuit chip and exposes a top surface of the substrate.

Description

Integrated circuit package product

Technical Field

The present utility model relates to the field of semiconductors, and more particularly, to an integrated circuit package product.

Background

In the prior art, it is often necessary for some integrated circuit products to use an encapsulant to form a cavity around the integrated circuit chip. However, due to the certain fluidity of the sealant, the sealant spreads outwards before heating and curing, so that the sealant spreads to surrounding chips and devices to influence the performance of the product.

Disclosure of Invention

In view of the above, the present application proposes an integrated circuit package product to solve the above-mentioned problems.

In accordance with one embodiment of the present application, an integrated circuit package product is provided. The integrated circuit packaging product comprises a substrate, an insulating medium layer and an isolation groove. The insulating medium layer is arranged on the substrate. The isolation groove is arranged on the substrate. The isolation trench is disposed around the integrated circuit chip and exposes a top surface of the substrate.

According to an embodiment of the present application, the integrated circuit package product further comprises metal contacts. The metal contact is arranged on the substrate and embedded in the insulating dielectric layer. The metal contact is arranged in the area surrounded by the isolation groove.

According to an embodiment of the application, the metal contact is disposed between the isolation groove and the integrated circuit chip, and the metal contact and the integrated circuit chip are connected through a conductive wire.

According to an embodiment of the present application, the metal contacts are disposed under the integrated circuit chip. The metal contact is connected with the lower surface of the integrated circuit chip.

According to an embodiment of the application, the isolation trench is closed on the substrate around the integrated circuit chip.

According to an embodiment of the application, the isolation trenches are spaced around the integrated circuit chip on the substrate.

According to an embodiment of the present application, the integrated circuit package product further includes an encapsulant. The sealing glue is arranged on the insulating medium layer. The sealant forms a cavity around the enclosed region. The integrated circuit chip and the isolation trench are disposed in the cavity.

In the integrated circuit packaging product provided by the application, through set up the isolation groove at integrated circuit chip and metal contact periphery for in the installation of integrated circuit packaging product, seal glues if to the diffuse time delay all around, can diffuse to the isolation groove in, and under the isolation of isolation groove, stop to integrated circuit chip and metal contact diffuse, and then cause the harm of integrated circuit chip and metal contact.

Drawings

The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and, together with the description, do not limit the application. In the drawings:

fig. 1 illustrates a cross-sectional view of an integrated circuit package product according to an embodiment of the present application.

Fig. 2A illustrates a top view of an integrated circuit package product according to an embodiment of the present application.

Fig. 2B illustrates a top view of an integrated circuit package product according to an embodiment of the present application.

Fig. 3 illustrates a cross-sectional view of an integrated circuit package product according to another embodiment of the present application.

Fig. 4 illustrates a cross-sectional view of an integrated circuit package product according to another embodiment of the present application.

Fig. 5A illustrates a top view of an integrated circuit package product according to an embodiment of the present application.

Fig. 5B illustrates a top view of an integrated circuit package product according to an embodiment of the present application.

Detailed Description

The following disclosure provides various embodiments or examples that can be used to implement the various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. It is to be understood that these descriptions are merely exemplary and are not intended to limit the present disclosure. For example, in the following description, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may include embodiments in which additional components are formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. Such reuse is for brevity and clarity purposes and does not itself represent a relationship between the different embodiments and/or configurations discussed.

Moreover, spatially relative terms, such as "under," "below," "lower," "upper," and the like, may be used herein to facilitate a description of the relationship between one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be placed in other orientations (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally means that the actual value is within plus or minus 10%, 5%, 1% or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within an acceptable standard error of the average value, depending on the consideration of those ordinarily skilled in the art to which the present application pertains. It is to be understood that all ranges, amounts, values, and percentages used herein (e.g., to describe amounts of materials, lengths of time, temperatures, operating conditions, ratios of amounts, and the like) are modified by the word "about" unless otherwise specifically indicated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present specification and attached claims are approximations that may vary depending upon the desired properties. At least these numerical parameters should be construed as the number of significant digits and by applying ordinary rounding techniques. Herein, a numerical range is expressed as from one end point to another end point or between two end points; unless otherwise indicated, all numerical ranges recited herein include endpoints.

Fig. 1 illustrates a cross-sectional view of an integrated circuit package product 1 according to an embodiment of the present application. In some embodiments, the integrated circuit package product 1 may be an integrated circuit product that includes a cavity structure. In some embodiments, the integrated circuit package product 1 includes a substrate 100, an insulating dielectric layer 101, an isolation trench 102, an integrated circuit chip 103, metal contacts 104, conductive lines 105, and an encapsulant 106. In some embodiments, encapsulant 106 is disposed over dielectric layer 101. The encapsulant 106 forms a cavity around the enclosed region A1, wherein the isolation trench 102 and the integrated circuit chip 103 are disposed in the cavity.

In some embodiments, an insulating dielectric layer 101 is disposed on the substrate 100. In some embodiments, the insulating dielectric layer 101 is used for insulation, and the insulating dielectric layer 101 may not have photosensitive characteristics. In some embodiments, isolation trenches 102 are provided on substrate 100. In some embodiments, isolation trenches 102 are disposed over substrate 100 and formed in insulating dielectric layer 101. In some embodiments, isolation trenches 102 are disposed around integrated circuit chip 103 and expose a top surface of substrate 100. In some embodiments, the isolation trenches 102 penetrating the insulating dielectric layer 101 and exposing the top surface of the substrate 100 may be processed by a laser process or a copper pillar process or the like. In some embodiments, the insulating dielectric layer 101 is a photosensitive insulating dielectric layer, and the isolation trench 102 may also be processed by exposing and developing the photosensitive insulating dielectric layer 101.

In some embodiments, metal contacts 104 are disposed on substrate 100 and embedded within insulating dielectric layer 101. Referring to fig. 2A, fig. 2A illustrates a top view of an integrated circuit package product 1 according to an embodiment of the present application. In some embodiments, isolation trenches 102 are spaced around integrated circuit chip 103 and metal contacts 104 on substrate 100. In some embodiments, the metal contacts 104 are disposed within the region of the isolation trench 102 that is circumferentially surrounded by the space such that the metal contacts 104 are disposed between the isolation trench 102 and the integrated circuit chip 103. The integrated circuit chip 103 is connected to the metal contacts 104 by conductive lines 105.

By arranging the isolation groove 102 at the periphery of the integrated circuit chip 103 and the metal contact 104, the sealing adhesive 106 can be spread into the isolation groove 102 if being spread to the periphery in the installation process of the integrated circuit packaging product 1, and the integrated circuit chip 103 and the metal contact 104 are stopped from being spread under the isolation of the isolation groove 102, so that the integrated circuit chip 103 and the metal contact 104 are damaged.

It should be noted that, although in the embodiment of fig. 2A, the isolation trenches 102 are formed on the substrate 100 to surround the integrated circuit chip 103 and the metal contacts 104 at intervals, the distribution shape of the isolation trenches 102 may be set according to practical requirements. Referring to fig. 2B, fig. 2B illustrates a top view of an integrated circuit package product 1 according to another embodiment of the present application. In the embodiment of fig. 2B, isolation trenches 102 are closed on substrate 100 around integrated circuit chip 103 and metal contacts 104. Likewise, metal contacts 104 are disposed within the area of isolation trenches 102 that is spaced around the perimeter such that metal contacts 104 are disposed between isolation trenches 102 and integrated circuit chip 103. The integrated circuit chip 103 is connected to the metal contacts 104 by conductive lines 105.

Referring again to fig. 1, in some embodiments, the depth h of isolation trenches 102 (i.e., the thickness of insulating dielectric layer 101) is approximately in the range of 15-45 um. In some embodiments, the width W1 of the isolation trenches 102 is approximately in the range of 50-200 um. In some embodiments, the retained distance W2 between isolation trenches 102 and metal contacts 104 is approximately in the range of 50-200 um.

It should be noted that, although in the above embodiment, the metal contact 104 is a metal contact body formed by filling the trench in the insulating dielectric layer 101 with a conductive material, this is not a limitation of the present application. In other embodiments, the metal contact 104 may be formed by partially filling a trench in the insulating dielectric layer 101 with a conductive material. In the integrated circuit product 1' shown in fig. 3, the metal contact 104 is formed by only partially filling the trench in the insulating dielectric layer 101 with the conductive material, and the metal contact 104 is not in full contact with the insulating dielectric layer 101. It should be understood by those skilled in the art that the purpose of the metal contacts 104 is to electrically connect with the integrated circuit chip 103 via the conductive lines 105 and further connect with the circuits in the substrate 100, so long as the dimensions of the metal contacts 104 meet the soldering requirements of the conductive lines 105.

In the embodiment of fig. 1 and 3, the integrated circuit chip 103 is connected to metal contacts 104, and thus to circuitry in the substrate 100, by conductive lines 105. However, this is not a limitation of the present application. Referring to fig. 4, fig. 4 illustrates a cross-sectional view of an integrated circuit package product 4 according to an embodiment of the present application. In some embodiments, the integrated circuit package product 4 includes a substrate 400, an insulating dielectric layer 401, isolation trenches 402, an integrated circuit chip 403, metal contacts 404, and an encapsulant 406. The substrate 400, insulating dielectric layer 401, isolation trench 402, integrated circuit chip 403, and encapsulant 406 of the integrated circuit package product 4 are substantially the same as the substrate 100, insulating dielectric layer 101, isolation trench 102, integrated circuit chip 103, and encapsulant 106 of the embodiment of fig. 1, except for the configuration of the metal contacts 404. Therefore, the same parts of the integrated circuit package product 4 as those of the integrated circuit package product 1 are omitted here for brevity.

In some embodiments, metal contacts 404 are disposed on substrate 400 and embedded within insulating dielectric layer 401. In some embodiments, metal contacts 404 are disposed under integrated circuit chip 403, with metal contacts 404 being connected to the lower surface of the integrated circuit chip. By providing the metal contact 404 connected thereto under the integrated circuit chip 403, the provision of the conductive line 405 can be omitted.

Referring to fig. 5A, fig. 5A illustrates a top view of an integrated circuit package product 4 according to an embodiment of the present application. In some embodiments, isolation trenches 402 are spaced around integrated circuit chip 403 and metal contacts 404 on insulating dielectric layer 401. By arranging the isolation groove 402 at the periphery of the integrated circuit chip 403 and the metal contact 404, the sealing glue 406 can be spread into the isolation groove 402 if being spread to the periphery in the installation process of the integrated circuit packaging product 4, and the spreading to the integrated circuit chip 403 and the metal contact 404 is stopped under the isolation of the isolation groove 402, so that the integrated circuit chip 403 and the metal contact 404 are damaged.

It should be noted that, although in the embodiment of fig. 5A, the isolation trenches 402 are formed on the insulating dielectric layer 401 to surround the integrated circuit chip 403 and the metal contacts 404 at intervals, the distribution shape of the isolation trenches 402 may be set according to practical requirements. Referring to fig. 5B, fig. 5B illustrates a top view of an integrated circuit package product 4 according to another embodiment of the present application. In the embodiment of fig. 5B, isolation trenches 402 are closed over insulating dielectric layer 401 around integrated circuit chip 403.

It should be understood by those skilled in the art that, in order to more effectively block the spreading of the sealing compound and damage the integrated circuit chip and other components, a plurality of isolation grooves may be additionally provided on the basis of the above embodiments, so as to increase the blocking effect. One skilled in the art will readily understand the structure of the product with the additional isolation grooves after reading the above embodiments. Detailed description is omitted here.

As used herein, the terms "approximately," "substantially," and "about" are used to describe and account for minor variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely and instances where it occurs to the close approximation. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1% or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to the other endpoint, or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term "substantially coplanar" may refer to two surfaces within a few micrometers (μm) positioned along a same plane, for example, within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm positioned along the same plane. When referring to "substantially" the same value or property, the term may refer to a value that is within ±10%, 5%, 1% or 0.5% of the average value of the values.

As used herein, the terms "approximately," "substantially," and "about" are used to describe and explain minor variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely and instances where it occurs to the close approximation. For example, when used in conjunction with a numerical value, the term can refer to a range of variation of less than or equal to ±10% of the numerical value, e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values may be considered to be "substantially" or "about" the same if the difference between the two values is less than or equal to ±10% (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%) of the average value of the values. For example, "substantially" parallel may refer to a range of angular variation of less than or equal to ±10° relative to 0 °, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, "substantially" perpendicular may refer to a range of angular variation of less than or equal to ±10° relative to 90 °, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

For example, two surfaces may be considered to be coplanar or substantially coplanar if the displacement between the two surfaces is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm. A surface may be considered planar or substantially planar if the displacement of the surface relative to the plane between any two points on the surface is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm.

As used herein, the singular terms "a" and "an" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the former component is directly on (e.g., in physical contact with) the latter component, as well as the case where one or more intermediate components are located between the former component and the latter component.

As used herein, spatially relative terms such as "below," "lower," "above," "upper," "lower," "left," "right," and the like may be used herein for ease of description to describe one component or feature's relationship to another component or feature as illustrated in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

The foregoing has outlined features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure and are susceptible to various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

Claims (7)

1. An integrated circuit package product, comprising:

a substrate;

an insulating medium layer arranged on the substrate; and

and the isolation groove is arranged on the substrate, surrounds the integrated circuit chip and exposes the top surface of the substrate.

2. The integrated circuit package product of claim 1, further comprising:

and the metal contact is arranged on the substrate and embedded in the insulating dielectric layer, and the metal contact is arranged in the area surrounded by the isolation groove.

3. The integrated circuit package product of claim 2, wherein the metal contacts are disposed between the isolation trenches and the integrated circuit chip, the metal contacts and the integrated circuit chip being connected by conductive lines.

4. The integrated circuit package product of claim 2, wherein the metal contacts are disposed under the integrated circuit chip, the metal contacts being connected to a lower surface of the integrated circuit chip.

5. The integrated circuit package product of claim 1, wherein the isolation trench encloses the integrated circuit chip on the substrate.

6. The integrated circuit package product of claim 1, wherein the isolation trenches are spaced around the integrated circuit chip on the substrate.

7. The integrated circuit package product of claim 1, further comprising:

and the sealing glue is arranged on the insulating medium layer, a cavity is formed by surrounding the sealing glue with the surrounding area, and the integrated circuit chip and the isolation groove are arranged in the cavity.