CN220543916U - High-power switch module - Google Patents

Abstract

The utility model discloses a high-power switch module, relates to the technical field of semiconductors, and solves the technical problem of low reliability of the existing power semiconductor module. The module comprises: a DBC ceramic substrate, a positive terminal, a negative terminal and a plurality of chip modules disposed on the DBC ceramic substrate; the chips are connected in series end to end, the positive terminal is connected with the first chip module of the chip modules, and the negative terminal is connected with the last chip module of the chip modules. The positive terminal, the negative terminal and the plurality of chip modules are connected in series, so that stray inductance in the modules can be reduced, voltage is divided, the high-power switch module is suitable for high-power application scenes, and the reliability of the switch module is improved.

Description

High-power switch module

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a high-power switch module.

Background

Power semiconductor modules, also known as power electronics, which generally function as power processors, are semiconductor devices with the ability to handle high voltages, large currents, including frequency conversion, voltage transformation, current conversion, power management, and the like.

In the existing high-power semiconductor device, when the voltage exceeds 2kV, the device is broken down or damaged due to the fact that excessive power cannot be born, so that the existing module is designed in a multi-chip serial-parallel connection mode in order to adapt to more high-power application scenes, but the reliability of the power semiconductor device is affected by the stray inductance of the multi-chip serial-parallel connection module. The power terminal of the existing power semiconductor device is often welded on the preset position of the PCB in the form of a contact pin, a patch and the like, but certain errors are inevitably generated in the welding process due to the fact that the PCB is smooth, so that the power module cannot be accurately welded on the expected appointed position, and the reliability of a product is reduced. Therefore, the existing power semiconductor module has the problems of low overvoltage and overcurrent capacity, large stray inductance, low product reliability caused by the fact that the existing power semiconductor module cannot be accurately welded at a preset position, and the like.

In the process of implementing the present utility model, the inventor finds that at least the following problems exist in the prior art:

the existing power semiconductor module has low reliability.

Disclosure of Invention

The utility model aims to provide a high-power switch module so as to solve the technical problem of low reliability of a power semiconductor module in the prior art. The preferred technical solutions of the technical solutions provided by the present utility model can produce a plurality of technical effects described below.

In order to achieve the above purpose, the present utility model provides the following technical solutions:

the utility model provides a high-power switch module, which is characterized by comprising: a DBC ceramic substrate, a positive terminal, a negative terminal and a plurality of chip modules disposed on the DBC ceramic substrate; the chips are connected in series end to end, the positive terminal is connected with the first chip module of the chip modules, and the negative terminal is connected with the last chip module of the chip modules.

Preferably, the DBC ceramic substrate includes a ceramic layer, a first copper-clad layer and a second copper-clad layer, the ceramic layer is disposed between the first copper-clad layer and the second copper-clad layer, and the positive terminal, the negative terminal and the plurality of chip modules are disposed on the second copper-clad layer.

Preferably, the second copper-clad layer is etched with a negative electrode terminal copper layer and a plurality of chip module copper layers, the negative electrode terminal is arranged on the negative electrode terminal copper layer, each of the plurality of chip modules is arranged on one chip module copper layer, and the positive electrode terminal is arranged on the chip module copper layer corresponding to the first chip module.

Preferably, each chip module comprises a first power chip, a second power chip, a gate control terminal and a sampling terminal; each chip module copper layer comprises a chip copper layer, a gate control terminal copper layer and a sampling terminal copper layer;

in the chip module copper layer corresponding to each chip module, the first power chip and the second power chip are both arranged on the chip copper layer, the gate control terminal is arranged on the gate control terminal copper layer, and the sampling terminal is arranged on the sampling terminal copper layer.

Preferably, in each chip module, the gate electrode control terminal copper layer is connected with the gate electrode of the first power chip through a bonding wire, and the sampling terminal copper layer is connected with a position, except the gate electrode, on the first power chip through a bonding wire;

in the adjacent two chip modules, the adjacent two first power chips are connected in series, and the adjacent two second power chips are connected in series.

Preferably, in the chip module copper layer corresponding to each chip module, the first power chip and the second power chip are welded with the chip copper layer in a vacuum reflow soldering manner by using solder, and the gate control terminal and the sampling terminal are respectively connected with the gate control terminal copper layer and the sampling terminal copper layer in a solder bonding or vacuum reflow soldering manner;

the positive terminal and the negative terminal are respectively connected with the first chip module copper layer and the negative terminal copper layer in a solder bonding or vacuum reflow soldering mode.

Preferably, the gate control terminal copper layer and the sampling terminal copper layer on each chip module copper layer are located at the side edges of the second copper-clad layer, and the gate control terminals and the sampling terminals on the plurality of chip module copper layers are arranged in a paddle shape.

Preferably, the gate control terminal and the sampling terminal are in a strip shape, the positive terminal and the negative terminal are in a sheet shape, and the arrangement shape of the positive terminal, the negative terminal and the plurality of chip modules is a plane U shape.

Preferably, the ceramic layer, the first copper-clad layer and the second copper-clad layer are connected through hot pressing, welding or low-temperature sintering by a planar ceramic substrate process.

Preferably, an encapsulation colloid is arranged on the second copper-clad layer, and encapsulates the positive electrode terminal, the negative electrode terminal, the plurality of chip modules, the plurality of chip module copper layers and the negative electrode terminal copper layer.

By implementing one of the technical schemes, the utility model has the following advantages or beneficial effects:

the positive terminal, the negative terminal and the plurality of chip modules are connected in series, so that stray inductance in the modules can be reduced, voltage is divided, the high-power switch module is suitable for high-power application scenes, and the reliability of the switch module is improved.

Drawings

For a clearer description of the technical solutions of embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art, in which:

FIG. 1 is a first perspective view of an overall structure of an embodiment of the present utility model;

FIG. 2 is a schematic diagram of the current flow in an embodiment of the utility model;

FIG. 3 is a second perspective view of the overall structure of an embodiment of the present utility model;

fig. 4 is a schematic diagram of the structure of each copper layer on the second copper-clad layer according to the embodiment of the present utility model.

In the figure: 1. a DBC ceramic substrate; 11. a ceramic layer; 12. a first copper-clad layer; 13. a second copper-clad layer; 14. a negative terminal copper layer; 15. a chip copper layer; 151. a first power chip region; 152. a second power chip region; 16. a gate control terminal copper layer; 17. sampling a terminal copper layer; 2. a positive electrode terminal; 3. a negative electrode terminal; 4. a first power chip; 41. a gate electrode; 5. a second power chip; 6. a gate control terminal; 7. a sampling terminal; 8. and (5) bonding wires.

Detailed Description

For a better understanding of the objects, technical solutions and advantages of the present utility model, reference should be made to the various exemplary embodiments described hereinafter with reference to the accompanying drawings, which form a part hereof, and in which are described various exemplary embodiments which may be employed in practicing the present utility model. The same reference numbers in different drawings identify the same or similar elements unless expressly stated otherwise. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. It is to be understood that they are merely examples of processes, methods, apparatuses, etc. that are consistent with certain aspects of the present disclosure as detailed in the appended claims, other embodiments may be utilized, or structural and functional modifications may be made to the embodiments set forth herein without departing from the scope and spirit of the present disclosure.

In the description of the present utility model, it should be understood that the terms "center," "longitudinal," "transverse," and the like are used in an orientation or positional relationship based on that shown in the drawings, and are merely for convenience in describing the present utility model and to simplify the description, rather than to indicate or imply that the elements referred to must have a particular orientation, be constructed and operate in a particular orientation. The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "plurality" means two or more. The terms "connected," "coupled" and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, integrally connected, mechanically connected, electrically connected, communicatively connected, directly connected, indirectly connected via intermediaries, or may be in communication with each other between two elements or in an interaction relationship between the two elements. The term "and/or" includes any and all combinations of one or more of the associated listed items. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

In order to illustrate the technical solutions of the present utility model, the following description is made by specific embodiments, only the portions related to the embodiments of the present utility model are shown.

Examples:

as shown in fig. 1, the present utility model provides a high power switch module, comprising: a DBC ceramic substrate 1, a positive electrode terminal 2, a negative electrode terminal 3, and a plurality of chip modules provided on the DBC ceramic substrate 1; the chips are connected in series end to end, the positive electrode terminal 2 is connected with the first chip module of the chip modules, and the negative electrode terminal 3 is connected with the last chip module of the chip modules.

Specifically, as shown in fig. 1, the positive electrode terminal 2, the negative electrode terminal 3 and a plurality of chip modules are all disposed on the DBC ceramic substrate 1, and chips on the plurality of chip modules are electrically connected in series end to end. The positive terminal 2 is connected with the first chip module, and a plurality of chip modules are connected in series in proper order in the middle, namely first chip module, second chip module, &..the last chip module is connected in series in proper order. The negative terminal 3 is arranged after the last chip module and is connected to the last chip module. As shown in fig. 2, the dotted arrows indicate the current flow direction, and since the positive electrode terminal 2, the plurality of chip modules, and the negative electrode terminal 3 are connected end to end in this order to form a series structure, the current flows from the positive electrode terminal 2 through the plurality of chip modules connected in series in the middle, and finally flows back to the negative electrode terminal 3 to form a series circuit. The positive terminal 2, the negative terminal 3 and the plurality of chip modules are connected in series, so that stray inductance in the modules can be reduced, voltage can be divided in a series mode, the high-power switch module is suitable for high-power application scenes, and the reliability of the switch module is improved.

As an alternative embodiment, as shown in fig. 3, the DBC ceramic substrate 1 includes a ceramic layer 11, a first copper clad layer 12, and a second copper clad layer 13, the ceramic layer 11 being disposed between the first copper clad layer 12 and the second copper clad layer 13, and the positive electrode terminal 2, the negative electrode terminal 3, and the plurality of chip modules being disposed on the second copper clad layer 13. Specifically, the ceramic layer 11, the first copper-clad layer 12 and the second copper-clad layer 13 are connected by hot pressing, welding or low-temperature sintering through a planar ceramic substrate process. In this embodiment, the planar ceramic substrate process includes, but is not limited to, a DBC process and an AMB process. The welding mode includes, but is not limited to, inorganic glue welding. The second copper-clad layer 13 is provided with a plurality of copper layers for correspondingly placing the positive electrode terminal 2, the negative electrode terminal 3 and a plurality of chip modules, and errors in the welding process can be avoided and the stability and reliability of welding are improved due to the fact that the positive electrode terminal, the negative electrode terminal or the chip modules are placed at the corresponding positions.

As an alternative embodiment, as shown in fig. 1, the second copper-clad layer 13 is etched with a negative terminal copper layer 14 and a plurality of chip module copper layers, the negative terminal 3 is disposed on the negative terminal copper layer 14, each of the plurality of chip modules is disposed on one chip module copper layer, and the positive terminal 2 is disposed on the chip module copper layer corresponding to the first chip module.

Specifically, when the negative electrode terminal 3, the positive electrode terminal 2 and the plurality of chip modules are required to be placed on the DBC ceramic substrate 1 for welding, the negative electrode terminal 3 is only required to be placed on the negative electrode terminal copper layer 14, the positive electrode terminal 2 is placed on the chip copper layer 15 corresponding to the first chip module, each chip module is correspondingly placed on each chip module copper layer, welding can be performed, the negative electrode terminal 3, the positive electrode terminal 2 and the chip modules are not required to be fixed by using other auxiliary tools, the positions of the welding cannot be moved in the welding process, and the welding accuracy, stability and reliability of products can be improved.

As an alternative embodiment, as shown in fig. 1 and 4, each chip module includes a first power chip 4, a second power chip 5, a gate control terminal 6, and a sampling terminal 7; each chip module copper layer comprises a chip copper layer 15, a gate control terminal copper layer 16 and a sampling terminal copper layer 17, wherein the chip copper layer 15 comprises a first power chip area 151 and a second power chip area 152; in the chip module copper layer corresponding to each chip module, the first power chip 4 and the second power chip 5 are arranged in the first power chip area 151 and the second power chip area 152 on the chip copper layer 15, the gate control terminal 6 is arranged on the gate control terminal copper layer 16, and the sampling terminal 7 is arranged on the sampling terminal copper layer 17.

Specifically, each chip module copper layer includes a chip copper layer 15, a gate control terminal copper layer 16, and a sampling terminal copper layer 17, and the first power chip 4, the second power chip copper layer 152, the gate control terminal copper layer 16, and the sampling terminal copper layer 17 are disposed on the first power chip region 151, the second power chip region 152, the gate control terminal copper layer 16, and the sampling terminal copper layer 17, respectively, and can be soldered. Each chip module has a corresponding position on each chip copper layer 15 and is connected with the chip copper layers 15, so that the positions of the chip modules cannot be moved in the welding process, and the welding accuracy and reliability can be improved.

As shown in fig. 1, the first power chip 4 is an IGBT chip, and the second power chip 5 is an FRD chip. One IGBT chip and one FRD chip are preferably provided on each chip module.

As an alternative embodiment, in each chip module, the first power chip 4 and the second power chip 5 are connected in parallel through the bonding wire 8, the gate control terminal copper layer 16 is connected with the gate 41 of the first power chip 4 through the bonding wire 8, and the sampling terminal copper layer 17 is connected with the position except the gate 41 on the first power chip 4 through the bonding wire 8; in the adjacent two chip modules, the adjacent two first power chips 4 are connected in series, and the adjacent two second power chips 5 are connected in series. From the positive electrode terminal 2, two adjacent first power chips 4 are connected in series, two adjacent second power chips 5 are connected in series, and the connection ends to the negative electrode terminal 3, so that a series structure is formed, voltage can be divided, and parasitic inductance can be reduced. Specifically, the bonding wire 8 is made of aluminum wire and copper wire, and aluminum wire is preferable in the present utility model.

As an alternative embodiment, in the chip module copper layer corresponding to each chip module, the first power chip 4 and the second power chip 5 are respectively welded with the first power chip area 151 and the second power chip area 152 on the chip copper layer 15 in a vacuum reflow soldering manner through solder, and the gate control terminal 6 and the sampling terminal 7 are respectively connected with the gate control terminal copper layer 16 and the sampling terminal copper layer 17 in a solder bonding manner or a vacuum reflow soldering manner; the positive terminal 2 and the negative terminal 3 are connected to the first chip module copper layer and the negative terminal copper layer 14, respectively, by means of solder bonding or vacuum reflow soldering.

Specifically, the positive electrode terminal 2, the negative electrode terminal 3, the first power chip 4, the second power chip 5, the gate control terminal 6 and the sampling terminal 7 are all made of weldable metal materials such as copper, aluminum, copper alloy, aluminum alloy, electro-gold plating, nickel, tin, silver and the like.

The first power chip 4 and the second power chip 5 are soldered to the first power chip region 151 and the second chip region 15, respectively, in a vacuum reflow manner using solder paste or nano silver paste. The gate control terminal 6 and the sampling terminal 7 are bonded or vacuum reflow soldered with solder paste or nano silver paste, respectively, to the gate control terminal copper layer 16 and the sampling terminal copper layer 17. The positive electrode terminal 2 is bonded or vacuum reflow-soldered to the first chip module copper layer using a solder paste or nano-silver solder paste, and the negative electrode terminal 3 is bonded or vacuum reflow-soldered to the negative electrode terminal copper layer 14. Specifically, the vacuum reflow soldering has the characteristics of uniform and consistent temperature, ultra-low temperature safe soldering, no temperature difference, no overheating, reliable and stable technological parameters, no need of complex technological tests, low environment-friendly cost operation and the like, can better perform soldering, improves the soldering quality and further improves the reliability.

The positive electrode terminal 2, the negative electrode terminal 3, the first power chip 4, the second power chip 5, the gate electrode control terminal 6 and the sampling terminal 7 can be arranged on the corresponding copper layers, so that the correct welding of the positive electrode terminal can be ensured, the welding quality of the positive electrode terminal can be ensured, and the reliability of the positive electrode terminal can be improved.

As an alternative embodiment, as shown in fig. 1, the gate control terminal copper layer 16 and the sampling terminal copper layer 17 on each chip module copper layer are located at the side of the second copper-clad layer 13, and the gate control terminals 6 and the sampling terminals 7 on the plurality of chip module copper layers are arranged in a paddle shape.

Specifically, regarding each chip module, the distribution positions of the gate control terminal copper layer 16 and the sampling terminal copper layer 17 of each chip module are identical, as shown in fig. 1, the sampling terminal copper layer 17 is disposed on the left side and the gate control terminal copper layer 16 is disposed on the right side below the chip copper layer of each chip module, so that the plurality of gate control terminal copper layers 16 and the sampling terminal copper layer 17 are disposed at intervals. In this way, in each chip module, the gate control terminal copper layer 16 is connected to the gate on the first power chip 4, and the sampling terminal copper layer 17 is connected to a position on the first power chip 4 other than the gate, avoiding the cross-connection when using the bonding wire 8 for connection. The gate control terminal 6 and the sampling terminal 7 are arranged on the gate control terminal copper layer 16 and the sampling terminal copper layer 17, and the gate control terminal 6 and the sampling terminal 7 are arranged in a paddle type.

As an alternative embodiment, the gate control terminal 6 and the sampling terminal 7 are elongated, the positive electrode terminal 2 and the negative electrode terminal 3 are sheet-shaped, and the arrangement shape of the positive electrode terminal 2, the negative electrode terminal 3, and the plurality of chip modules is a planar U-shape.

Specifically, the gate control terminal 6 and the sampling terminal 7 are set to be long strips, the positive electrode terminal 2 and the negative electrode terminal 3 are set to be sheet-shaped, and are arranged on the second copper-clad layer 13 in a plane state, so that the situation that the gate control terminal 6, the sampling terminal 7, the positive electrode terminal 2 and the negative electrode terminal 3 are uneven after welding is avoided, and subsequent packaging is facilitated. In the present utility model, the copper layers of the chip modules are arranged in two rows on the second copper-clad layer 13, and each row is provided with five copper layers of the chip modules for placing five chip modules, and according to the connection manner between the positive electrode terminal 2, the negative electrode terminal 3 and the plurality of chip modules described above, the positive electrode terminal 2, the negative electrode terminal 3 and the plurality of chip modules after being connected in series form a planar U shape. When the IGBT chip is conducted, the upper and lower rows of inductors can cancel each other, so that stray inductance of the switch module can be reduced, and reliability of the switch module is improved.

And adopt rectangular shaped gate control terminal 6 and sampling terminal 7, the positive electrode terminal 2 of slice shape welds with negative electrode terminal 3, and the current trend in the switch module is sharp, can further reduce stray inductance.

As an alternative embodiment, the second copper-clad layer 13 is provided with an encapsulation body, and the encapsulation body encapsulates the positive electrode terminal 2, the negative electrode terminal 3, the plurality of chip modules, the plurality of chip module copper layers and the negative electrode terminal copper layer 14.

Specifically, the packaging adhesive can wrap the positive electrode terminal 2, the negative electrode terminal 3, the plurality of chip modules, the plurality of chip module copper layers, the negative electrode terminal copper layer 14 and the bonding wire 8 connected with the plurality of chip modules, and package the positive electrode terminal, the negative electrode terminal, the plurality of chip modules, so that the switch module is kept stable in the use process. The packaging range of the packaging colloid is the range of the whole DBC ceramic substrate 1, and the preferable height of the packaging colloid is 3-5 cm. After the packaging colloid is used for packaging, the whole switch module can be packaged by adopting a plastic shell, and the annular shell can be used for packaging when the whole switch module is packaged again. However, since the module can be kept stable after being packaged by the packaging colloid, the module can be packaged without using a plastic shell, and the packaging can be specific according to actual use conditions.

The embodiment is a specific example only and does not suggest one such implementation of the utility model.

The foregoing is only illustrative of the preferred embodiments of the utility model, and it will be appreciated by those skilled in the art that various changes in the features and embodiments may be made and equivalents may be substituted without departing from the spirit and scope of the utility model. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the utility model without departing from the essential scope thereof. Therefore, it is intended that the utility model not be limited to the particular embodiment disclosed, but that the utility model will include all embodiments falling within the scope of the appended claims.

Claims (10)

1. A high power switch module, comprising: a DBC ceramic substrate (1), a positive electrode terminal (2), a negative electrode terminal (3) and a plurality of chip modules which are arranged on the DBC ceramic substrate (1); the chips are connected end to end in series, the positive electrode terminal (2) is connected with the first chip module of the chip modules, and the negative electrode terminal (3) is connected with the last chip module of the chip modules.

2. A high power switch module according to claim 1, characterized in that the DBC ceramic substrate (1) comprises a ceramic layer (11), a first copper-clad layer (12) and a second copper-clad layer (13), the ceramic layer (11) being arranged between the first copper-clad layer (12) and the second copper-clad layer (13), the positive terminal (2), the negative terminal (3) and the plurality of chip modules being arranged on the second copper-clad layer (13).

3. A high power switch module according to claim 2, characterized in that the second copper-clad layer (13) is etched with a negative terminal copper layer (14) and a plurality of chip module copper layers, the negative terminal (3) is arranged on the negative terminal copper layer (14), each of the plurality of chip modules is arranged on one chip module copper layer, and the positive terminal (2) is arranged on the chip module copper layer corresponding to the first chip module.

4. A high power switch module according to claim 3, characterized in that each of the chip modules comprises a first power chip (4), a second power chip (5), a gate control terminal (6) and a sampling terminal (7); each chip module copper layer comprises a chip copper layer (15), a gate control terminal copper layer (16) and a sampling terminal copper layer (17);

in the chip module copper layer corresponding to each chip module, the first power chip (4) and the second power chip (5) are both arranged on the chip copper layer (15), the gate control terminal (6) is arranged on the gate control terminal copper layer (16), and the sampling terminal (7) is arranged on the sampling terminal copper layer (17).

5. A high power switch module according to claim 4, characterized in that in each of the chip modules the gate control terminal copper layer (16) is connected to the gate (41) of the first power chip (4) by means of bond wires (8), and the sampling terminal copper layer (17) is connected to the first power chip (4) at a location other than the gate (41) by means of bond wires (8);

in the adjacent two chip modules, the adjacent two first power chips (4) are connected in series, and the adjacent two second power chips (5) are connected in series.

6. A high power switch module according to claim 4, characterized in that in the chip module copper layer corresponding to each chip module, the first power chip (4), the second power chip (5) are soldered with the chip copper layer (15) by means of vacuum reflow soldering, and the gate control terminal (6) and the sampling terminal (7) are connected with the gate control terminal copper layer (16) and the sampling terminal copper layer (17), respectively, by means of solder bonding or vacuum reflow soldering;

the positive electrode terminal (2) and the negative electrode terminal (3) are respectively connected with the first chip module copper layer and the negative electrode terminal copper layer (14) through a solder bonding or vacuum reflow soldering mode.

7. A high power switch module according to claim 4, characterized in that a gate control terminal copper layer (16) and a sampling terminal copper layer (17) on each of said chip module copper layers are located on the side of said second copper-clad layer (13), and that gate control terminals (6) and sampling terminals (7) on a plurality of said chip module copper layers are arranged in a paddle-type arrangement.

8. The high-power switch module according to claim 4, wherein the gate control terminal (6) and the sampling terminal (7) are elongated, the positive electrode terminal (2) and the negative electrode terminal (3) are sheet-shaped, and the arrangement of the positive electrode terminal (2), the negative electrode terminal (3) and the plurality of chip modules is planar U-shaped.

9. A high power switch module according to claim 2, characterized in that the ceramic layer (11), the first copper-clad layer (12) and the second copper-clad layer (13) are connected by hot pressing, soldering or low temperature sintering by a planar ceramic substrate process.

10. A high power switch module according to any of claims 2-9, characterized in that the second copper-clad layer (13) is provided with an encapsulation body, which encapsulates the positive terminal (2), the negative terminal (3), the plurality of chip modules, the plurality of chip module copper layers and the negative terminal copper layer (14).