CN220106547U

CN220106547U - Semiconductor structure

Info

Publication number: CN220106547U
Application number: CN202321434293.5U
Authority: CN
Inventors: 李浩南; 魏进; 张永杰; 周永昌; 黄晓辉; 董琪琪
Original assignee: Feicheng Semiconductor Shanghai Co ltd
Current assignee: Feicheng Semiconductor Shanghai Co ltd
Priority date: 2023-06-06
Filing date: 2023-06-06
Publication date: 2023-11-28
Anticipated expiration: 2033-06-06

Abstract

The present application provides a semiconductor structure comprising: the semiconductor comprises a semiconductor substrate, wherein an epitaxial layer is formed on the surface of the semiconductor substrate, and the semiconductor substrate comprises a first area and a second area; at least one first ion implantation region in the epitaxial layer, the volume of the at least one first ion implantation region decreasing from the first region toward the second region; a second ion implantation region in the epitaxial layer of the first region, the second ion implantation region partially covering the at least one first ion implantation region; at least one third ion implantation region is located in the epitaxial layer of the second region. The application provides a semiconductor structure, which reduces the volume of at least one first ion implantation region from the first region to the second region, can avoid breakdown of a junction at the outermost periphery of the first region and improves the reliability of a device.

Description

Semiconductor structure

Technical Field

The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure.

Background

Silicon carbide diodes include Schottky Barrier Diodes (SBDs) and junction barrier schottky diodes (JBS). The SBD is formed by combining a single Schottky plane with an N-type epitaxial layer in a unit area; the JBS is coupled to the N-type epitaxial layer in the cell region through schottky interfaces and junctions. The JBS has better reverse leakage performance by junction suppression electric field and better surge current in the PN junction. The MOSFET can also achieve balanced electric fields in the epitaxial layer by means of channel injection through the same design, so that the electrical property of the device is improved. Because the depth of the P-type ion implantation region is deeper, the junction depth gap causes all breakdown to occur at the outermost junction of the device region.

Therefore, it is necessary to provide a more effective and reliable technical solution, to avoid breakdown occurring at the junction at the outermost periphery of the device region, and to improve the device reliability.

Disclosure of Invention

The utility model provides a semiconductor structure, which can avoid breakdown of a junction at the outermost periphery of a first region and improve the reliability of a device.

One aspect of the present utility model provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein an epitaxial layer is formed on the surface of the semiconductor substrate, and the semiconductor substrate comprises a first area and a second area; performing a first ion implantation process to form at least one first ion implantation region in the epitaxial layer, the at least one first ion implantation region decreasing in volume from the first region to the second region; and performing a second ion implantation process, forming a second ion implantation region in the epitaxial layer of the first region, and forming at least one third ion implantation region in the epitaxial layer of the second region, wherein the second ion implantation region partially covers the at least one first ion implantation region.

In some embodiments of the present utility model, the at least one first ion implantation region includes a first doped region partially covered by the second ion implantation region, a longitudinal cross-sectional pattern of the first doped region is a right triangle, and a depth of the first doped region gradually decreases from the first region toward the second region.

In some embodiments of the present application, the at least one first ion implantation region includes a first doped region partially covered by the second ion implantation region and a second doped region partially covered by the third ion implantation region, the first doped region has a rectangular longitudinal cross-sectional shape, the second doped region has a right triangle longitudinal cross-sectional shape, the depth of the second doped region gradually decreases from the first region toward the second region, and the maximum depth of the second doped region is the same as the depth of the first doped region.

In some embodiments of the present application, the at least one first ion implantation region includes a first doping region and a plurality of second doping regions, the first doping region is partially covered by the second ion implantation region, the plurality of second doping regions is partially covered by the plurality of third ion implantation regions, the number of the plurality of second doping regions is the same as the number of the plurality of third ion implantation regions, the first doping region and the plurality of second doping regions have rectangular longitudinal section patterns, and the plurality of second doping regions have the same width and are smaller than the width of the first doping region.

In some embodiments of the present application, the at least one first ion implantation region includes a first doping region and a plurality of second doping regions, the first doping region is partially covered by the second ion implantation region, the plurality of second doping regions is partially covered by the plurality of third ion implantation regions, the number of the plurality of second doping regions is the same as the number of the plurality of third ion implantation regions, the longitudinal section patterns of the first doping region and the plurality of second doping regions are rectangular, and the widths of the plurality of second doping regions and the first doping region gradually decrease from the first region to the second region.

In some embodiments of the present application, the at least one first ion implantation region includes a plurality of first doped regions partially covered by the second ion implantation region, a longitudinal cross-sectional pattern of the plurality of first doped regions is rectangular, and a depth of the plurality of first doped regions gradually decreases from the first region toward the second region.

In some embodiments of the present application, the at least one first ion implantation region includes a plurality of first doping regions and a plurality of second doping regions, the plurality of first doping regions are partially covered by the second ion implantation region, the plurality of second doping regions are partially covered by the plurality of third ion implantation regions, the number of the plurality of second doping regions is the same as the number of the plurality of third ion implantation regions, the longitudinal section patterns of the plurality of first doping regions and the plurality of second doping regions are rectangular, the depth of the plurality of first doping regions gradually decreases from the first region to the second region, and the depth of the plurality of second doping regions is the same and equal to the minimum depth of the plurality of first doping regions.

In some embodiments of the present application, the method for forming a semiconductor structure further includes: forming a second epitaxial layer on the surface of the epitaxial layer; etching the second epitaxial layer to form a plurality of grooves, wherein the second ion implantation region and the third ion implantation region are exposed by the grooves; forming a field oxide layer connected with the third ion implantation region in the groove of the second region and on the surface of the second epitaxial layer; and forming a source metal layer electrically connected with the second ion implantation region in the groove of the first region and on the surface of the second epitaxial layer.

In some embodiments of the application, the second ion implantation region also extends into the second region.

Another aspect of the present application also provides a semiconductor structure, comprising: the semiconductor comprises a semiconductor substrate, wherein an epitaxial layer is formed on the surface of the semiconductor substrate, and the semiconductor substrate comprises a first area and a second area; at least one first ion implantation region in the epitaxial layer, the volume of the at least one first ion implantation region decreasing from the first region toward the second region; a second ion implantation region in the epitaxial layer of the first region, the second ion implantation region partially covering the at least one first ion implantation region; at least one third ion implantation region is located in the epitaxial layer of the second region.

In some embodiments of the present application, the at least one first ion implantation region includes a first doped region partially covered by the second ion implantation region, a longitudinal cross-sectional pattern of the first doped region is a right triangle, and a depth of the first doped region gradually decreases from the first region toward the second region.

In some embodiments of the present utility model, the semiconductor structure further comprises: the second epitaxial layer is positioned on the surface of the epitaxial layer; the field oxide layer is positioned on the surface of the second epitaxial layer, penetrates through the second epitaxial layer and is connected with the third ion implantation region; and the source electrode metal layer is positioned on the surface of the second epitaxial layer, penetrates through the second epitaxial layer and is electrically connected with the second ion implantation region.

In some embodiments of the utility model, the field oxide layer also covers a portion of the second ion implantation region.

In some embodiments of the utility model, the second ion implantation region also extends into the second region.

The utility model provides a semiconductor structure, which designs a transition structure with the volume of a first ion implantation region gradually reduced from a first region to a second region, so that the volume of at least one first ion implantation region is reduced from the first region to the second region, the electric field of the first region can be gradually reduced to the second region, the junction at the outermost periphery of the first region can be prevented from being broken down, and the reliability of a device is improved.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present utility model. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description only and are not intended to limit the scope of the utility model, as other embodiments may equally well accomplish the inventive intent in this disclosure. It should be understood that the drawings are not to scale. Wherein:

FIG. 1 is a schematic diagram of some semiconductor structures;

fig. 2 to 5 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a semiconductor structure according to some embodiments of the present application;

fig. 7 is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present application;

FIG. 8 is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present application;

fig. 9 is a schematic structural diagram of a semiconductor structure according to some embodiments of the present application;

fig. 10 is a schematic structural diagram of a semiconductor structure according to some embodiments of the present application.

Detailed Description

The following description provides specific applications and requirements of the application to enable any person skilled in the art to make and use the application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The technical scheme of the utility model is described in detail below with reference to the examples and the accompanying drawings.

Fig. 1 is a schematic structural diagram of some semiconductor structures.

Referring to fig. 1, the semiconductor structure includes: the semiconductor substrate 100, an epitaxial layer 110 is formed on the surface of the semiconductor substrate 100, and the semiconductor substrate 100 includes a first region 101 and a second region 102.

With continued reference to fig. 1, the epitaxial layer 110 of the first region 101 includes a first ion implantation region 120, and the first ion implantation region 120 includes a second ion implantation region 130 and a current diffusion layer 140.

With continued reference to fig. 1, a field oxide layer 150 is formed on the surface of the epitaxial layer 110 in the second region 102, and a source metal layer 160 is formed on the surface of the epitaxial layer 110 in the first region 101, where the source metal layer 160 further extends to a portion of the surface of the field oxide layer 150.

The first ion implantation region 120 is used to balance the electric field in the epitaxial layer 110. However, the first ion implantation region 120 has a larger volume and a deeper depth and is only located in the first region 101, and the junction depth difference between the first region 101 and the second region 102 may make all the breakdown easily occur at the junction (shown by the dashed box 170 in fig. 1) at the outermost periphery of the first region 101, thereby reducing the device reliability.

Based on the above problems, the present application provides a semiconductor structure, which designs a transition structure in which the volume of a first ion implantation region gradually decreases from a first region to a second region, so that the volume of at least one first ion implantation region decreases from the first region to the second region, the electric field of the first region can gradually decrease toward the second region, a junction at the outermost periphery of the first region can be avoided from breakdown, and the reliability of the device is improved.

Fig. 2 to 5 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the application. The method for forming the semiconductor structure according to the embodiments of the present application is described in detail below with reference to the accompanying drawings.

Referring to fig. 2, a semiconductor substrate 200 is provided, an epitaxial layer 210 is formed on a surface of the semiconductor substrate 200, and the semiconductor substrate 200 includes a first region 201 and a second region 202.

In some embodiments of the present application, the material of the semiconductor substrate 200 includes a semiconductor material such as silicon carbide or silicon. The semiconductor substrate 200 may have N-type doping.

In some embodiments of the present application, the first region 201 is a core device region (or cell region) for forming a core silicon carbide power device, such as a MOSFET and a diode device. The second region 202 is an edge region, and is located at the edge of the first region 201 and surrounds the first region 201.

In the embodiment of the present application, the partial area (the area indicated by the dashed box 203 in fig. 2) adjacent to the first area 201 and the second area 202 is referred to as a transition area from the first area 201 to the second area 202, which is hereinafter referred to as a transition area 203. Since the technical solution of the present application is mainly located in the transition region 203, only the structure of the transition region 203 is shown later, but a person skilled in the art should be able to eliminate the structure in the first region 201 and the second region 202 outside the transition region 203 in connection with the semiconductor structure shown in fig. 1.

In some embodiments of the present application, it should be noted that fig. 2 is merely a schematic illustration of the relationship between the first region 210 and the second region 202, and is not an actual structure. In practice, the semiconductor substrate 200 may include a plurality of first regions 201 distributed in an array, and the second regions 202 are located at the periphery of the plurality of first regions 201 and surround the plurality of first regions 201. Whereas the transition regions 203 of interest for the present application are those partial regions between the first region 201 and the second region 202 that are located at the outermost periphery adjacent to the second region 202.

In some embodiments of the present application, the material of the epitaxial layer 210 is the same as the material of the semiconductor substrate 200, such as silicon carbide or silicon.

In some embodiments of the present application, the epitaxial layer 210 may have N-type doping. The doping concentration of the epitaxial layer 210 is 1E15atom/cm ³ To 1E17atom/cm ³ 。

In some embodiments of the application, the epitaxial layer 210 has a thickness of 5 to 33 microns.

Referring to fig. 3, fig. 3 is an enlarged view of the transition region 203 of fig. 2. A first ion implantation process is performed to form at least one first ion implantation region 220 in the epitaxial layer 210, the volume of the at least one first ion implantation region 220 decreasing from the first region 201 toward the second region 202.

In some embodiments of the present application, referring to fig. 3, the number of the at least one first ion implantation regions 220 is plural, the at least one first ion implantation region 220 includes a first doping region 221 and a plurality of second doping regions 222, the longitudinal cross-sectional patterns of the first doping region 221 and the plurality of second doping regions 222 are rectangular, the plurality of second doping regions 222 have the same width and are smaller than the width of the first doping region 221 (this is the case shown in fig. 3 of the embodiment of the present application), or the plurality of second doping regions 222 and the width of the first doping region 221 gradually decrease from the first region 201 toward the second region 202 (other embodiments). Wherein the first doped region 221 is located in the first region 201, and the second doped regions 222 are located in the second region 202. Or the first doped region 221 spans the first region 201 and the second region 202, and the plurality of second doped regions 222 are located in the second region 202.

In the embodiment shown in fig. 3, the first doped region 221 and the plurality of second doped regions 222 have a rectangular parallelepiped shape, and the volumes of the first doped region 221 and the plurality of second doped regions 222 decrease from the first region 201 to the second region 202. The lengths of the first doped region 221 and the plurality of second doped regions 222 are the dimension perpendicular to the paper surface, the widths of the first doped region 221 and the plurality of second doped regions 222 are the dimension in the horizontal direction in the drawing, and the heights of the first doped region 221 and the plurality of second doped regions 222 are the dimension in the vertical direction in the drawing. In the embodiment shown in fig. 3, the height and length of the first doped region 221 and the plurality of second doped regions 222 are kept unchanged, and the volume is reduced by reducing the width.

In some embodiments of the present application, the method of forming the first doped region 221 and the plurality of second doped regions 222 includes: forming a patterned photoresist layer on the surface of the epitaxial layer 210, wherein the patterned photoresist layer defines the positions of the first doped region 221 and the plurality of second doped regions 222; forming the first doped region 221 and the plurality of second doped regions 222 in the epitaxial layer 210 by using the patterned photoresist layer as a mask and adopting a first ion implantation process; and removing the patterned photoresist layer.

In some embodiments of the present application, the first ion implantation process has an implantation energy of 10 to 5MKEV and an implantation concentration of 1E15atom/cm ³ To 1E18atom/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the The implantation depth is 0.4 to 33 microns; the implantation width is 0.6 to 10 microns; the implantation type is P-type.

In some embodiments of the present application, the doping type of the first doped region 221 is P-type; doping concentration of 1E15atom/cm ³ To 1E18atom/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the A depth of 0.4 to 33 microns; the width is 1 to 10 microns, for example 1.5 microns.

In some embodiments of the present application, the doping type of the second doped region 222 is P-type; doping concentration of 1E15atom/cm ³ To 1E18atom/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the A depth of 0.4 to 33 microns; the width is 0.5 to 9.5 microns, for example 1 micron. The spacing between the second doped regions 222 is the same, for example, 0.6 to 30 microns.

In the embodiment shown in fig. 3, the heights (or depths) of the first doped region 221 and the second doped regions 222 are the same, and only the widths are different, so that the first ion implantation process can be relatively simple, and only the positions of the first doped region 221 and the second doped regions 222 need to be defined by controlling the patterned photoresist layer.

In the technical scheme of the application, a transition structure in which the volume of the first ion implantation region 220 gradually decreases from the first region 201 to the second region 201 is designed, so that the volume of the at least one first ion implantation region 220 decreases from the first region 201 to the second region 202, the electric field of the first region 201 can gradually decrease to the second region 202, the junction at the outermost periphery of the first region 201 can be avoided from breakdown, and the device reliability is improved.

Referring to fig. 4, a second ion implantation process is performed, a second ion implantation region 230 is formed in the epitaxial layer 210 of the first region 201, and at least one third ion implantation region 240 is formed in the epitaxial layer 210 of the second region 202, the second ion implantation region 230 partially covering the at least one first ion implantation region 220. The second ion implantation region 230 and the third ion implantation region 240 have a width slightly greater than the width of the at least one first ion implantation region 220. The sidewalls of the second ion implantation region 230 and the third ion implantation region 240 may extend beyond the sidewalls of the at least one first ion implantation region 220 (shown in the embodiments of the present application) or may be located in the at least one first ion implantation region 220 away from the sidewalls of the second region 202 (in other embodiments).

Specifically, the first doped region 221 is partially covered by the second ion implantation region 230, the plurality of second doped regions 222 is partially covered by the plurality of third ion implantation regions 240, and the number of the plurality of second doped regions 222 is the same as the number of the plurality of third ion implantation regions 240. The second ion implantation region 230 is a contact layer between the first doped region 221 and the source metal layer, and the third ion implantation region 240 is a junction termination extension (Junction terminal extension, JTE).

In some embodiments of the present application, the method of forming the second ion implantation region 230 and the plurality of third ion implantation regions 240 includes: forming a patterned photoresist layer on the surface of the epitaxial layer 210, wherein the patterned photoresist layer defines the positions of the second ion implantation regions 230 and the third ion implantation regions 240; forming the second ion implantation region 230 and the plurality of third ion implantation regions 240 in the epitaxial layer 210 by using the patterned photoresist layer as a mask and adopting a second ion implantation process; and removing the patterned photoresist layer.

In some embodiments of the present application, the second ion implantation process has an implantation energy of 10 to 5MKEV and an implantation concentration of 1E17 atoms/cm ³ To 1E21atom/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the The implantation depth is 0.2 to 1.5 microns; the implantation width is 1.2 to 100 micrometers; the implantation type is P-type.

In some embodiments of the present application, the doping type of the second ion implantation region 230 is P-type; doping concentration of 1E17atom/cm ³ To 1E21atom/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the A depth of 0.2 to 1.5 microns; the width is 1.2 to 100 micrometers.

In some embodiments of the present application, the doping type of the third ion implantation region 240 is P-type; doping concentration of 1E17atom/cm ³ To 1E21atom/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the A depth of 0.2 to 1.5 microns; the width is 1.2 to 100 micrometers. The third ion implantation regions 240 have the same pitch, for example, 0.6 to 30 μm.

In some embodiments of the present application, the second ion implantation region 230 also extends into the second region 202.

In some embodiments of the present application, the method for forming a semiconductor structure further includes: a current diffusion layer (not shown in the figure) is formed in the first region 201. The doping type of the current diffusion layer is N type; doping concentration of 1E15atom/cm ³ To 1E18atom/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the The depth is 0.4 to 6 microns. From the following componentsIn the solution of the present application, the structures in the first region 201 and the second region 202 except the transition region 203 are omitted mainly in the transition region 203.

Referring to fig. 5, a field oxide layer 250 is formed on the surface of the epitaxial layer 210 of the second region 202 and connected to the third ion implantation region 240; and forming a source metal layer 260 electrically connected to the second ion implantation region 240 on the surface of the epitaxial layer 210 of the first region 201, wherein the source metal layer 260 further extends to a portion of the surface of the field oxide layer 250.

In some embodiments of the present application, a drain metal layer (not shown) may also be formed on a side of the semiconductor substrate 200 opposite to the side on which the epitaxial layer 210 is formed.

In the technical solution of the present application, in the transition region 203, the volume of the at least one first ion implantation region 220 is reduced from the first region 201 to the second region 202, so that the electric field of the first region 201 can be gradually reduced to the second region 202, and the junction at the outermost periphery of the first region 201 can be avoided from breakdown, thereby improving the reliability of the device.

Note that the transition region 203 is focused on in the technical solution of the present application, so any suitable semiconductor device, such as a silicon carbide planar MOSFET or a silicon carbide device with a trench gate structure, etc., may be formed in the first region 201.

The first ion implantation region 220, the second ion implantation region 230, and the third ion implantation region 240 of the transition region 203 may be formed simultaneously with the corresponding ion implantation regions at other positions of the first region 201 and the second region 202, respectively.

The second ion implantation region 230 with a higher doping concentration may cause lattice damage. The technical scheme of the application adopts the first ion implantation region 220 with lower doping concentration to push the electric field to a deeper place with less lattice damage, thereby improving the reliability and the electrical property of the device.

In the technical solution of the present application, the first ion implantation region 220 with a deeper depth can balance the electric field distribution in the epitaxial layer 210, thereby improving the breakdown voltage of the device.

In the technical solution of the present application, the contact surface between the deep first ion implantation region 220 and the epitaxial layer 210 increases and the distance between the first ion implantation region and the semiconductor substrate 200 decreases, so that the surge current can be increased.

Fig. 6 is a schematic structural diagram of a semiconductor structure according to some embodiments of the present application.

Referring to fig. 6, in some embodiments of the present application, the method for forming a semiconductor structure further includes: forming a second epitaxial layer 270 on the surface of the epitaxial layer 210; etching the second epitaxial layer 270 to form a plurality of trenches exposing the second ion implantation region 230 and the third ion implantation region 240; forming a field oxide layer 250 connecting the third ion implantation region 240 in the trench of the second region 202 and on the surface of the second epitaxial layer 270; a source metal layer 260 electrically connected to the second ion implantation region 230 is formed in the trench of the first region 201 and on the surface of the second epitaxial layer 270.

It should be noted that the semiconductor structure shown in fig. 6 is different from the semiconductor structure shown in fig. 5 only in that a second epitaxial layer 270 is added, and the corresponding field oxide layer 250 and source metal layer 260 need to penetrate through the second epitaxial layer 270 to connect the second ion implantation region 230 and the third ion implantation region 240. Other structures are the same, and therefore other similar partial structures are not described herein.

In some embodiments of the present application, the source metal layer 260 and the field oxide layer 250 also connect the first ion implantation region when a portion of the sidewall of the first ion implantation region 220 exceeds the sidewalls of the second ion implantation region 230 and the third ion implantation region 240.

In some embodiments of the present application, the second epitaxial layer 270 is the same material as the first epitaxial layer 210. The second epitaxial layer 270 has a thickness of 0.1 to 23 microns. The width of the grooves is 0.5 to 23 micrometers.

In the technical solution of the present application, the second epitaxial layer 270 may be designed with a core device region, and the depletion region of the second ion implantation region 230 can pinch off the electric field in the second epitaxial layer 270, so that the electric field between 270 and 230 achieves a charge balance effect, and the concentration of the second epitaxial layer 270 can be adjusted to increase the current density and reliability of the device.

The above is an embodiment of changing the volumes of the different first ion implantation regions by changing the widths of the different first ion implantation regions. Other embodiments of the application are as follows. It should be noted that, in some other embodiments below, only the structure of the first ion implantation region is changed, and the forming process is the same as the forming method shown in fig. 2 to 5, so the forming method will not be described in detail in some other embodiments below.

Fig. 7 is a schematic structural diagram of a semiconductor structure according to some embodiments of the present application.

Referring to fig. 7, in some embodiments of the present application, the at least one first ion implantation region 220 includes a first doped region 221, the first doped region 221 is partially covered by the second ion implantation region 230, a longitudinal cross-sectional pattern of the first doped region 221 is a right triangle, and a depth of the first doped region 221 gradually decreases from the first region 201 toward the second region 202.

In some embodiments of the present application, the method of forming the first doped region 221 includes: forming an ion implantation mask layer on the surface of the epitaxial layer 210, wherein the position of the ion implantation mask layer corresponds to the position of the first doped region 221, and the thickness of the ion implantation mask layer increases from the first region 201 to the second region 202; performing the first ion implantation process through the ion implantation mask layer to form the first doped region 221; and removing the ion implantation mask layer. The ion implantation mask layer may play a role in blocking, and reduce the implantation depth of the first doped region 221, and the thickness of the ion implantation mask layer increases from the first region 201 to the second region 202, so that the depth of the corresponding first doped region 221 gradually decreases from the first region 201 to the second region 202. Similarly, in other embodiments, the depth of the first ion implantation region 220 at different positions is also different, which will not be described in detail later.

It should be noted that the semiconductor structure shown in fig. 7 is different from the semiconductor structure shown in fig. 5 only in the structure of the first ion implantation region 220. Other structures are the same, and therefore other similar partial structures are not described herein.

Fig. 8 is a schematic structural diagram of a semiconductor structure according to some embodiments of the present application.

Referring to fig. 8, in some embodiments of the present application, the at least one first ion implantation region 220 includes a first doping region 221 and a second doping region 222, the first doping region 221 is partially covered by the second ion implantation region 230, the second doping region 222 is partially covered by the third ion implantation region 240, the first doping region 221 has a rectangular longitudinal cross-sectional shape, the second doping region 222 has a right triangle longitudinal cross-sectional shape, the second doping region 222 has a depth gradually decreasing from the first region 201 toward the second region 202 and the second doping region 222 has a maximum depth identical to the first doping region 221.

In some embodiments of the present application, the first doped region 221 and the second doped region 222 may be formed simultaneously or may be formed separately.

It should be noted that the semiconductor structure shown in fig. 8 is different from the semiconductor structure shown in fig. 5 only in the structure of the first ion implantation region 220. Other structures are the same, and therefore other similar partial structures are not described herein.

Fig. 9 is a schematic structural diagram of a semiconductor structure according to some embodiments of the present application.

Referring to fig. 9, in some embodiments of the present application, the at least one first ion implantation region 220 includes a plurality of first doped regions 221, the plurality of first doped regions 221 are partially covered by the second ion implantation region 230, a longitudinal cross-sectional pattern of the plurality of first doped regions 221 is rectangular, and a depth of the plurality of first doped regions 221 gradually decreases from the first region 201 toward the second region 202.

Note that the semiconductor structure shown in fig. 9 is different from the semiconductor structure shown in fig. 5 only in the structure of the first ion implantation region 220. Other structures are the same, and therefore other similar partial structures are not described herein.

Referring to fig. 10, in some embodiments of the present application, the at least one first ion implantation region 220 includes a plurality of first doping regions 221 and a plurality of second doping regions 222, the plurality of first doping regions 221 are partially covered by the second ion implantation region 230, the plurality of second doping regions 222 are respectively partially covered by the plurality of third ion implantation regions 240, the number of the plurality of second doping regions 222 is the same as the number of the plurality of third ion implantation regions 240, the longitudinal section patterns of the plurality of first doping regions 221 and the plurality of second doping regions 222 are rectangular, the depth of the plurality of first doping regions 221 gradually decreases from the first region 201 toward the second region 202, and the depth of the plurality of second doping regions 222 is the same and equal to the minimum depth of the plurality of first doping regions 221.

In some embodiments of the present application, the first doped regions 221 and the second doped regions 222 may be formed simultaneously or may be formed separately.

Note that the semiconductor structure shown in fig. 10 is different from the semiconductor structure shown in fig. 5 only in the structure of the first ion implantation region 220. Other structures are the same, and therefore other similar partial structures are not described herein.

The application provides a method for forming a semiconductor structure, which designs a transition structure with the volume of a first ion implantation region gradually reduced from a first region to a second region, so that the volume of at least one first ion implantation region is reduced from the first region to the second region, the electric field of the first region can be gradually reduced to the second region, the junction at the outermost periphery of a device region can be prevented from breakdown, and the reliability of the device is improved.

Another aspect of the present application also provides a semiconductor structure, as shown with reference to fig. 5, comprising: a semiconductor substrate 200, an epitaxial layer 210 is formed on the surface of the semiconductor substrate 200, and the semiconductor substrate 200 comprises a first region 201 and a second region 202; at least one first ion implantation region 220 located on the epitaxial layer 210, the volume of the at least one first ion implantation region 220 decreasing from the first region 201 toward the second region 202; a second ion implantation region 230 located in the epitaxial layer 210 of the first region 201, the second ion implantation region 230 partially covering the at least one first ion implantation region 220; at least one third ion implantation region 240 is located in the epitaxial layer 210 of the second region 202.

In some embodiments of the present application, the first region 201 is a core device region (or cell region) for forming a core silicon carbide diode device. The second region 202 is an edge region, and is located at the edge of the first region 201 and surrounds the first region 201.

Referring to fig. 2, in the embodiment of the present application, a partial region (a region indicated by a dashed box 203 in fig. 2) adjacent to the first region 201 and the second region 202 is referred to as a transition region from the first region 201 to the second region 202, which is hereinafter referred to as a transition region 203. Since the technical solution of the present application is mainly located in the transition region 203, only the structure of the transition region 203 is shown later, but a person skilled in the art should be able to eliminate the structure in the first region 201 and the second region 202 outside the transition region 203 in connection with the semiconductor structure shown in fig. 1.

In some embodiments of the present application, referring to fig. 5, the number of the at least one first ion implantation regions 220 is plural, the at least one first ion implantation region 220 includes a first doping region 221 and a plurality of second doping regions 222, the longitudinal cross-sectional patterns of the first doping region 221 and the plurality of second doping regions 222 are rectangular, the plurality of second doping regions 222 have the same width and are smaller than the width of the first doping region 221 (this is the case shown in fig. 3 of the embodiment of the present application), or the plurality of second doping regions 222 and the width of the first doping region 221 gradually decrease from the first region 201 toward the second region 202 (other embodiments). Wherein the first doped region 221 is located in the first region 201, and the second doped regions 222 are located in the second region 202. Or the first doped region 221 spans the first region 201 and the second region 202, and the plurality of second doped regions 222 are located in the second region 202.

In the embodiment shown in fig. 5, the first doped region 221 and the plurality of second doped regions 222 have a rectangular parallelepiped shape, and the volumes of the first doped region 221 and the plurality of second doped regions 222 decrease from the first region 201 to the second region 202. The lengths of the first doped region 221 and the plurality of second doped regions 222 are the dimension perpendicular to the paper surface, the widths of the first doped region 221 and the plurality of second doped regions 222 are the dimension in the horizontal direction in the drawing, and the heights of the first doped region 221 and the plurality of second doped regions 222 are the dimension in the vertical direction in the drawing. In the embodiment shown in fig. 3, the height and length of the first doped region 221 and the plurality of second doped regions 222 are kept unchanged, and the volume is reduced by reducing the width.

In the embodiment shown in fig. 5, the heights (or depths) of the first doped region 221 and the second doped regions 222 are the same, and only the widths are different, so that the first ion implantation process can be relatively simple, and only the positions of the first doped region 221 and the second doped regions 222 need to be defined by controlling the patterned photoresist layer.

With continued reference to fig. 5, a second ion implantation region 230 is formed in the epitaxial layer 210 of the first region 201, and at least one third ion implantation region 240 is formed in the epitaxial layer 210 of the second region 202, and the second ion implantation region 230 partially covers the at least one first ion implantation region 220. The second ion implantation region 230 and the third ion implantation region 240 have a width slightly greater than the width of the at least one first ion implantation region 220. The sidewalls of the second ion implantation region 230 and the third ion implantation region 240 may extend beyond the sidewalls of the at least one first ion implantation region 220 (shown in the embodiments of the present application) or may be located in the at least one first ion implantation region 220 away from the sidewalls of the second region 202 (in other embodiments).

Specifically, the first doped region 221 is partially covered by the second ion implantation region 230, the plurality of second doped regions 222 is partially covered by the plurality of third ion implantation regions 240, and the number of the plurality of second doped regions 222 is the same as the number of the plurality of third ion implantation regions 240. The second ion implantation region 230 is a contact layer between the first doped region 221 and the source metal layer, and the third ion implantation region 240 is a JTE.

In some embodiments of the present application, the semiconductor structure further comprises: a current spreading layer (not shown) is located in the first region 201. The doping type of the current diffusion layer is N type; doping concentration of 1E15atom/cm ³ To 1E18atom/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the The depth is 0.4 to 6 microns. Since the technical solution of the present application is mainly in the transition region 203, the structures in the first region 201 and the second region 202 except for the transition region 203 are omitted.

With continued reference to fig. 5, a field oxide layer 250 is formed on the surface of the epitaxial layer 210 in the second region 202 and connected to the third ion implantation region 240; a source metal layer 260 electrically connected to the second ion implantation region 240 is formed on the surface of the epitaxial layer 210 in the first region 201, and the source metal layer 260 further extends to a portion of the surface of the field oxide layer 250.

In some embodiments of the present application, the field oxide layer 250 may also cover a portion of the second ion implantation region 240 extending to the second region 202.

Referring to fig. 6, in some embodiments of the application, the semiconductor structure further comprises: a second epitaxial layer 270 on the surface of the epitaxial layer 210; a field oxide layer 250 located on the surface of the second epitaxial layer 270, penetrating the second epitaxial layer 270 and connecting the third ion implantation region 240; the source metal layer 260 is located on the surface of the second epitaxial layer 270, penetrates through the second epitaxial layer 270 and is electrically connected to the second ion implantation region 230.

In some embodiments of the present application, the second epitaxial layer 270 is the same material as the first epitaxial layer 210. The second epitaxial layer 270 has a thickness of 0.1 to 23 microns.

The above is an embodiment of changing the volumes of the different first ion implantation regions by changing the widths of the different first ion implantation regions. Other embodiments of the application are as follows. It should be noted that, in the following other embodiments, only the structure of the first ion implantation region is changed, and thus, in the following other embodiments, other structures other than the first ion implantation region are not described in detail.

The application provides a semiconductor structure and a forming method thereof, and designs a transition structure with the volume of a first ion implantation region gradually reduced from a first region to a second region, so that the volume of at least one first ion implantation region is reduced from the first region to the second region, the electric field of the first region can be gradually reduced to the second region, the junction at the outermost periphery of a device region can be prevented from breakdown, and the reliability of the device is improved.

In view of the foregoing, it will be evident to those skilled in the art after reading this disclosure that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.

It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.

Furthermore, the present description describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, comprising:

the semiconductor comprises a semiconductor substrate, wherein an epitaxial layer is formed on the surface of the semiconductor substrate, and the semiconductor substrate comprises a first area and a second area;

at least one first ion implantation region in the epitaxial layer, the volume of the at least one first ion implantation region decreasing from the first region toward the second region;

a second ion implantation region in the epitaxial layer of the first region, the second ion implantation region partially covering the at least one first ion implantation region;

At least one third ion implantation region is located in the epitaxial layer of the second region.

2. The semiconductor structure of claim 1, wherein the at least one first ion implantation region comprises a first doped region partially covered by the second ion implantation region, the first doped region having a longitudinal cross-sectional profile of a right triangle, the first doped region having a depth that decreases gradually from the first region toward the second region.

3. The semiconductor structure of claim 1, wherein the at least one first ion implantation region comprises a first doped region and a second doped region, the first doped region is partially covered by the second ion implantation region, the second doped region is partially covered by the third ion implantation region, the first doped region has a rectangular longitudinal cross-sectional pattern, the second doped region has a right triangle longitudinal cross-sectional pattern, the depth of the second doped region decreases gradually from the first region toward the second region and the maximum depth of the second doped region is the same as the depth of the first doped region.

4. The semiconductor structure of claim 1, wherein the at least one first ion implantation region comprises a first doped region and a plurality of second doped regions, the first doped region being partially covered by the second ion implantation region, the plurality of second doped regions being partially covered by the plurality of third ion implantation regions, the number of second doped regions being the same as the number of third ion implantation regions, the first doped region and the plurality of second doped regions having a rectangular longitudinal cross-sectional pattern, the plurality of second doped regions having a width that is the same and less than the width of the first doped region.

5. The semiconductor structure of claim 1, wherein the at least one first ion implantation region comprises a first doped region and a plurality of second doped regions, the first doped region being partially covered by the second ion implantation region, the plurality of second doped regions being partially covered by the plurality of third ion implantation regions, the number of second doped regions being the same as the number of third ion implantation regions, the first doped region and the plurality of second doped regions having a rectangular longitudinal cross-sectional pattern, the plurality of second doped regions and the first doped region decreasing in width from the first region toward the second region.

6. The semiconductor structure of claim 1, wherein the at least one first ion implantation region comprises a plurality of first doped regions partially covered by the second ion implantation region, the plurality of first doped regions having a rectangular longitudinal cross-sectional profile, the plurality of first doped regions having a depth that decreases progressively from the first region toward the second region.

7. The semiconductor structure of claim 1, wherein the at least one first ion implantation region comprises a plurality of first doped regions and a plurality of second doped regions, the plurality of first doped regions being partially covered by the second ion implantation region, the plurality of second doped regions being partially covered by the plurality of third ion implantation regions, the plurality of second doped regions being the same as the plurality of third ion implantation regions, the plurality of first doped regions and the plurality of second doped regions having a rectangular longitudinal cross-sectional profile, the plurality of first doped regions having depths that gradually decrease from the first region toward the second region, the plurality of second doped regions having depths that are the same and equal to a minimum depth of the plurality of first doped regions.

8. The semiconductor structure of claim 1, further comprising:

the second epitaxial layer is positioned on the surface of the epitaxial layer;

the field oxide layer is positioned on the surface of the second epitaxial layer, penetrates through the second epitaxial layer and is connected with the third ion implantation region;

and the source electrode metal layer is positioned on the surface of the second epitaxial layer, penetrates through the second epitaxial layer and is electrically connected with the second ion implantation region.

9. The semiconductor structure of claim 8, wherein the field oxide layer further covers a portion of the second ion implantation region.

10. The semiconductor structure of claim 1, wherein the second ion implantation region further extends into the second region.