CN216980572U

CN216980572U - Semiconductor structure

Info

Publication number: CN216980572U
Application number: CN202123382749.1U
Authority: CN
Inventors: 李浩南; 张永杰; 周永昌; 黄晓辉; 董琪琪
Original assignee: Feicheng Semiconductor Shanghai Co ltd; Alpha Power Solutions Ltd
Current assignee: Feicheng Semiconductor Shanghai Co ltd; Alpha Power Solutions Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2022-07-15
Anticipated expiration: 2031-12-29

Abstract

The present application provides a semiconductor structure, comprising: the device comprises a substrate, a first epitaxial layer and a second epitaxial layer, wherein the substrate comprises the first epitaxial layer, and part of the first epitaxial layer comprises the second epitaxial layer; the well protection layer separately extends from the surface of the first epitaxial layer to the first epitaxial layer and extends to the position below the second epitaxial layer in the width direction; a well contact layer having the same doping type as the well protection layer, extending from the surface of the well protection layer into the well protection layer, and having sidewalls and a bottom surrounded by the well protection layer; and the metal layer is positioned on the surface of the well contact layer and the side wall and the surface of the second epitaxial layer. The semiconductor structure can reduce the surface electric field of the device, increase the forward current and improve the reliability of the device.

Description

Semiconductor structure

Technical Field

The present application relates to the field of semiconductor devices, and more particularly, to a semiconductor structure.

Background

Among high voltage devices, silicon carbide diodes have been widely studied for their superior electrical properties. Silicon carbide diodes include Schottky Barrier Diodes (SBD) and junction barrier schottky diodes (JBS), in which the schottky barrier diode has a problem in that a reverse leakage current is large due to a schottky barrier lowering effect, and the schottky barrier lowering is more serious as a reverse bias voltage increases. The junction barrier Schottky diode can improve the Schottky barrier lowering effect and does not influence the forward performance of the device.

However, the electrical performance of the current junction barrier schottky diode has many defects, such as high surface electric field, small forward current, and the like.

SUMMERY OF THE UTILITY MODEL

The technical problem to be solved by the application is to provide a semiconductor structure, which can reduce the surface electric field of a device, increase the forward current and improve the reliability of the device.

To solve the above technical problem, the present application provides a semiconductor structure, including: the device comprises a substrate, a first epitaxial layer and a second epitaxial layer, wherein the substrate comprises the first epitaxial layer, and part of the first epitaxial layer comprises the second epitaxial layer; the well protection layer separately extends from the surface of the first epitaxial layer to the first epitaxial layer and extends to the position below the second epitaxial layer in the width direction; a well contact layer having the same doping type as the well protection layer, extending from the surface of the well protection layer into the well protection layer, and having sidewalls and a bottom surrounded by the well protection layer; and the metal layer is positioned on the surface of the well contact layer and the side wall and the surface of the second epitaxial layer.

In an embodiment of the present application, the semiconductor structure further includes a current diffusion layer having a doping type different from that of the well protection layers, and the current diffusion layer extends from a surface of the first epitaxial layer between the adjacent well protection layers into the first epitaxial layer.

In the embodiment of the application, the thickness of the current diffusion layer is 0.4-1.4 μm, the width is 2-6 μm, and the doping concentration is 6 x 10¹⁵/cm³～6×10¹⁶/cm³。

In the embodiment of the application, the doping concentration of the well protection layer is 6 multiplied by 10¹⁶/cm³～5×10¹⁷/cm³The doping concentration of the well contact layer is 1 × 10¹⁸/cm³～1×10²⁰/cm³。

In the embodiment of the application, the thickness of the well protection layer on the side wall of the well contact layer is not more than 0.2 μm, the depth of the well protection layer is 0.6 μm to 1.2 μm, and the thickness of the first epitaxial layer between the well protection layer and the substrate is 8 μm to 12 μm.

In the embodiment of the application, the metal layer further extends into the well contact layer, and the thickness of the metal layer in the well contact layer is 0.1-0.3 μm.

In the embodiment of the present application, the thickness of the first epitaxial layer is 8 μm to 12 μm, the thickness of the second epitaxial layer is 0.5 μm to 2 μm, and the doping concentration of the first epitaxial layer and the second epitaxial layer is 6 × 10¹⁵/cm³～1.4×10¹⁶/cm³。

Compared with the prior art, the semiconductor structure of the technical scheme of the application has the following beneficial effects:

through forming first epitaxial layer and second epitaxial layer on the substrate to form the well contact layer in first epitaxial layer, encircle the lateral wall and the bottom of well contact layer through the well protective layer simultaneously, avoided because of the electric leakage phenomenon that the lattice damage that causes when forming the well contact layer leads to, the well protective layer can also push the electric field branch to the place that is darker and the lattice damage is less, thereby improves the reliability and the electrical property of device.

The well protection layers also extend to the lower part of the second epitaxial layer, so that a depletion region can be formed between the well protection layers under the reverse voltage; further, it is adjacent still can include the current diffusion layer between the well protective layer, be favorable to the diffusion of electric current, can be under the surface electric field that does not increase the schottky, reduce the adjacent width of well protective layer to reduce the unit interval and reduce the extrusion of depletion region to the electric current, thereby increase the forward current of schottky and the surge current of well protective layer.

The metal layer is formed on the surface of the trap contact layer and the side wall and the surface of the second epitaxial layer, so that the Schottky surface area is greatly increased, the Schottky surface is provided with larger forward current, the electric field is kept away from the Schottky surface, and the surface electric field of the device can be greatly reduced. The metal layer can also extend into the well contact layer, so that the contact area of the metal layer and the well contact layer is increased, and the internal resistance of the device is further reduced.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:

FIG. 1 is a schematic diagram of a junction barrier Schottky diode;

FIG. 2 is a schematic diagram of another junction barrier Schottky diode;

fig. 3 is a schematic flow chart illustrating a method of forming a semiconductor structure according to an embodiment of the present disclosure;

fig. 4 to 10 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

FIG. 11 is a schematic flow chart illustrating another method of forming a semiconductor structure according to an embodiment of the present disclosure;

fig. 12 to 16 are schematic structural views of steps of another method for forming a semiconductor structure according to an embodiment of the present disclosure;

FIG. 17 is a graph illustrating the results of an epitaxial layer electric field simulation of the semiconductor structure shown in FIGS. 2 and 9;

fig. 18 is a graph of forward current simulation results for the semiconductor structures shown in fig. 2 and 9.

Detailed Description

The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

Referring to fig. 1, a junction barrier schottky diode includes an N-type substrate 1, an N-type epitaxial layer 2 is formed on a surface of the N-type substrate 1, a P-type heavily doped region 3 is formed from the surface of the N-type epitaxial layer 2 toward the inside, a P-type lightly doped region 4 is formed at the bottom of the P-type heavily doped region 3, and a metal layer 5 is deposited on the surface of the N-type epitaxial layer 2, and the junction barrier schottky diode uses only the P-type heavily doped region 3 as a shielding junction. When the working voltage is applied, the contact position between the P-type heavily doped region 3 and the N-type epitaxial layer 2 is seriously damaged, so that the leakage current and instability of the P-type heavily doped region 3 are increased. In addition, because the schottky surface is closer to the bottom of the P-type heavily doped region 3, the depletion region formed by the P-type heavily doped region 3 and the reverse voltage cannot effectively reduce the electric field of the schottky surface, thereby increasing the reverse leakage current of the schottky.

Referring to fig. 2, another junction barrier schottky diode includes an N-type substrate 10, an N-type epitaxial layer 20 formed on a surface of the N-type substrate 10, a metal layer 50 formed on a surface of the N-type epitaxial layer 20, and the metal layer 50 further extending into the N-type epitaxial layer 20. A P-type heavily doped region 30 and a P-type lightly doped region 40 are formed below the metal layer 50. This junction barrier schottky diode uses only the P-type heavily doped region 30 as the shielding junction. When the operating voltage is applied, the lattice damage of the contact between the P-type heavily doped region 30 and the N-type epitaxial layer 20 is severe, thereby increasing the leakage current and instability of the P-type heavily doped region 30. Moreover, if the adjacent width of the P-type heavily doped region 30 adjacent to the metal layer 50 is too narrow, the current flowing between the P-type heavily doped regions 30 is squeezed, so that the forward conducting current is greatly reduced; if the distance between the adjacent P-type heavily doped regions 30 is large, the surface electric field of the metal layer 50 is also increased, so that the reverse leakage current of the schottky is increased, and the balance between the two is difficult.

Based on this, this application technical scheme forms first epitaxial layer and second epitaxial layer on the substrate, and forms the well contact layer in first epitaxial layer to through well protective layer encircleing well contact layer's lateral wall and bottom, avoid making the lattice damage position that causes when forming the contact layer with first epitaxial layer contacts, leads to the device electric leakage under high pressure, the well protective layer can also be with electric field branch pushing comparatively safe position, thereby improves the reliability and the electrical property of device. Simultaneously because the well protective layer still extends to second epitaxial layer below, be favorable to forming the depletion region between the well protective layer when reverse voltage, reduce the electric field and the leakage current of schottky, cooperate the current diffusion layer simultaneously, can be under the surperficial electric field that does not increase the schottky, reduce the adjacent width of well protective layer to reduce the cell interval and reduce the extrusion of well depletion region to the electric current, thereby increase the forward current of schottky and the surge current of well protective layer. And meanwhile, the metal layer is positioned on the surface of the well contact layer and the side wall and the surface of the second epitaxial layer, so that the Schottky surface area is greatly improved, the electric field is far away from the Schottky surface, and the surface electric field is reduced.

Fig. 8 is a schematic structural diagram of the semiconductor structure according to the embodiment of the present application, and only one of the structural units is taken as an example for explanation. The semiconductor structure comprises a substrate 100, wherein a first epitaxial layer 200 is arranged on the substrate 100, and a second epitaxial layer 500 is arranged on part of the first epitaxial layer 200. The substrate 100 may be, for example, an N-type doped silicon carbide substrate. The material of the first epitaxial layer 200 and the second epitaxial layer 500 may include N-type doped silicon carbide, and the doping concentration of the first epitaxial layer 200 and the second epitaxial layer 500 may be 6 × 10¹⁵/cm³～1.4×10¹⁶/cm³. The thickness of the first epitaxial layer 200 may be 8 to 12 μm, and the thickness of the second epitaxial layer is 0.5 to 2 μm.

The semiconductor structure of the embodiment of the present application further includes a well protection layer 300 extending from the surface of the first epitaxial layer 200 into the first epitaxial layer 200. The adjacent well protection layers 300 are not in contact with each other and are separately located in the first epitaxial layer 200. The well protection layer 300 also extends below the second epitaxial layer 500 in the width direction. The well protection layer 300 and the first epitaxial layer 200 have different doping types, for example, P-type doping, and the doping concentration may be 6 × 10¹⁶/cm³～5×10¹⁷/cm³. The width of the well protection layer 300 may be 1 to 4 μm. The depth of the well protection layer 300 may be 0.6 μm to 1.2 μm. The thickness of the first epitaxial layer 200 between the well protection layer 300 and the substrate 100 is 8 μm to 12 μm, that is, the distance between the bottom surface of the well protection layer 300 and the surface of the substrate 100 is 8 μm to 12 μm.

A well contact layer 400 is further included in the well protection layer 300, and the well contact layer 400 extends from the surface of the well protection layer 300 into the well protection layer 300. The doping type of the well contact layer 400 is the same as that of the well protection layer 300, and the doping concentration of the well contact layer 400 is greater than that of the well protection layer 300, so as to reduce contact resistance. For example, the well contact layer 400 is doped P-type, and the doping concentration may be 1 × 10¹⁸/cm³～1×10²⁰/cm³. The sidewalls and the bottom of the well contact layer 400 are surrounded by the well protection layer 300. Wherein the thickness of the well protection layer 300 on the sidewall of the well contact layer 400 is not more than 0.2 μm, and functions to moderate an electric field. The well contact layer 400 may function as an ohmic contact to reduce the internal resistance of the device.

The well contact layer 400 is formed to cause lattice damage, and the location of the lattice damage may cause a leakage phenomenon at a high voltage. However, since the sidewalls and the bottom of the well contact layer 400 are surrounded by the well protection layer 300, the lattice damage site is protected, and the well protection layer 300 can push the electric field deeper and less lattice damage, thereby greatly improving the reliability and electrical property of the device.

The semiconductor structure of the embodiment of the present application further includes a metal layer 600, the metal layer 600 is located on the surface of the well contact layer 400 and the sidewall and the surface of the second epitaxial layer 500, so as to increase the schottky surface area, and simultaneously, the electric field can be kept away from the schottky surface, thereby reducing the surface electric field. Referring to fig. 10, in some embodiments of the present application, the metal layer 600 further extends into the well contact layer 400, so that the contact area between the metal layer 600 and the well contact layer 400 can be increased, and the internal resistance of the device can be further reduced. The thickness of the metal layer 600 extending into the well contact layer 400 may be 0.1 μm to 0.3 μm. The material of the metal layer 600 may include at least one of nickel, titanium, and molybdenum.

In some embodiments of the present application, with reference to fig. 9 and 10, the semiconductor structure further includes a current diffusion layer 700, and the current diffusion layer 700 extends from the surface of the first epitaxial layer 200 between the adjacent well protection layers 300 into the first epitaxial layer 200. The current spreading layer 700 may allow current to be better spread. The thickness of the current spreading layer 700 should not be too large, and the current spreading layer 700 with too large thickness increases the electric field at the bottom of the well protection layer 300, thereby reducing the breakdown voltage of the device. The current diffusion layer 700 of the embodiment of the present application has a thickness of 0.4 μm to 1.4 μm. The current spreading layer 700 and the bottom surface of the well protection layer 300 may or may not be coplanar, and the current spreading layer 700 and the well protection layer 300 may be coplanar with each otherThe sidewalls of the well protection layer 300 abut. The doping types of the current diffusion layer 700 and the well protection layer 300 are different, and the doping concentration of the current diffusion layer 700 also affects the electrical property of the device. The smaller the doping concentration of the current diffusion layer 700 is, the smaller the doping concentration is, the current flowing between the well protection layers 300 is squeezed, but the surface electric field of schottky is favorably reduced; the larger the doping concentration of the current spreading layer 700 is, the more the current flowing between the well protection layers 300 can be increased, but it is not beneficial to reduce the surface electric field of the schottky, and in this case, the width of the current spreading layer 700 can be adjusted to optimize the surface electric field of the schottky and increase the forward current. As an example, the current diffusion layer 700 is doped N-type, and the doping concentration may be 6 × 10¹⁵/cm³～6×10¹⁶/cm³The width of the current spreading layer 700 may be 2 to 6 μm.

The method for forming the semiconductor structure according to the embodiment of the present application is described in detail below with reference to the accompanying drawings.

Referring to fig. 3, a method for forming a semiconductor structure according to an embodiment of the present application includes:

step S100: providing a substrate, wherein the substrate comprises a first epitaxial layer;

step S110: forming a discrete well protection layer extending from the surface of the first epitaxial layer into the first epitaxial layer;

step S120: forming a well contact layer which extends from the surface of the well protection layer into the well protection layer, and the side wall and the bottom of the well contact layer are surrounded by the well protection layer, wherein the doping type of the well contact layer is the same as that of the well protection layer;

step S130: forming a second epitaxial layer on a part of the first epitaxial layer;

step S140: and forming a metal layer on the surface of the well contact layer and the side wall and the surface of the second epitaxial layer.

Referring to fig. 4, a substrate 100 is provided. The substrate 100 may be a doped silicon carbide substrate. As an example, the substrate 100 is an N-type doped substrate. The substrate 100 includes a first epitaxial layer 200 thereon, and the first epitaxial layer 200 may beAn epitaxial layer of silicon carbide grown by an epitaxial process. The doping type of the first epitaxial layer 200 and the substrate 100 are the same, and the doping concentration may be 6 × 10¹⁵/cm³～1.4×10¹⁶/cm³. The thickness of the first epitaxial layer 200 may be 8 μm to 12 μm.

Referring to fig. 5, a well protection layer 300 is formed in the first epitaxial layer 200, and the well protection layer 300 separately extends from the surface of the first epitaxial layer 200 into the first epitaxial layer 200. The depth of the well protection layer 300 may be 0.6 μm to 1.2 μm, and the thickness of the first epitaxial layer 200 between the well protection layer 300 and the substrate 100 is 8 μm to 12 μm. The width of the well protection layer 300 may be 1 to 4 μm. Forming the well protection layer 300 by a second ion implantation process, wherein the second ion implantation process has a different ion implantation type from the doping ion type of the first epitaxial layer 200, such as P-type ion implantation, with an implantation energy of 10keV to 670keV and a doping concentration of 6 × 10¹⁶/cm³～5×10¹⁷/cm³。

Referring to fig. 6, a well contact layer 400 is formed in the well protection layer 300, and the well contact layer 400 extends from the surface of the well protection layer 300 into the well protection layer 300. The well contact layer 400 may be formed by a third ion implantation process with an implantation energy of 10keV to 400keV and a doping concentration of 1 × 10¹⁸/cm³～1×10²⁰/cm³. Since the well contact layer 400 has a high doping concentration and may cause lattice damage during ion implantation, the width and depth of the well contact layer 400 need to be smaller than those of the well protection layer 300, so that the well protection layer 300 may surround the sidewall and bottom of the well contact layer 400, and prevent the lattice damage from contacting the first epitaxial layer 200, which may cause a leakage problem under high voltage. In some embodiments, the thickness of the well protection layer 300 on the sidewall of the well contact layer 400 is not more than 0.2 μm.

Referring to fig. 7, a second epitaxial layer 500 is formed on a portion of the first epitaxial layer 200. Specifically, the second epitaxial layer 500 is positioned on the surfaces of the well protection layer 300 and the first epitaxial layer 200 between the adjacent well contact layers 400. The forming method comprises the following steps: forming a second epitaxial material on the first epitaxial layer 200; portions of the second epitaxial material are etched, stopping on the well contact layer 400, forming a second epitaxial layer 500 and trenches 610. The trench 610 exposes a surface of the well contact layer 400. In some embodiments, the trench 610 may also expose a portion of the surface of the well protection layer 300.

Referring to fig. 8, a metal layer 600 is formed in the trench 610 and on the surface and sidewalls of the second epitaxial layer 500. The metal layer 600 covers the surface of the well contact layer 400 and the sidewalls and surface of the second epitaxial layer 500, which greatly increases the schottky surface area. Meanwhile, the electric field is far away from the Schottky surface, and the size of the surface electric field is further reduced. The process of forming the metal layer 600 may be physical vapor deposition.

Referring to fig. 9, in some embodiments of the present application, before forming the second epitaxial layer 500, a step of forming a current spreading layer 700 is further included. Specifically, after the well contact layer 400 is formed, ion implantation may be performed into the first epitaxial layer 200 between the adjacent well protection layers 300 to form the current diffusion layer 700 extending from the surface of the first epitaxial layer 200 between the adjacent well protection layers 300 into the first epitaxial layer 200. Forming the current diffusion layer 700 by a first ion implantation process with an implantation energy of 10keV to 670keV and a doping concentration of 6 × 10¹⁵/cm³～6×10¹⁶/cm³The type of the doping ions is different from that of the well protection layer 300. As an example, the current spreading layer 700 is N-type doped.

Referring to fig. 10, in some embodiments of the present application, when forming the metal layer 600, not only a portion of the second epitaxial material but also a portion of the well contact layer 400 need to be etched, so that the formed trench 610 extends into the well contact layer 400, and further the formed metal layer 600 extends into the well contact layer 400, thereby further reducing the internal resistance of the device.

Referring to fig. 11, an embodiment of the present application further provides another method for forming a semiconductor structure, including:

step S200: providing a substrate;

step S210: forming a first epitaxial layer and a second epitaxial material on the substrate;

step S220: etching part of the second epitaxial material to form a second epitaxial layer and a groove;

step S230: forming a well protection layer in the first epitaxial layer below the trench, wherein the well protection layer extends from the surface of the first epitaxial layer to the first epitaxial layer and also extends to a part of the position below the second epitaxial layer;

step S240: forming a well contact layer which extends from the surface of the well protection layer into the well protection layer, and the side wall and the bottom of the well contact layer are surrounded by the well protection layer, wherein the doping type of the well contact layer is the same as that of the well protection layer;

step S250: a metal layer is formed in the trench and on the sidewalls and surface of the second epitaxial layer.

Referring to fig. 12, a substrate 1000 is provided, which substrate 1000 may be an N-type doped silicon carbide substrate. A first epitaxial layer 2000 and a second epitaxial material 5100 are formed over the substrate 1000. The first epitaxial layer 2000 and the second epitaxial material 5100 may be formed in the same epitaxial process. The first epitaxial layer 2000 and the second epitaxial layer 5100 may be N-type doped silicon carbide materials, and the doping concentration may be 6 × 10¹⁵/cm³～1.4×10¹⁶/cm³. The thickness of the first epitaxial layer 2000 may be 8 to 12 μm, and the thickness of the second epitaxial material 5100 is 0.5 to 2 μm.

Referring to fig. 13, a portion of the second epitaxial material 5100 is etched to form a second epitaxial layer 5000 and a trench 6100. A mask (not shown) is then formed on the surface of the second epitaxial layer 5000 to prevent the surface of the second epitaxial layer 5000 from being damaged by a subsequent ion implantation process. A well protection layer 3000 is formed in the first epitaxial layer 2000 under the trench 6100 by using an oblique ion implantation process, and the well protection layer 3000 extends from the surface of the first epitaxial layer 2000 into the first epitaxial layer 2000 and also extends to a portion below the second epitaxial layer 5000. The parameters of the tilted ion implantation process, such as the doping type, the doping concentration, and the ion implantation energy, may refer to the parameters when the well protection layer 3000 is formed by the aforementioned method.

Referring to fig. 14, ion implantation is performed into the well protection layer 3000 to form a well contact layer 4000. The well contact layer 4000 extends from the surface of the well protection layer 3000 into the well protection layer 3000, and the sidewall and the bottom of the well contact layer 4000 are surrounded by the well protection layer 3000. The well contact layer 4000 has the same doping type as the well protection layer 3000. The parameters of doping type, doping concentration, ion implantation energy, etc. when the well contact layer 4000 is formed by ion implantation may refer to the parameters when the well contact layer 4000 is formed by the aforementioned method. Referring to fig. 15, a metal layer 6000 is formed in the trench 6100 and the sidewalls and surface of the second epitaxial layer 5000. Referring to fig. 16, the trench 6100 may also extend into the well contact layer 4000 such that the metal layer 6000 also extends into the well contact layer 4000 to further reduce internal resistance.

At a leakage voltage of 1200V, an electric field simulation test is performed on the semiconductor structures shown in fig. 2 and fig. 9 of the embodiment of the present application, respectively, to obtain an epitaxial layer electric field simulation result shown in fig. 17, where a curve labeled as an embodiment is the electric field simulation result of the embodiment of the present application, and a curve labeled as a comparative example is the electric field simulation result of the semiconductor structure shown in fig. 2. As can be seen from fig. 17, the surface electric field of the semiconductor structure of the embodiment of the present application is only 9.5 × 10⁵V/cm, whereas the surface electric field of the semiconductor structure of the comparative example is only 1.55X 10⁶V/cm, therefore, the semiconductor structure of the embodiment can greatly reduce the surface electric field.

Fig. 18 shows the forward current simulation results for the semiconductor structures shown in fig. 2 and 9 at a leakage voltage of 1200V. According to the current simulation results, it is known that the current is in the range of 3.2 × 10-⁶The semiconductor structure of the embodiment of the present application can achieve a target current density of A/5 μm with only 1.41V, while the semiconductor structure of the comparative example requires 1.49V, so the semiconductor structure of the embodiment of the present application has a larger forward current, which is larger than that of the conventional semiconductor structureThe current spreading layer and the schottky surface area of the semiconductor structure of the embodiments of the present application are increased.

In summary, after reading the present disclosure, those skilled in the art will appreciate that the foregoing may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.

It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will also be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.

Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, comprising:

the device comprises a substrate, a first epitaxial layer and a second epitaxial layer, wherein the substrate comprises the first epitaxial layer, and part of the first epitaxial layer comprises the second epitaxial layer;

the well protection layer extends from the surface of the first epitaxial layer to the first epitaxial layer in a separated mode and extends to the position below the second epitaxial layer in the width direction;

a well contact layer having the same doping type as the well protection layer, extending from the surface of the well protection layer into the well protection layer, and having sidewalls and a bottom surrounded by the well protection layer;

and the metal layer is positioned on the surface of the well contact layer and the side wall and the surface of the second epitaxial layer.

2. The semiconductor structure of claim 1, further comprising a current diffusion layer of a different doping type than the well protection layers, and extending into the first epitaxial layer from a first epitaxial layer surface between adjacent well protection layers.

3. The semiconductor structure of claim 2, wherein the current spreading layer has a thickness of 0.4 μm to 1.4 μm and a width of 2 μm to 6 μm.

4. The semiconductor structure according to claim 1 or 2, wherein a thickness of the well protection layer on the sidewall of the well contact layer is not more than 0.2 μm, a depth of the well protection layer is 0.6 μm to 1.2 μm, and a thickness of the first epitaxial layer between the well protection layer and the substrate is 8 μm to 12 μm.

5. The semiconductor structure of claim 1 or 2, wherein the metal layer further extends into the well contact layer, and the thickness of the metal layer in the well contact layer is 0.1 μm to 0.3 μm.

6. The semiconductor structure of claim 1 or 2, wherein the first epitaxial layer has a thickness of 8 μm to 12 μm and the second epitaxial layer has a thickness of 0.5 μm to 2 μm.