CN219891658U - Hybrid communication board card - Google Patents

Abstract

The utility model relates to a hybrid communication board card, comprising: a PXIe bus, a board main body; the board card main body is provided with an FPGA main control chip, a bus communication module and an external connector; the FPGA main control chip is arranged on one side surface of the board main body; the PXIe bus is electrically connected with the FPGA main control chip; the FPGA main control chip is electrically connected with the bus communication module; the bus communication module is electrically connected with the external connector; the external connector is suitable for being electrically connected with external equipment; the bus communication module is provided with more than two bus communication modules which are respectively arranged on two opposite sides of the board card main body. The utility model is suitable for integrating more than two buses on the PXIe module with a single slot, reduces the consumption of the slot resources in the PXIe chassis while realizing common communication of various buses, reduces the cost and meets the development trend of miniaturization and high density of the system.

Description

Hybrid communication board card

Technical Field

The utility model relates to the technical field of communication, in particular to a hybrid communication board card.

Background

The MIL-STD-1553B bus is used as a standard communication bus of an airborne system, can effectively realize data transmission among all subsystems, meets specific communication characteristics, and has strong anti-interference capability. The ARINC429 bus adopts bipolar return-to-zero codes, and uses twisted pair shielded wires to asynchronously transmit data, and has the advantages of simple structure, stable performance and strong anti-interference performance. The RS422 bus has high transmission rate and long transmission distance. Based on the advantages of the three buses, the bus is often applied to industrial communication at the same time.

The existing PXIE board cards based on the 1553B bus, the ARINC429 bus and the RS422 bus are generally three independent PXIE board card modules, namely the PXIE board card based on the 1553B bus, the PXIE board card based on the ARINC429 bus and the PXIE board card based on the RS422 bus are jointly arranged in the same PXIE chassis, and each board card needs to communicate with an embedded controller through respective PXIE interfaces to realize the receiving and sending of data on the corresponding buses. Because each board card needs to occupy more than one slot position resource of the PXIe chassis, the consumption of the slot position resource of the chassis is greatly increased, the structure of the system is complex, and the development trend of miniaturization of the system cannot be met.

How to reduce the consumption of the slot resources in the PXIe chassis is a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

In view of this, the present utility model provides a hybrid communication board card, which is suitable for reducing the consumption of the slot resources in the PXIe chassis.

According to an aspect of the present utility model, there is provided a hybrid communication board, comprising: a PXIe bus, a board main body;

the board card main body is provided with an FPGA main control chip, a bus communication module and an external connector;

the FPGA main control chip is arranged on one side surface of the board main body;

the PXIe bus is electrically connected with the FPGA main control chip; the FPGA main control chip is electrically connected with the bus communication module; the bus communication module is electrically connected with the external connector;

the external connector is suitable for being electrically connected with external equipment;

the bus communication module is provided with more than two bus communication modules which are respectively arranged on two opposite sides of the board card main body.

In one possible implementation, the card body includes a first card and a second card; one side of the first board clamping piece is provided with a second board clamping piece;

more than two bus communication modules are respectively arranged on the first board card and the second board card.

In one possible implementation, the bus communication module is provided with three;

the three bus communication modules are respectively: two-channel MIL-STD-1553B bus communication modules, four-channel RS422 bus communication modules and two-channel ARINC429 bus communication modules.

In one possible implementation, the two-channel MIL-STD-1553B bus communication module is disposed on a first board card.

In one possible implementation manner, the two-channel MIL-STD-1553B bus communication module is provided with a protocol conversion chip and a transformer chip;

the protocol conversion chip is electrically connected with the FPGA main control chip and the transformer chip.

In one possible implementation, the four-way RS422 bus communication module is disposed on the first board card.

In one possible implementation, the four-way RS422 bus communication module is provided with an isolation transceiver;

the FPGA main control chip is electrically connected with the isolation transceiver.

In one possible implementation, a two-channel ARINC429 bus communication module is provided on the second board.

In one possible implementation manner, the bus communication module is provided with an isolation chip and a transceiver chip;

the FPGA main control chip is electrically connected with the isolation chip;

the isolation chip is electrically connected with the transceiver chip.

In one possible implementation, the method further includes: an inter-board connector;

the FPGA main control chip is electrically connected with the isolation chip through the inter-board connector.

The utility model is suitable for integrating more than two buses on the PXIe module with a single slot, reduces the consumption of the slot resources in the PXIe chassis while realizing common communication of various buses, reduces the cost and meets the development trend of miniaturization and high density of the system. For the application scene with high time synchronization precision among buses, the bus coupling can be scheduled on the board main body without the participation of upper computer software, so that the high-precision time synchronization application is realized, the volume and the structure of the system are simpler, and the miniaturization and the high density of the system are further satisfied.

Other features and aspects of the present utility model will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the utility model and together with the description, serve to explain the principles of the utility model.

Fig. 1 shows a hardware schematic of a first board of a hybrid communication board according to an embodiment of the utility model;

fig. 2 shows a hardware schematic of a second board of the hybrid communication board according to an embodiment of the utility model.

Detailed Description

Various exemplary embodiments, features and aspects of the utility model will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

It should be understood, however, that the terms "center," "longitudinal," "transverse," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counter-clockwise," "axial," "radial," "circumferential," and the like indicate or are based on the orientation or positional relationship shown in the drawings, and are merely for convenience of describing the utility model or simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the utility model.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following description in order to provide a better illustration of the utility model. It will be understood by those skilled in the art that the present utility model may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present utility model.

Fig. 1 shows a hardware schematic of a first board of a hybrid communication board according to an embodiment of the utility model; fig. 2 shows a hardware schematic of a second board of the hybrid communication board according to an embodiment of the utility model. As shown in fig. 1 and 2, the hybrid communication board card includes: PXIe bus 200, board body; the board card main body is provided with an FPGA main control chip 100, a bus communication module and an external connector; the FPGA main control chip 100 is arranged on one side surface of the board main body; the PXIe bus 200 is electrically connected with the FPGA main control chip 100; the FPGA main control chip 100 is electrically connected with the bus communication module; the bus communication module is electrically connected with the external connector; the external connector is suitable for being electrically connected with an external communication bus; the bus communication module is provided with more than two bus communication modules which are respectively arranged on two opposite sides of the board card main body.

Here, it should be noted that the present utility model is applicable to integrating more than two buses on a single-slot PXIe module, and reduces the consumption of bit resources in the PXIe chassis while realizing common communication of multiple buses. The FPGA master control chip 100 implements each bus protocol IP core, and completes analysis of the corresponding bus protocol, so as to meet requirements of implementation of more than two buses on FPGA logic resources. The bus communication module is provided with more than two bus communication modules which are respectively arranged on two opposite sides of the board card main body. More than two bus communication modules are integrated on the same board main body together, and further, the board main body is a PXIe board with a 3U single groove. Here, it should be noted that the two or more bus communication modules include: MIL-STD-1553B bus communication module 300, ARINC429 bus communication module 500 and RS422 bus communication module 400. The utility model integrates MIL-STD-1553B bus, ARINC429 bus and RS422 bus on a PXIE board main body of a single slot. The PXIe bus module with the height of 3U in the standard single slot can realize the receiving and transmitting of data on multiple types of buses with high density, so that the occupation of a communication system to bus slot resources and volumes in a hardware PXIe chassis is greatly reduced, more than three original PXIe bus modules are combined into one PXIe bus module, the cost is reduced, and the development trend of miniaturization and high density of the system is met. For the application scene with high time synchronization precision among buses, the bus coupling can be scheduled on a board card without the participation of upper computer software, so that the high-precision time synchronization application is realized, the volume and the structure of the system are simpler, and the development trend of miniaturization and high density of the system can be met.

In one possible implementation, the board body is provided with a PXIe bus interface connector 210, and the PXIe bus 200 accesses the FPGA host chip 100 through the PXIe bus interface connector 210.

In one possible implementation, the card body includes a first card and a second card; one side of the first board clamping piece is provided with a second board clamping piece; the first board card and the second board card are stacked through the inter-board connector. More than two bus communication modules are respectively arranged on the first board card and the second board card.

In one possible implementation, the bus communication module is provided with three. Here, it should be noted that the three bus communication modules are an MIL-STD-1553B bus communication module 300, an RS422 bus communication module 400, and an ARINC429 bus communication module 500, respectively.

In one possible implementation, two external connectors are provided, a first external connector 600 and a second external connector 700, respectively; the first and second external connectors 600 and 700 are disposed on opposite sides of the board main body, respectively. Further, the FPGA main control chip 100 is disposed on the first board; the first pair of external connectors 600 are disposed on the first board; the second external connector 700 is disposed on a second board; the MIL-STD-1553B bus communication module 300 and the RS422 bus communication module 400 are arranged on the first board card; the ARINC429 bus communication module 500 is disposed on the second board.

In one possible implementation, the FPGA main control chip 100 is electrically connected with the MIL-STD-1553B bus communication module 300; the MIL-STD-1553B bus communication module 300 is electrically connected with the first pair of external connectors 600 and accesses external MIL-STD-1553B bus equipment.

In one possible implementation, the MILs-STD-1553B bus communication module 300 is provided with a protocol conversion chip and a transformer chip; the protocol conversion chip is electrically connected with the transformer chip. Here, it should be noted that, because the MIL-STD-1553B bus communication is a differential signal in the form of manchester encoding, there is a problem that the signal level standard is not matched with the FPGA main control chip 100, the protocol conversion chip and the transformer chip are suitable for making the levels of both sides meet the own requirements and can perform normal communication.

In one possible implementation manner, the FPGA master control chip 100 implements each bus protocol IP core to complete the parsing of the corresponding bus protocol, and further, selects a Cyclone V-series FPGA chip of Intel corporation as the core of the FPGA control circuit, and the chip model is 5CGXFC7DF31, so as to meet the requirements of implementing the MILs-STD-1553B bus communication module 300 on FPGA logic resources.

Here, it should be noted that one end of the FPGA master chip 100 is electrically connected to the PXIe bus 200, and the other end of the FPGA master chip 100 is electrically connected to the MIL-STD-1553B bus communication module 300. Further, the PXIe bus 200 is connected to the FPGA master control chip 100 through the PXIe bus interface connector 210, the FPGA master control chip 100 is electrically connected to the protocol conversion chip, the FPGA master control chip 100 completes conversion between the PXIe bus 200 data and the MIL-STD-1553B bus data, the protocol conversion chip is electrically connected to the transformer chip, and the transformer chip is electrically connected to the first external connector 600, so as to realize connection communication with external MIL-STD-1553B bus devices.

Further, the MILs-STD-1553B bus is a two-channel MILs-STD-1553B bus, as shown in fig. 1, each channel of the two-channel MILs-STD-1553B bus is provided with a protocol conversion chip correspondingly connected with the two channels, and each protocol conversion chip is electrically connected with two transformer chips. Namely, two protocol conversion chips are arranged, and four transformer chips are arranged.

Furthermore, the protocol conversion chip adopts an HI-1573 chip; the transformer chip employs PM-DB2725EX.

In one possible implementation, the FPGA master control chip 100 is electrically connected to the RS422 bus communication module 400; the RS422 bus communication module 400 is electrically connected to the first pair of external connectors 600.

In one possible implementation, the RS422 bus communication module 400 is provided with an isolation transceiver; the FPGA master chip 100 is electrically connected to the isolation transceiver. Here, it should be noted that, the isolation transceiver is suitable for signal conversion between the RS422 differential signal and the LVTTL level, and meanwhile, realizes electrical isolation between the terminal level of the FPGA main control chip 100 and the RS422 bus level, so as to improve the anti-interference capability and communication stability of the module.

Here, it should be noted that, the PXIe bus 200 is connected to the FPGA master control chip 100 through the PXIe bus interface connector 210, the FPGA master control chip 100 is electrically connected to the isolation transceiver, the FPGA master control chip 100 completes the conversion between the PXIe bus 200 data and the RS422 bus data, and the isolation transceiver is electrically connected to the first connector 600, so as to realize the connection communication with the external RS422 bus device.

Further, the RS422 bus is a four-channel RS422 bus, as shown in fig. 1, each channel of the four-channel RS422 bus is provided with four isolation transceivers correspondingly connected with the four channels, that is, the four isolation transceivers are all arranged on four connection paths of the FPGA main control chip 100 and the RS422 bus, so that isolation between the four-channel RS422 bus is realized while isolation between the level of the FPGA main control chip 100 and the level of the RS422 bus is realized.

Further, the isolated transceiver employs an isolated RS-422 transceiver ADM2582E chip.

In one possible implementation, the FPGA master chip 100 is electrically connected to the ARINC429 bus communication module 500; the ARINC429 bus communication module 500 is electrically connected to the second pair of external connectors 700.

In one possible implementation, the method further includes: the inter-board connector 120, one end of the inter-board connector 120 is electrically connected with the FPGA main control chip 100, and the other end of the inter-board connector 120 is electrically connected with the ARINC429 bus communication module 500. Because the ARINC429 bus communication module 500 is disposed on the second board, the FPGA main control chip 100 is located on the first board, and therefore, the connection between the FPGA main control chip 100 and the ARINC429 bus communication module 500 needs to be achieved by using the inter-board connector 120 between the first board and the second board.

In one possible implementation, the ARINC429 bus communication module 500 is provided with an isolation chip and a transceiver chip; the FPGA main control chip 100 is electrically connected with the isolation chip through the inter-board connector 120; the isolation chip is electrically connected with the transceiver chip. Here, it should be noted that the isolation chip is suitable for implementing electrical isolation between the LVTTL level of the FPGA master control chip 100 and the TTL level of the ARINC429 bus transceiver chip.

In one possible implementation, the FPGA master control chip 100 is used as a core of the FPGA control circuit to meet the requirements of implementation of the ARINC429 bus communication module 500 on FPGA logic resources. The PXIe bus 200 is connected to the FPGA master control chip 100 through the PXIe bus interface connector 210, the FPGA master control chip 100 is electrically connected to the isolation chip through the inter-board connector 120, the isolation chip is electrically connected to the transceiver chip, and the transceiver chip is electrically connected to the second external connector 700, so as to realize connection communication with external ARINC429 bus devices.

Further, the ARINC429 bus is a two-channel ARINC429 bus, and the ARINC429 bus communication module 500 is provided with two ARINC429 bus communication interface circuits. As shown in fig. 2, each channel of the two-channel ARINC429 bus is provided with two isolation chips, a transmitting chip and a receiving chip correspondingly connected with the two channels, and further, one channel corresponds to the other channel: the output end of the FPGA main control chip 100 is electrically connected with the input end of one of the isolation chips, the output end of the isolation chip is electrically connected with the input end of the transmitting chip, and the transmitting end of the transmitting chip is electrically connected with the second external connector 700; the input end of the receiving chip is electrically connected with the second external connector 700, the output end of the receiving chip is electrically connected with the input end of another isolating chip, and the output end of the isolating chip is electrically connected with the input end of the FPGA main control chip 100. The other channel is connected in the same manner as described above. Namely, the number of the isolation chips is four, the number of the sending chips is two, and the number of the receiving chips is two. Here, it should be noted that, the first board card is connected with the second board card through the inter-board connector 120, each ARINC429 bus realizes the isolation between the power supply of the first board card and the power supply of the ARINC429 bus transceiver chip through the DC/DC isolation power LTM8057I chip, and meanwhile, the isolation chip is used to realize the electrical isolation between the LVTTL level of the FPGA main control chip 100 and the TTL level of the transceiver chip, so as to improve the anti-interference capability and safety of the module.

Furthermore, the four isolation chips are all ADuM7442 chips, the type of the sending chip is HI-8597, and the type of the receiving chip is HI-8450.

In one possible implementation, the first board is disposed at the bottom of the second board, the first board is a bottom plate, and the second board is a top plate.

In one possible implementation, the first pair of external connectors 600 employs a Guizhou space J30JA-74ZKW connector and the second pair of external connectors 700 employs a Guizhou space J30JA-25ZKW connector.

In one possible implementation, the device further includes a storage module 140; the storage module 140 is disposed on the first board and is a DDR3 storage module, where the storage module 140 is electrically connected to the FPGA main control chip 100, and it should be noted that, the DDR3 storage circuit selects an MT41J128M16JT-125 chip as the DDR3 storage chip, and is suitable for receiving and transmitting MILs-STD-1553B bus messages by the buffer module, so as to implement storage of historical communication MILs-STD-1553B bus data.

In one possible implementation, the device further includes a clock module 130, where the clock module 130 is disposed on the first board, the clock module 130 is electrically connected to the FPGA main control chip 100, and the clock module 130 provides a reference clock signal for operation of the FPGA chip 110.

In one possible implementation manner, the device further comprises a FLASH chip 150, wherein the FLASH chip 150 is arranged on the first board card, the FLASH chip 150 adopts an EPCQ256 configuration chip, and the EPCQ256 configuration chip is electrically connected with the FPGA main control chip 100 and is suitable for storing the configuration program of the FPGA main control chip 100.

In one possible implementation manner, the power management module 160 is further included, the power management module 160 is disposed on the first board, the power management module 160 selects an LTM4644 chip, and is suitable for converting the 12V voltage signal provided by the PXIe bus connector 210 into various voltages, and supplying power to each circuit of the first board and the second board, so as to meet the power-on timing requirements of the first board and the second board.

The foregoing description of embodiments of the utility model has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. A hybrid communication board card, comprising: a PXIe bus, a board main body;

the board card main body is provided with an FPGA main control chip, a bus communication module and an external connector;

the FPGA main control chip is arranged on one side surface of the board main body;

the PXIe bus is electrically connected with the FPGA main control chip; the FPGA main control chip is electrically connected with the bus communication module; the bus communication module is electrically connected with the external connector;

the external connector is suitable for being electrically connected with external equipment;

the bus communication module is provided with more than two bus communication modules, and the more than two bus communication modules are respectively arranged on two opposite side surfaces of the board card main body.

2. The hybrid communication board of claim 1, wherein the board body comprises a first board and a second board;

the first board card is closely attached to one surface of the second board card;

more than two bus communication modules are respectively arranged on the first board card and the second board card.

3. The hybrid communication board of claim 2, wherein the bus communication module is provided with three;

the three bus communication modules are respectively: two-channel MIL-STD-1553B bus communication modules, four-channel RS422 bus communication modules and two-channel ARINC429 bus communication modules.

4. The hybrid communication board of claim 3, wherein the two-channel MIL-STD-1553B bus communication module is disposed on the first board.

5. The hybrid communication board of claim 4, wherein the two-channel MIL-STD-1553B bus communication module is provided with a protocol conversion chip and a transformer chip;

the protocol conversion chip is electrically connected with the FPGA main control chip and the transformer chip.

6. The hybrid communication board of claim 3, wherein the four-channel RS422 bus communication module is disposed on the first board.

7. The hybrid communication board of claim 6, wherein the four-channel RS422 bus communication module is provided with an isolation transceiver;

the FPGA main control chip is electrically connected with the isolation transceiver.

8. The hybrid communication board of claim 3, wherein the two-channel ARINC429 bus communication module is disposed on the second board.

9. The hybrid communication board of claim 8, wherein the bus communication module is provided with an isolation chip and a transceiver chip;

the FPGA main control chip is electrically connected with the isolation chip;

the isolation chip is electrically connected with the transceiver chip.

10. The hybrid communication board of claim 9, further comprising: an inter-board connector;

the FPGA main control chip is electrically connected with the isolation chip through the inter-board connector.