CN219658119U

CN219658119U - Multi-serial-port NPU intelligent development board

Info

Publication number: CN219658119U
Application number: CN202320989712.5U
Authority: CN
Inventors: 刘凯
Original assignee: Shenzhen Speed Electronics Co ltd
Current assignee: Shenzhen Speed Electronics Co ltd
Priority date: 2023-04-23
Filing date: 2023-04-23
Publication date: 2023-09-08
Anticipated expiration: 2033-04-23

Abstract

The NPU intelligent development board comprises a main board and an NPU chip arranged on the main board, wherein the NPU intelligent development board only needs to replace a control module after a serial port is newly added, the NPU chip is connected with an SPI interface, the SPI interface is connected with a plurality of serial ports, and the SPI interface can convert data input by the serial ports into SPI data. According to the utility model, the serial port is connected through the SPI interface, the serial port is not required to be directly connected with the NPU chip, the processing load of the NPU chip can be reduced, meanwhile, the SPI interface can directly convert the data of the serial port into the data type which can be accepted by the SPI interface, and the processing intensity of the NPU chip is further reduced. The serial ports are connected through the SPI interface, and the serial ports with corresponding numbers can be added according to the needs of clients. Under the condition that only serial ports are added, the SPI interface can be replaced to realize upgrading, and an NPU chip does not need to be rewritten, so that the replacement cost of the whole main board can be reduced, and meanwhile, the whole main board is convenient to upgrade.

Description

Multi-serial-port NPU intelligent development board

Technical Field

The utility model relates to the field of board cards, in particular to an NPU intelligent development board with a control module only needing to be replaced after a serial port is newly added.

Background

With the advent of artificial intelligence and the advent of big data, it has been increasingly difficult for CPUs and GPUs in previous embedded processors to meet the increasing demands, especially in terms of deep learning. To cope with the increasing demand, NPUs are emerging. To meet the need for artificial intelligence, the RK3568 processor is also increasingly integrated with NPUs, referred to as RKNPUs. RKNPU has evolved over several generations, the first introduction of RKNPU beginning with RK3399pro and RK 1808. Compared with the traditional CPU and GPU, the deep learning operation capability is greatly improved. Next, the second generation NPU is used on RV1109 and RV1126, thereby improving the utilization rate of the NPU. The third generation NPU is applied to RK3566 and RK3568, and a brand new NPU self-grinding architecture is carried. RK3568 is a high-performance and high-stability intelligent development board, adopts a 64-bit processor, integrates a dual-core architecture GPU and a high-performance NPU, can support 8G memory to the maximum extent, supports an android11.0/Linux operating system, and is mainly oriented to industry customization markets such as Internet of things gateways, NVR storage, industrial control panels, industrial detection, industrial control boxes, karaoke, cloud terminals, vehicle-mounted central control and the like. The board card is provided with a display interface such as USB\SATA\PCIE\MIPI\HDMI and the like, and simultaneously supports WiFi and RGMII gigabit networks; possessing a TUNER module; the multi-system network live television is supported, and online TV programs and program recording and program playback are supported; the high-definition multimedia interface module is accessed, so that a picture-in-picture (PIP) function can be realized, and 4KP30 signals can be supported at maximum; the microphone array is provided, so that functions of far-field voice, noise suppression, echo cancellation and the like can be realized; the secondary development of a developer is supported, and the APP can be customized for customers.

The NPU mainboard has the problems that the number of serial ports is limited, so that the number of connectable modules is limited, and the replacement is inconvenient. If a certain module needs to be replaced, all related modules connected to the NPU chip need to be replaced, so that the compatibility of products is reduced, and the working difficulty and cost of replacing the modules are improved.

In addition, the interface compatible mode on the existing NPU mainboard is too single, and the interfaces cannot be mutually communicated, so that the transmission efficiency is affected.

Disclosure of Invention

The utility model aims to provide an NPU intelligent development board with a control module only needing to be replaced after a serial port is newly added.

Specifically, the utility model aims to provide a multi-serial port NPU intelligent development board which comprises a main board and an NPU chip arranged on the main board, wherein the NPU chip is connected with an SPI interface, the SPI interface is connected with a plurality of serial ports, and the SPI interface can convert data input by the serial ports into SPI data.

Another embodiment of the utility model is: the serial ports of SPI interface connection are 2 to 4 in number.

Yet another embodiment of the present utility model is: the SPI interface is a replaceable interface, and the SPI interface is replaced according to the number of the serial ports.

Another embodiment of the utility model is: the main board is also provided with a PCIE interface, the PCIE interface is connected with a plurality of Ethernet ports, and the PCIE interface can convert data input by the Ethernet ports into PCIE data.

Another embodiment of the utility model is: the PCIE interfaces are replaceable interfaces that are replaced according to the increased number of ethernet ports.

According to the utility model, the serial port is connected through the SPI interface, the serial port is not required to be directly connected with the NPU chip, the processing load of the NPU chip can be reduced, meanwhile, the SPI interface can directly convert the data of the serial port into the data type which can be accepted by the SPI interface, and the processing intensity of the NPU chip is further reduced.

The serial ports are connected through the SPI interface, so that the serial ports with corresponding numbers can be added according to the needs of clients, and more choices are provided for the clients. Under the condition that only serial ports are added, the SPI interface can be replaced to realize upgrading, and an NPU chip does not need to be rewritten, so that the replacement cost of the whole main board can be reduced, and meanwhile, the whole main board is convenient to upgrade. The use requirement of a user on connecting more modules with the NPU intelligent development board can be met.

The SPI interface is also provided with an interface which can enable PCIE transmission signals and Ethernet port transmission signals to be compatible with each other, and the data transmission mode is expanded by converting different protocol interfaces. The PCIE and the Ethernet port are communicated, so that a data transmission mode can be increased, and the function of the Ethernet port is improved.

Drawings

FIG. 1 is a schematic diagram of an SPI interface connection of the present utility model;

the reference numerals in the figures illustrate: 1. a main board; NPU chip; SPI interface; 4. a serial port; PCIE interface; 6. an Ethernet port.

Detailed Description

The present solution is further described below in conjunction with the accompanying drawings for ease of understanding by those skilled in the art.

Referring to fig. 1, the present embodiment provides an intelligent multi-serial NPU development board, which includes a motherboard 1, an NPU chip 2 mounted on the motherboard 1, an SPI interface 3 disposed on the motherboard 1, a serial port 4 connected to the SPI interface 3, a PCIE interface 5 disposed on the motherboard, and a serial port 6 connected to the PCIE interface 5.

The NPU chip 2 is used as a main computing chip of the main board and is directly connected with an SPI interface, which is fixed on the main board by welding or plugging, and the SPI interface is an abbreviation of a serial peripheral interface (Serial Peripheral Interface). SPI is a high-speed, full duplex, synchronous communication bus and occupies only four wires on the pins of the chip. The SPI interface built-in program (SPI data processing chip) can convert data input by a serial port into SPI data and then convey the SPI data to the NPU chip, and the NPU chip directly receives the data transmitted by the SPI interface. According to the utility model, the serial port is connected through the SPI interface, the serial port is not required to be directly connected with the NPU chip, the processing load of the NPU chip can be reduced, meanwhile, the SPI interface can directly convert the data of the serial port into the data type which can be accepted by the SPI interface, and the processing intensity of the NPU chip is further reduced.

In this embodiment, two or more SPI interfaces may be provided on the motherboard, each SPI interface may be connected to several serial ports respectively, or only a specific SPI interface may be used to connect a corresponding number of serial ports. Wherein the number of serial ports can be 2-4. Some serial ports in the embodiment can be directly connected with the NPU chip, and some serial ports can be connected with the NPU chip through the SPI interface.

In another embodiment of the present utility model, when the number of serial ports of the motherboard needs to be increased, only the internal control data of the motherboard needs to be adjusted in the new SPI interface (i.e. the data in the SPI data processing chip is modified), and then the original SPI interface is replaced by the new SPI interface. According to the embodiment, under the condition that only the serial port is added, the SPI interface can be replaced to realize upgrading, the NPU chip does not need to be rewritten, the replacement cost of the whole main board can be reduced, and meanwhile, the whole main board is convenient to upgrade. The use requirement of a user on connecting more modules with the NPU intelligent development board can be met.

According to the SPI interface, the purpose of connecting more serial ports can be achieved by replacing the SPI interface of the control serial port under the condition that the original NPU chip and each connected module are not affected by a user.

A PCIE interface connected with an NPU chip is arranged on a main board, the PCIE interface and an Ethernet interface on the existing main board are respectively connected with the NPU chip and controlled by the NPU chip, and in one embodiment of the utility model, the Ethernet interface is connected with the PCIE interface, and then the PCIE interface converts corresponding data and then transmits the converted data to the NPU chip. The implementation mode overcomes the defect that the existing network transmission mode is too single, converts the data input by the Ethernet port into the data form which can be identified by the PCIE interface, and realizes mutual compatibility of the two transmission modes.

Here, each PCIE interface may be connected to 2-4 ethernet ports, so that the motherboard can connect more devices at the same time.

Furthermore, the PCIE interface connected to the ethernet port is a replaceable interface, and when the ethernet port is added according to the number of devices, the PCIE interface updated with the internal control program may be directly replaced without replacing the NPU chip. When the number of serial ports of the motherboard needs to be increased, the motherboard only needs to adjust the internal control data (namely, modify the data in the PCIE data processing chip) in the new PCIE interface, and then replaces the original PCIE interface with the new PCIE interface. According to the embodiment, under the condition that only serial ports are added, the PCIE interface can be replaced, the NPU chip does not need to be rewritten, the replacement cost of the whole main board can be reduced, and meanwhile the whole main board is convenient to upgrade. The use requirement of a user on connecting more modules with the NPU intelligent development board can be met.

In one embodiment of the present utility model, some of the chips on the motherboard to which the NPU chips are connected are briefly described.

The power adapter inputs 12V/2A power, obtains system power VCC5V0_SYS and VCC3V3_SYS after passing through a front-end buck converter (buck), and then provides system voltage for the PMIC power management chip, the multipath discrete DCDC, the LDO and the field effect transistor switch to output different voltages; the RTC circuit is arranged and controlled through the HYM8563TS chip, so that the clock signal can be ensured not to go wrong under the condition of power failure; the TF Card holder is provided with a TFP09-2-12B Card holder and can be connected with the SD Card; the WiFi module is arranged, and an AP6275PR3 chip is adopted to convert PCIE into an Ethernet port so as to improve the network port function; the HDMI is installed, so that the installation degree of a circuit can be simplified, and three-screen display is supported; the camera interface is arranged, and the MIPI interface is adopted, so that the interface inside the mobile equipment can be standardized; the MIPI interface is installed, so that the MIPI interface has the advantages of high speed, high power consumption and low noise; the control chip of the Ethernet port adopts RTL8111HS so as to facilitate multi-machine networking, and the interface uses PCIE interface; the audio decoder is arranged, the model adopted is ES8388, and an I2C interface is used, so that the audio decoder has the advantages of stereophonic sound, high performance and low power consumption; the M.2_5G module is installed, the M.2_5G module is a 5G module, and the adopted chip is M2_EM06, so that the network transmission speed can be increased.

While the foregoing is directed to the preferred embodiments of the present utility model, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the utility model, such changes and modifications are also intended to be within the scope of the utility model.

Claims

1. The utility model provides a many serial ports NPU intelligence development board, includes mainboard (1), installs NPU chip (2) on mainboard (1), its characterized in that: the NPU chip (2) is connected with an SPI interface (3), the SPI interface (3) is connected with a plurality of serial ports (4), and the SPI interface (3) can convert data input by the serial ports (4) into SPI data.

2. The multi-serial NPU intelligent development board of claim 1, wherein:

the number of serial ports (4) connected with the SPI interface (3) is 2 to 4.

3. The multi-serial NPU intelligent development board of claim 1, wherein:

the SPI interface (3) is a replaceable interface, and is replaced according to the number of the serial ports (4) which is increased.

4. The multi-serial NPU intelligent development board of claim 1, wherein:

the PCIE communication system is characterized in that the PCIE interface (5) is further installed on the main board (1), the PCIE interface (5) is connected with a plurality of Ethernet ports (6), and the PCIE interface (5) can convert data input by the Ethernet ports (6) into PCIE data.

5. The multi-serial NPU intelligent development board of claim 4, wherein:

the PCIE interface (5) is a replaceable interface, and is replaced according to the increased number of the Ethernet ports (6).