CN219459021U

CN219459021U - Internal matching circuit of ceramic tube shell packaging power amplifier

Info

Publication number: CN219459021U
Application number: CN202222227221.5U
Authority: CN
Inventors: 曾瑞锋; 陈志勇; 胡蝶; 祝超; 张振东; 李志强; 马乐; 朱彦青
Original assignee: Nanjing Guomicroelectronics Co ltd; NANJING GUOBO ELECTRONICS CO Ltd
Current assignee: Nanjing Guomicroelectronics Co ltd; NANJING GUOBO ELECTRONICS CO Ltd
Priority date: 2022-08-23
Filing date: 2022-08-23
Publication date: 2023-08-01
Anticipated expiration: 2032-08-23

Abstract

The application provides an internal matching circuit of a ceramic tube shell packaging power amplifier, which comprises a harmonic impedance and envelope impedance control network which are packaged in the ceramic tube shell together with the internal matching power amplifier; one end of a first inductor L1 of the harmonic impedance and envelope impedance control network is connected to an output internal matching capacitor or a tube shell of the internal matching power amplifier, the other end of the first inductor L1 is connected with one end of a first capacitor C1, the other end of the first capacitor C1 is grounded, one end of a second inductor L2 is connected with the first capacitor C1, the other end of the second inductor L2 is connected with the first resistor R1, the other end of the first resistor R1 is connected with one end of a third inductor L3, the other end of the third inductor L3 is connected with a second capacitor C2, the other end of the second capacitor C2 is grounded, the harmonic impedance and envelope impedance control network is added into the internal matching power amplifier packaged by the ceramic tube shell, the memory effect is reduced, and the linearization performance of the device is improved while the power amplifier VBW is greatly improved.

Description

Internal matching circuit of ceramic tube shell packaging power amplifier

Technical Field

The application relates to the technical field of integrated circuits, in particular to an internal matching circuit of a ceramic tube shell packaging power amplifier.

Background

In a wireless communication device, a radio frequency power amplifier as a core component is particularly important. In practical application of the power amplifier, the output efficiency and the memory effect of the power amplifier are two important indexes.

The output efficiency of the power amplifier is dependent on the matching circuit in addition to the performance of the power die itself. The ceramic package shell high-power amplifier internal matching circuit is only used for fundamental wave impedance pre-matching, the harmonic wave impedance matching circuit is usually arranged in the external matching circuit, as shown in fig. 1, the external matching circuit of the power amplifier usually comprises the functions of fundamental wave impedance matching, a bias circuit and the like, and the parasitic effect of the shell and the like, the harmonic wave impedance matching usually cannot reach an optimal state, particularly in the mass production process, due to the discrete effect, the effect of improving the output efficiency is limited by carrying out the harmonic wave impedance matching in the mode, and the output efficiency is usually only 2-3%.

The memory effect of the power amplifier is closely related to the operating bandwidth, and the Video Bandwidth (VBW) representing the operating bandwidth of the radio frequency power amplifier and the memory effect affecting the power amplifier performance are two important factors for measuring the performance of the radio frequency power amplifier. From a frequency domain perspective, the memory effect of a power amplifier is defined as a phenomenon in which the amplitude and phase characteristics of the power amplifier change with changes in the envelope frequency of the input signal. Memory effects of power amplifiers are generally classified into two types, one is an electrical memory effect, which is related to devices and circuit designs of the power amplifiers; the other is the thermal memory effect, which is related to the transistor channel temperature period. Since the thermal memory effect of the power amplifier is optimized by the device manufacturer before the device leaves the factory, the memory effect optimized in the actual design of the power amplifier circuit is usually referred to as the electrical memory effect of the power amplifier.

The main reason for the generation of the electric memory effect is that in the working bandwidth of the amplifier, the source impedance and the load impedance of the amplifier change along with the frequency of the input broadband modulation signal, the frequency correlation characteristic is shown, and finally the amplitude and the phase of the intermodulation component output by the amplifier change along with the frequency of the input signal, and the asymmetry phenomenon of the upper side band and the lower side band of the frequency spectrum component output by the amplifier is embodied. In order to reduce the memory effect, most articles add an auxiliary circuit to the bias circuit to short-circuit the envelope signal and the second harmonic, as shown in fig. 1, but due to the discrete action of the transmission line, the method is difficult to realize broadband short-circuit, and it is difficult to greatly improve the VBW of the power amplifier by reducing the equivalent inductance of the microstrip line at the bias position, and the bias circuit generally has the function of the feed network, so that the function of reducing the envelope impedance is difficult to realize.

Disclosure of Invention

Various exemplary embodiments of the present application provide an internal matching circuit of a ceramic package power amplifier, so as to at least achieve the technical effects of reducing the memory effect of the power amplifier and improving the VBW and output efficiency of the power amplifier.

Various exemplary embodiments of the present application provide an internal matching circuit of a ceramic package power amplifier, including a harmonic impedance and an envelope impedance control network, where the harmonic impedance and the envelope impedance control network are packaged in a ceramic package together with the internal matching power amplifier; the harmonic impedance and envelope impedance control network comprises a first inductor L1, a first capacitor C1, a second inductor L2, a first resistor R1, a third inductor L3 and a second capacitor C2; one end of the first inductor L1 is connected to an output internal matching capacitor or a tube shell of the internal matching power amplifier, the other end of the first inductor L1 is connected with one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, one end of the second inductor L2 is connected with the first capacitor C1, the other end of the second inductor L2 is connected with the first resistor R1, the other end of the first resistor R1 is connected with one end of the third inductor L3, the other end of the third inductor L3 is connected with the second capacitor C2, and the other end of the second capacitor C2 is grounded.

In an embodiment, the first inductor L1, the second inductor L2 and the third inductor L3 are connected by wire bonding wires.

In one embodiment, the first resistor R1, the second capacitor C2, and the third capacitor C3 are respectively a thin film resistor and a ceramic capacitor, and are interconnected by a bond wire.

In an embodiment, the equivalent inductances L of the first inductance L1, the second inductance L2 and the third inductance L3 and the parasitic capacitance Cg of the internal matching power amplifier are in parallel resonance, the resonance frequency is fr, the equivalent inductance l=l1+l2+l3, the video bandwidth of the power amplifier is determined by the resonance frequency fr, and the video bandwidth is controlled by adjusting the golden wire parameters of the second inductance L2 and the third inductance L3.

In an embodiment, the harmonic impedance, envelope impedance control network comprises one or more.

The application has the following beneficial effects:

1. according to the utility model, the second harmonic resistance optimization of the power amplifier is realized through the first inductor L1 and the first capacitor, so that the purpose of improving the power amplifier efficiency is achieved. Compared with the external matching capacitor, the circuit has obvious improvement efficiency, which is approximately 5-6%, and the circuit performs automatic test before the power amplifier device leaves the factory, thereby ensuring the consistency of the device performance and being convenient for the mass production and use of the communication equipment.

2. The utility model achieves the purpose of reducing the envelope impedance through the first resistor R of the envelope network. Compared with a method for improving VBW bandwidth through an external matching bias circuit, when the traditional method envelops frequency resonance, the impedance is usually in a high-impedance area. The utility model not only improves the resonant frequency of the envelope, but also reduces the envelope impedance, so that the envelope impedance is flatter, and the effect of reducing the memory effect is more obvious.

3. The utility model controls the equivalent inductance of the network and the parasitic capacitance of the power tube core to generate resonance, and optimizes and reduces the inductance by controlling the second inductance L2 and the third inductance L3, and improves the resonance frequency of the envelope, thereby widening the video bandwidth of the power amplifier. Compared with the method for reducing the inductance and parasitic inductance on the power supply arm, the video bandwidth of the power amplifier is about 100MHz-200MHz; according to the utility model, the inductance is reduced by adjusting the parameters of the bond wires, and VBW can be increased to about 500 MHz.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 is a schematic diagram of a circuit structure for reducing memory effect and optimizing harmonic impedance of a prior art power amplifier;

FIG. 2 is a block diagram of an internal matching circuit of the ceramic package rate amplifier of the present application;

FIG. 3 simulation results of the present application optimizing envelope impedance;

FIG. 4 is a schematic diagram of one embodiment of a harmonic impedance, envelope impedance control network of the present application;

FIG. 5 is a schematic diagram of one embodiment of the harmonic impedance and envelope impedance control network of the present application;

fig. 6 is a schematic diagram of one embodiment of a harmonic impedance, envelope impedance control network of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

According to the requirement of the 5G communication system on linearization technology and aiming at the defects existing in the prior art, the application provides an internal matching circuit added in an internal matching power amplifier packaged by a ceramic tube shell, and the internal matching circuit has the functions of envelope impedance control and harmonic impedance control, so that the video bandwidth of the power amplifier can be widened, the envelope impedance can be flexibly controlled, the harmonic impedance can be controlled, the envelope impedance can be reduced, the harmonic impedance can be optimized, the memory effect of the power amplifier can be reduced, and the output efficiency of the power amplifier can be improved under the condition that the fundamental wave working frequency band of the power amplifier is not influenced.

As shown in fig. 2, the internal matching circuit of the ceramic tube shell packaging power amplifier comprises a harmonic impedance and envelope impedance control network, wherein the harmonic impedance and envelope impedance control network and the internal matching power amplifier are packaged in the ceramic tube shell together, so that the effects of improving the output efficiency of the power amplifier and the linearization performance of the internal matching power amplifier are achieved.

The harmonic impedance and envelope impedance control network comprises a first inductor L1, a first capacitor C1, a second inductor L2, a first resistor R1, a third inductor L3 and a second capacitor C2; one end of the first inductor L1 is connected to an output internal matching capacitor or a tube shell of the internal matching power amplifier, the other end of the first inductor L1 is connected with one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, one end of the second inductor L2 is connected with the first capacitor C1, the other end of the second inductor L2 is connected with the first resistor R1, the other end of the first resistor R1 is connected with one end of the third inductor L3, the other end of the third inductor L3 is connected with the second capacitor C2, and the other end of the second capacitor C2 is grounded. The first inductor L1, the second inductor L2 and the third inductor L3 are connected through gold bonding wires, namely, the variables such as arc height, span, number of gold wires and the like of the bonding alloy wires are adjusted to control the magnitude of inductance.

The first resistor R1, the second capacitor C2 and the third capacitor C3 are respectively made of film resistor and ceramic capacitor and are interconnected through bonding alloy wires, the equivalent inductance L of the first inductor L1, the second inductor L2 and the third inductor L3 and the parasitic capacitance Cg of the internal matching power amplifier are in parallel resonance, the resonance frequency is fr, the equivalent inductance L=L1+L2+L3, and the video bandwidth is controlled by adjusting gold wire parameters of the second inductor L2 and the third inductor L3. The higher the resonant frequency, the wider the video bandwidth of the power amplifier. The video bandwidth of a power amplifier is a direct reflection of the capability of the power amplifier to handle broadband signals, which is usually determined by the parallel resonant frequency fr, the higher the resonant frequency, the wider the video bandwidth. The correlation formula is as follows:

since the parasitic capacitance Cg of the die itself is already a constant value, the video bandwidth of the power amplifier can be controlled by adjusting the gold parameters of the second inductor L2 and the third inductor L3.

It should be noted that, at present, the conventional power amplifier is based on an external matching circuit to improve a bias circuit to reduce the memory effect and the second harmonic matching, for example, the drain adopts a dual bias network form, a shorter and wider drain bias network, and adopts a multi-stage bypass decoupling. However, these methods have limited VBW widening, and the shorter and wider bias networks can cause low frequency performance degradation, and the envelope impedance is usually in the high-impedance region, which is unfavorable for reducing the memory effect of the broadband signal.

The ceramic package shown in fig. 2 is internally packaged with a GaN HEMT die, an input-output matching circuit, and a harmonic impedance and envelope impedance control network. Cg is the die output capacitance, determined by the die gate width. The output matching circuit adopts a T-shaped LCL low-pass filter network to realize impedance conversion, wherein L is realized by gold wire bonding wires. The bonding wire inductor realizes the electrical interconnection of the device and the microstrip circuit while meeting circuit matching. C is a ceramic capacitor, and the circuit has better impedance transformation ratio through the adjustment of the gold wire bonding lead and the ceramic capacitor.

The first inductor L1 and the first capacitor C1 are used for optimizing harmonic impedance and improving power amplification efficiency. The first capacitance value is selected according to the frequency of the second harmonic, and for a power amplifier in the frequency range of 700MHz-4000MHz, the capacitance value and capacitance range of the capacitor are usually about 0.5pf-3pf, and the first inductor L1 realizes the change of inductance by adjusting a gold wire, so that the harmonic impedance of the power amplifier works in a higher efficiency area. The efficiency improvement achieved at present is nearly 5%, which is superior to the traditional method.

The equivalent inductances of the first inductor L1, the second inductor L2 and the third inductor L3 are in a high-resistance state for the fundamental wave, namely, the performance of the fundamental wave is not influenced, namely, the power amplifier is not influenced in the fundamental wave working frequency band. Since the first inductance L1 is mainly used for adjusting the harmonic impedance, the fundamental wave performance is normally not affected by the adjustment of the second and third inductances L3. The filter capacitance and resistance act to reduce the envelope impedance while providing good radio frequency to ground performance.

The third-order intermodulation products controlled by the envelope are filtered out by an additional circuit. The filter capacitor in the utility model has the function of introducing the resonant circuit to control the baseband impedance, and reducing the baseband impedance to make the third-order intermodulation distortion caused by the baseband impedance as small as possible. The baseband impedance, also referred to as envelope impedance, refers to the impedance that the amplifier responds to in the baseband frequency band, which includes the modulated signal (envelope) frequency band and the difference frequency of the carriers in the case of multiple carriers. The first resistor R1 is introduced to avoid that the envelope frequency band presents a pure LC network resonance causing a very large impedance value within the envelope frequency band of the signal.

As shown in fig. 3, curve S (2, 2) is the envelope impedance realized when the VBW bandwidth is increased by the conventional method, and at the resonance point, the envelope impedance is in the high impedance region; curve S (4, 4) is the envelope impedance achieved by the present utility model when the VBW bandwidth is increased by introducing the first resistor R1 simultaneously, at the resonance point the envelope impedance is to be in the low resistance region, and the whole in-band (DC-500 MHz) envelope impedance is flatter.

As shown in fig. 4, in this embodiment, for the high-efficiency, low-volume application of the Doherty technology, such a device integrates two independent power amplifier tubes (used as Carrier amplifier and Peak amplifier of the Doherty amplifier, respectively) in one package. According to the utility model, the harmonic impedance and the envelope impedance control network are respectively added to two independent power amplifiers, so that the power amplifier efficiency is improved, the memory effect of the power amplifier is reduced, and the linearization performance of the device is improved.

As shown in fig. 5, the envelope impedance control network may also be directly connected to the tube shell through a gold wire, so as to achieve the effect of reducing the memory effect of the power amplifier.

As shown in fig. 6, in the present embodiment, the circuit for reducing memory effect of the present utility model can be applied to internal matching power amplifiers of different types of ceramic package.

In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or an implicit indication of the number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include 1 or more such feature. In the description of the present application, the meaning of "plurality" is at least 2, such as 2, 3, etc., unless explicitly defined otherwise.

While the preferred embodiments of the present application have been described, additional variations and modifications in light of these examples may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all alterations and modifications as fall within the scope of the application.

Finally, it should be noted that the above embodiments are merely for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present application.

Claims

1. The internal matching circuit of the ceramic tube shell packaging power amplifier is applied to the ceramic tube shell packaging internal matching power amplifier and is characterized by comprising a harmonic impedance and envelope impedance control network, wherein the harmonic impedance and envelope impedance control network and the internal matching power amplifier are packaged in the ceramic tube shell together; the harmonic impedance and envelope impedance control network comprises a first inductor L1, a first capacitor C1, a second inductor L2, a first resistor R1, a third inductor L3 and a second capacitor C2; one end of the first inductor L1 is connected to an output internal matching capacitor or a tube shell of the internal matching power amplifier, the other end of the first inductor L1 is connected with one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, one end of the second inductor L2 is connected with the first capacitor C1, the other end of the second inductor L2 is connected with the first resistor R1, the other end of the first resistor R1 is connected with one end of the third inductor L3, the other end of the third inductor L3 is connected with the second capacitor C2, and the other end of the second capacitor C2 is grounded.

2. The internal matching circuit of a ceramic package power amplifier of claim 1, wherein said first inductor L1, said second inductor L2 and said third inductor L3 are connected by wire bonding wires.

3. The internal matching circuit of a ceramic package power amplifier according to claim 2, wherein the first resistor R1, the second capacitor C2 and the third capacitor C3 are respectively a thin film resistor and a ceramic capacitor and are interconnected by a bond wire.

4. The internal matching circuit of a ceramic package power amplifier according to claim 3, wherein an equivalent inductance L of the first inductance L1, the second inductance L2, and the third inductance L3 is parallel-resonant with a parasitic capacitance Cg of the internal matching power amplifier, the resonant frequency is fr, and the equivalent inductance l=l1+l2+l3.

5. The internal matching circuit of a ceramic package power amplifier of claim 4, wherein said harmonic impedance, envelope impedance control network comprises one or more.

6. The internal matching circuit of a ceramic package power amplifier of claim 5, wherein said harmonic impedance, envelope impedance control network is directly connected to the package by wires.