CN219457586U - Chip packaging structure and electronic equipment - Google Patents

Abstract

The application discloses chip packaging structure and electronic equipment, chip packaging structure includes the encapsulation base plate, fix the encapsulation lid shell on the encapsulation base plate, naked chip and strengthening rib, encapsulation lid shell and naked chip are located one side of encapsulation base plate, encapsulation lid shell encloses into an accommodation space with encapsulation base plate, naked chip is located accommodation space, and naked chip and encapsulation base plate electricity are connected, the strengthening rib is located the encapsulation base plate all around, and the strengthening rib is located at least one side that encapsulation base plate deviates from encapsulation lid shell, thereby can be through encapsulation lid shell and the strengthening rib that is located the encapsulation base plate relative both sides respectively, apply stress to encapsulation base plate from relative both sides, and then can suppress the warpage of chip packaging structure furthest, avoid chip packaging structure to warp and consequently solder joint subsides and bridging scheduling problem appears.

Description

Chip packaging structure and electronic equipment

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a chip packaging structure and electronic equipment.

Background

A DIE, also called a DIE or DIE, is a fully functional chip structure formed through circuit design and wafer fabrication processes. In order to prevent the die from being damaged by the outside, a packaging material or the like is generally used to package the die to form a chip packaging structure. However, the current chip packaging structure has a warpage problem, which affects the performance of the chip packaging structure.

Disclosure of Invention

The application discloses a chip packaging structure and electronic equipment to solve the problem of warpage.

In a first aspect, the application discloses a chip packaging structure, which comprises a packaging substrate, a packaging cover shell fixed on the packaging substrate, a bare chip and a reinforcing rib; the packaging cover shell and the bare chip are positioned on one side of the packaging substrate, the packaging cover shell and the packaging substrate enclose an accommodating space, the bare chip is positioned in the accommodating space, and the bare chip is electrically connected with the packaging substrate; the reinforcing ribs are located around the packaging substrate and at least located on one side, away from the packaging cover shell, of the packaging substrate.

Based on this, through the encapsulation lid shell and the strengthening rib that are located the encapsulation base plate relative both sides respectively, exert stress to the encapsulation base plate from relative both sides, and then can suppress the warpage of encapsulation base plate from relative both sides, and then can furthest suppress the warpage of chip packaging structure, avoid the chip packaging structure to appear solder joint subsidence and bridging scheduling problem because of the warpage.

In some alternative examples, the stiffener includes a first stiffener and a second stiffener; the first reinforcing ribs are positioned around the packaging substrate, and the first reinforcing ribs are positioned on the surface of one side, away from the packaging cover shell, of the packaging substrate; the second reinforcing ribs are located around the packaging substrate and located on one side surface of the packaging substrate, which is close to the packaging cover shell, or located on the side surface of the packaging substrate.

Based on this, can be through being located the first strengthening rib and the second strengthening rib of encapsulation base plate both sides respectively, exert stress to encapsulation base plate from both sides, and then can suppress the warpage of encapsulation base plate from both sides, and then can furthest suppress the warpage of chip packaging structure, avoid chip packaging structure to appear solder joint subsidence and bridging scheduling problem because of the warpage.

In some alternative examples, the reinforcing bars include a first reinforcing bar, a second reinforcing bar, and a third reinforcing bar; the first reinforcing ribs are positioned around the packaging substrate, and the first reinforcing ribs are positioned on the surface of one side, away from the packaging cover shell, of the packaging substrate; the second reinforcing ribs are positioned around the packaging substrate and positioned on the surface of one side of the packaging substrate, which is close to the packaging cover shell; the third reinforcing rib is located on the side face of the packaging substrate and is connected with the first reinforcing rib and the second reinforcing rib.

Based on the above, the warpage of the package substrate can be further suppressed by the first reinforcing rib, the second reinforcing rib and the third reinforcing rib which are respectively positioned at the three sides of the package substrate, so that the warpage of the chip package structure can be suppressed to the greatest extent, and the problems of welding spot collapse, bridging and the like of the chip package structure due to the warpage are avoided.

In some alternative examples, a side of the package substrate facing away from the package cover has solder balls; the thickness of the reinforcing rib at one side of the packaging substrate, which is away from the packaging cover shell, is smaller than the thickness of the solder balls, and the width of the reinforcing rib at one side of the packaging substrate, which is away from the packaging cover shell, is smaller than the distance between the solder balls and the side face of the packaging substrate. Based on this, the reinforcing ribs can be prevented from affecting the mounting of the package substrate and the integrated circuit board.

In some optional examples, the thickness of the reinforcing rib on the side of the packaging substrate facing away from the packaging cover shell ranges from 0.2mm to 0.3mm; the width range of the reinforcing rib at one side of the packaging substrate, which is away from the packaging cover shell, is 0.3-0.5 mm so as to ensure the convenience of the mounting of the packaging substrate and the integrated circuit board.

In some alternative examples, the material of the stiffener includes a metallic material including a stainless steel material. Accordingly, the warpage-suppressing effect of the reinforcing rib can be improved by the metal material having poor ductility.

In some alternative examples, the packaging cover shell comprises a cover plate and side walls positioned around the cover plate; the cover plate comprises a first plate area and a second plate area; the first board region is fixedly connected with the bare chip; the second plate region is located between the first plate region and the sidewall; the first plate area protrudes from the second plate area towards one side surface of the packaging substrate.

In some alternative examples, the thickness of the first plate region is greater than the thickness of the second plate region. Based on the method, the warping of the chip packaging structure can be further resisted through the first plate area with larger thickness and heavier weight, the bare chip is protected from being damaged, the failure probability of the chip packaging structure is reduced, the weight of the whole packaging cover shell is reduced through the second plate area with smaller thickness and lighter weight, and the risk of welding spot collapse, bridging among welding spots and other process problems caused by overlarge weight of the packaging cover shell in the packaging process is reduced.

In some alternative examples, the chip package structure further includes a passive device disposed between the second board region and the package substrate. Based on the above, when the height of the passive device is larger than that of the bare chip, the passive device can be packaged inside the packaging cover shell, so that the packaging welding risk of the passive device is reduced.

In some alternative examples, a distance between a surface of the third board region facing the package substrate and the passive device is greater than or equal to 0.2mm. Based on this, the passive device can be more conveniently installed and dissipated.

In a second aspect, the application provides an electronic device, which includes the chip packaging structure as claimed in any one of the above. Based on the method, the warping of the chip packaging structure can be restrained to the greatest extent, the problems of welding spot collapse, bridging and the like of the chip packaging structure caused by the warping are avoided, and the using effect of the electronic equipment is ensured.

Drawings

In order to more clearly describe the technical solutions in the embodiments or the background of the present application, the following description will describe the drawings that are required to be used in the embodiments or the background of the present application.

Fig. 1 is a schematic cross-sectional structure of a chip package structure disclosed in the present application;

fig. 2 is a schematic top view of a chip package structure according to an embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional view of the chip package structure shown in fig. 2 along a cutting line AA';

FIG. 4 is a schematic top view of another chip package structure according to an embodiment of the disclosure;

FIG. 5 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

FIG. 6 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

FIG. 7 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

fig. 8 is a schematic bottom view of a chip package structure according to an embodiment of the present disclosure;

FIG. 9 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

FIG. 10 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

FIG. 11 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

FIG. 12 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

fig. 13 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Most of the current Chip package structures are Flip Chip (Flip Chip) structures, which are leadless structures, as shown in fig. 1, fig. 1 is a schematic cross-sectional structure of a Chip package structure disclosed in the present application, and the Chip package structure includes a die 10, a package substrate 11 and a package cover 12. The package cover 12 and the package substrate 11 enclose an enclosed space, and the enclosed space is used for accommodating the die 10, so as to provide a certain mechanical protection for the die 10.

As shown in fig. 1, the package cover 12 is fixedly connected with the package substrate 11 through the adhesive 13, and the bare chip 10 is fixedly connected with the package substrate 11 through the filling adhesive 14, however, because the thermal expansion coefficients of the package substrate 11, the package cover 12 and the adhesive 13 are not matched, the thermal expansion coefficients of the package substrate 11, the bare chip 10 and the filling adhesive 14 are also not matched, and therefore, when the surface mounting technology is adopted to heat the molten solder balls 110, when the chip package structure is fixedly connected with the integrated circuit board through the molten solder balls 110, the temperature change can lead to the package substrate 11 to warp, and further the chip package structure has the problems of solder joint collapse where the solder balls 110 are located, bridging between adjacent solder joints and the like.

Based on this, this application discloses a chip packaging structure, sets up the strengthening rib at least in the encapsulation base plate one side that deviates from encapsulation lid, through encapsulation lid and the strengthening rib that is located the encapsulation base plate relative both sides, applies stress to encapsulation base plate from relative both sides, suppresses the warpage of encapsulation base plate from relative both sides.

As an optional implementation of the disclosure, an embodiment of the present application discloses a chip package structure, as shown in fig. 2 and fig. 3, fig. 2 is a schematic top view of the chip package structure disclosed in the embodiment of the present application, and fig. 3 is a schematic cross-sectional structure of the chip package structure along a cutting line AA' shown in fig. 2, where the chip package structure includes a die 10, a package substrate 11, a package cover 12, and a stiffener 15, and the die 10, the package cover 12, and the stiffener 15 are all fixed on the package substrate 11.

As shown in fig. 3, the package cover 12 and the die 10 are located at one side of the package substrate 11, the package cover 12 and the package substrate 11 enclose an accommodating space, the die 10 is located in the accommodating space, and the die 10 is electrically connected with the package substrate 11. As shown in fig. 2, the reinforcing ribs 15 are located around the package substrate 11, and as shown in fig. 3, the reinforcing ribs 15 are located at least on a side of the package substrate 11 facing away from the package cover 12.

Since the package cover 12 and the stiffener 15 are respectively located at two opposite sides of the package substrate 11, the package cover 12 and the stiffener 15 can apply stress to the package substrate 11 from two opposite sides, that is, the package cover 12 can apply stress to the package substrate 11 along the Z ' direction, and the stiffener 15 can apply stress to the package substrate 11 along the Z ' direction, so that warpage of the chip package structure in the Z and Z ' directions can be suppressed to the greatest extent, and problems such as solder joint collapse and bridging of the chip package structure due to warpage are avoided.

In some embodiments of the present application, as shown in fig. 2, the reinforcing ribs 15 may be disposed continuously around the periphery of the package substrate 11, however, the present application is not limited thereto, and in other embodiments, as shown in fig. 4, the reinforcing ribs 15 may be disposed discontinuously around the periphery of the package substrate 11. In practical applications, when the warpage of the package substrate 11 is asymmetric or uneven, the number of reinforcing ribs 15 may be increased or the density may be increased at the portion having the larger warpage, and the number of reinforcing ribs 15 may be decreased or the density may be decreased at the portion having the smaller warpage.

In some embodiments of the present application, as shown in fig. 3, the stiffener 15 may be located on only one side of the package substrate 11 facing away from the package cover 12, and of course, the present application is not limited thereto, and in other embodiments, the stiffener 15 may be located on one side of the package substrate 11 facing away from the package cover 12 and one side of the package substrate 11 near the package cover 12.

In some embodiments, as shown in fig. 5, the reinforcing bars 15 may include a first reinforcing bar 151 and a second reinforcing bar 152. The first reinforcing ribs 151 are located around the package substrate 11, and the first reinforcing ribs 151 are located on one side of the package substrate 11 facing away from the package cover 12. The second reinforcing ribs 152 are located around the package substrate 11, and the second reinforcing ribs 152 are located on one side of the package substrate 11 close to the package cover 12. Alternatively, in other embodiments, as shown in fig. 6, the second stiffener 152 may be further located at a side of the package substrate 11 and connected to the first stiffener 151.

Based on this, stress can be applied to the package substrate 11 from both sides by the first stiffener 151 and the second stiffener 152 respectively located at both sides of the package substrate 11, and thus warpage of the package substrate 11 can be suppressed from both sides, and warpage of the chip package structure can be suppressed to the greatest extent, and problems such as solder joint collapse and bridging due to warpage of the chip package structure can be avoided.

In other embodiments, as shown in fig. 7, the stiffener 15 may further include a first stiffener 151, a second stiffener 152 and a third stiffener 153, where the first stiffener 151 is located around the package substrate 11, and the first stiffener 151 is located on a side surface of the package substrate 11 facing away from the package cover 12, the second stiffener 152 is located around the package substrate 11, and the second stiffener 152 is located on a side surface of the package substrate 11 near the package cover 12, the third stiffener 153 is located on a peripheral side surface of the package substrate 11, and the third stiffener 153 connects the first stiffener 151 and the second stiffener 152.

Based on this, the warpage of the package substrate 11 can be further suppressed by the first stiffener 151, the second stiffener 152, and the third stiffener 153 respectively located at the three sides of the package substrate 11, so that the warpage of the chip package structure can be suppressed to the greatest extent, and the problems of solder joint collapse, bridging, and the like of the chip package structure due to the warpage can be avoided. It is understood that the first reinforcing rib 151, the second reinforcing rib 152, and the third reinforcing rib 153 may be continuously disposed or discontinuously disposed around the package substrate 11.

In this embodiment, the side of the package substrate 11 facing away from the package cover 12 has solder balls 110, and the solder balls 110 are used to electrically connect the package substrate 11 with the integrated circuit board, so that the die 10 is electrically connected with other devices on the integrated circuit board. In some embodiments, as shown in fig. 7 and 8, the thickness D1 of the stiffener 15 on the side of the package substrate 11 facing away from the package cover 12 is smaller than the thickness D2 of the solder balls 110, and the width L1 of the stiffener 15 on the side of the package substrate 11 facing away from the package cover 12 is smaller than the distance L2 between the solder balls 110 and the side of the package substrate 11, so that the stiffener 15 does not affect the mounting of the package substrate 11 and the integrated circuit board.

Optionally, a distance L3 between the solder balls 110 and the stiffener 15 on a side of the package substrate 11 facing away from the package cover 12 is greater than 0.5mm, so as to ensure convenience in mounting the package substrate 11 and the integrated circuit board. Optionally, the thickness D1 of the reinforcing rib 15 on the side of the package substrate 11 facing away from the package cover 12 ranges from 0.2mm to 0.3mm; the width L1 of the reinforcing rib 15 on the side of the package substrate 11 facing away from the package cover 12 ranges from 0.3mm to 0.5mm.

In some embodiments of the present application, the material of the reinforcing rib 15 includes a metal material including a stainless steel material or a copper material, etc., so as to improve the buckling suppressing effect of the reinforcing rib 15 through the metal material having poor ductility. It is understood that the stiffener 15 may be directly formed on the package substrate 11, or may be bonded to the package substrate 11 by an adhesive material or the like.

In some embodiments of the present application, the encapsulation cover 12 comprises a metal cover, and the connection material between the encapsulation cover 12 and the die comprises a metal solder material, wherein the metal solder material comprises indium. In other embodiments, the connection material may further include silicone grease material, etc., which will not be described herein. Based on this, a heat dissipation channel between the die 10 and the package cover 12 can be established by a metal solder material with good heat conduction performance, so that heat dissipation of the die 10 can be better realized.

In some embodiments, the material of the metal cap includes copper or copper alloy to further inhibit warpage of the die 10 by the metal cap. And the surface of the metal cover shell can be plated with nickel or gold to realize good infiltration of metal welding materials such as indium and achieve reliable welding effect.

In some embodiments of the present application, as shown in fig. 9, the package cover 12 includes a cover 120 and a sidewall 121 around the cover 120, the die 10 is fixed between the cover 120 and the package substrate 11, and the sidewall 121 is fixedly connected with the package substrate 11. The cover plate 120 may include a first plate region 120a and a second plate region 120b, where the first plate region 120a is fixedly connected with the die 10, the second plate region 120b is located between the first plate region 120a and the sidewall 121, and a side surface of the first plate region 120a facing the package substrate 11 protrudes from a side surface of the second plate region 120b facing the package substrate 11.

In some embodiments of the present application, as shown in fig. 9, a side surface of the first board area 120a facing away from the package substrate 11 is coplanar with a side surface of the second board area 120b facing away from the package substrate 11, and a side surface of the first board area 120a facing toward the package substrate 11 protrudes from a side surface of the second board area 120b facing toward the package substrate 11. Of course, the present application is not limited thereto, and in other embodiments, a side surface of the first plate region 120a and the second plate region 120b facing away from the package substrate 11 may not be coplanar. As shown in fig. 10, a side surface of the first board region 120a facing the package substrate 11 protrudes from a side surface of the second board region 120b facing the package substrate 11, and a side surface of the second board region 120b facing away from the package substrate 11 protrudes from a side surface of the first board region 120a facing away from the package substrate 11.

In some embodiments of the present application, as shown in fig. 11 and 12, the chip package structure further includes a passive device 16, where the passive device 16 is disposed between the second board area 120b and the package substrate 11. Based on this, the passive device 16 may be packaged inside the package cover 12 when the height of the passive device 16 is greater than the height of the die 10 to reduce the risk of soldering the passive device 16. The passive devices 16 may be resistors, capacitors, inductors, filters, etc. In some embodiments, passive device 16 is a decoupling capacitor connected to the power pins of die 10 that is used to reduce the noise effects of other devices in the circuit on die 10.

It will be appreciated that the size of the space between the second plate region 120b and the package substrate 11 depends on the size of the passive device 16. For example, if the size of the passive device 16 is 0.5mm×1.0mm, the space between the second board region 120b and the package substrate 11 is kept as small as 0.6mm×1.1mm. Optionally, a distance L3 between a side surface of the second board region 120b facing the package substrate 11 and the passive device 16 is greater than or equal to 0.2mm, so as to facilitate mounting and heat dissipation of the passive device 16.

In some embodiments of the present application, as shown in fig. 9 and 13, the thickness D3 of the first plate region 120a is greater than the thickness D4 of the second plate region 120 b. By making the thickness of the first board region 120a greater than that of the second board region 120b, the warpage of the chip package structure can be further resisted by the first board region 120a with greater thickness and heavier weight, the bare chip 10 is protected from damage, the failure probability of the chip package structure is reduced, the weight of the whole package cover 12 is reduced by the second board region 120b with smaller thickness and lighter weight, and the risk of technical problems such as solder joint collapse and bridging between solder joints caused by overlarge weight of the package cover 12 in the packaging process is reduced.

As another optional implementation of the disclosure, an embodiment of the present application discloses an electronic device, which includes the chip package structure disclosed in any one of the embodiments above. The electronic device may be a smart phone, a tablet computer, a digital camera, a server, etc. Based on the method, the warping of the chip packaging structure can be restrained to the greatest extent, the problems of welding spot collapse, bridging and the like of the chip packaging structure caused by the warping are avoided, and the using effect of the electronic equipment is ensured.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present specification, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the present description, which is within the scope of the present description. Accordingly, the protection scope of the patent should be determined by the appended claims.

Claims (10)

1. The chip packaging structure is characterized by comprising a packaging substrate, a packaging cover shell, a bare chip and a reinforcing rib, wherein the packaging cover shell is fixed on the packaging substrate;

the packaging cover shell and the bare chip are positioned on one side of the packaging substrate, the packaging cover shell and the packaging substrate enclose an accommodating space, the bare chip is positioned in the accommodating space, and the bare chip is electrically connected with the packaging substrate;

the reinforcing ribs are located around the packaging substrate and at least located on one side, away from the packaging cover shell, of the packaging substrate.

2. The chip package structure of claim 1, wherein the stiffener comprises a first stiffener and a second stiffener;

the first reinforcing ribs are positioned around the packaging substrate, and the first reinforcing ribs are positioned on the surface of one side, away from the packaging cover shell, of the packaging substrate;

the second reinforcing ribs are located around the packaging substrate and located on one side surface of the packaging substrate, which is close to the packaging cover shell, or located on the side surface of the packaging substrate.

3. The chip package structure of claim 1, wherein the stiffener comprises a first stiffener, a second stiffener, and a third stiffener;

the first reinforcing ribs are positioned around the packaging substrate, and the first reinforcing ribs are positioned on the surface of one side, away from the packaging cover shell, of the packaging substrate;

the second reinforcing ribs are positioned around the packaging substrate and positioned on the surface of one side of the packaging substrate, which is close to the packaging cover shell;

the third reinforcing rib is located on the side face of the packaging substrate and is connected with the first reinforcing rib and the second reinforcing rib.

4. The chip package structure of claim 1, wherein a side of the package substrate facing away from the package cover has solder balls; the thickness of the reinforcing rib at one side of the packaging substrate, which is away from the packaging cover shell, is smaller than the thickness of the solder balls, and the width of the reinforcing rib at one side of the packaging substrate, which is away from the packaging cover shell, is smaller than the distance between the solder balls and the side face of the packaging substrate.

5. The chip package structure according to claim 4, wherein the thickness of the reinforcing rib on the side of the package substrate facing away from the package cover is in the range of 0.2mm to 0.3mm; the width range of the reinforcing rib at one side of the packaging substrate, which is away from the packaging cover shell, is 0.3-0.5 mm.

6. The chip package structure of claim 1, wherein the material of the stiffener comprises a metallic material comprising a stainless steel material.

7. The chip packaging structure according to claim 1, wherein the packaging cover shell comprises a cover plate and side walls positioned around the cover plate; the cover plate comprises a first plate area and a second plate area;

the first board region is fixedly connected with the bare chip; the second plate region is located between the first plate region and the sidewall; the first plate area protrudes from the second plate area towards one side surface of the packaging substrate.

8. The chip package structure of claim 7, wherein a thickness of the first board region is greater than a thickness of the second board region.

9. The chip package structure of claim 7, further comprising a passive device disposed between the second board region and the package substrate.

10. An electronic device comprising the chip package structure of any one of claims 1 to 9.