CN218632020U - Packaging cover shell, chip packaging structure and electronic equipment - Google Patents

Abstract

The application discloses encapsulation lid shell, chip package structure and electronic equipment, encapsulation lid shell include the miniflow way, and the miniflow way is located inside the encapsulation lid shell, and the miniflow way is used for dispelling the heat through its inside coolant that flows to encapsulation lid shell and bare chip to improve the heat-sinking capability of encapsulation lid shell, prolong chip package structure and electronic equipment's life.

Description

Packaging cover shell, chip packaging structure and electronic equipment

Technical Field

The application relates to the technical field of chip packaging, in particular to a packaging cover shell, a chip packaging structure and electronic equipment.

Background

Along with the increasing size of the chip packaging structure, the packaging cover shell in the chip packaging structure is also thicker and thicker so as to resist the increasing warping generated by the chip packaging structure after the heating process, and protect the key parts of the chip packaging structure from being damaged. However, this results in poor heat dissipation capability of the chip package structure.

SUMMERY OF THE UTILITY MODEL

The application discloses encapsulation lid shell, chip package structure and electronic equipment to improve chip package structure's heat-sinking capability.

In a first aspect, the application discloses a package cover shell for encapsulating a bare chip, the package cover shell includes a micro-channel, the micro-channel is located inside the package cover shell, the micro-channel is used for cooling agent flowing through the interior of the micro-channel, and is right the package cover shell reaches the bare chip dissipates heat. Therefore, the heat dissipation capacity of the packaging cover shell can be improved, and the service lives of the chip packaging structure and the electronic equipment are prolonged.

In some optional examples, the die is located on a side surface of the package cover shell, and the micro flow channel at least partially covers the die to achieve effective heat dissipation for the die that generates more heat.

In some alternative examples, the inlet and outlet of the micro flow channel are located on the side of the package cover shell facing away from the die, so as to prevent coolant in the micro flow channel from corroding the connection lines and the like of the die and affecting the normal operation of the die.

In some alternative examples, the microfluidic channel comprises a plurality of first channels and a plurality of second channels; the first flow channel extends along a first direction, the second flow channel extends along a second direction, and the first direction and the second direction are intersected; the plurality of first flow channels are sequentially arranged along the second direction, and the second flow channel is positioned between two adjacent first flow channels, so that the two adjacent first flow channels are connected end to end, the micro flow channels uniformly cover the bare chip, and the uniform heat dissipation of the bare chip is realized.

In some alternative examples, the package cover shell includes a first portion and a second portion; the second part is located at the periphery of the first part, the thickness of the first part is larger than that of the second part, the first part is used for being fixedly connected with the bare chip, the micro flow channel is located inside the first part, the warping of the bare chip is resisted through the first part with larger thickness and heavier weight, the bare chip is protected from being damaged, the weight of the packaging cover shell is reduced through the second part with smaller thickness, and the process risks of welding point collapse, bridging and the like caused by the fact that the packaging cover shell is too heavy in the BGA packaging process are reduced.

In some optional examples, the package lid shell comprises a first surface for fixed connection with the die; the first surface is provided with a plurality of micro grooves for accommodating the connecting material between the first surface and the bare chip, so that the contact area of the connecting material with the first surface and the bare chip can be increased, the connecting material can be prevented from flowing excessively, and the connecting effect between the bare chip and the packaging cover shell can be enhanced.

In some alternative examples, the packaging cover shell is provided with a packaging retaining wall at the periphery; the packaging retaining wall is used for being fixedly connected with a packaging substrate of the bare chip, so that the packaging cover shell and the packaging substrate enclose a closed space for containing the bare chip; and the surface of one side of the packaging retaining wall facing the packaging substrate is provided with reinforcing ribs or fins so as to resist the warping of the packaging substrate caused by overlarge size through the reinforcing ribs.

In some optional examples, the package cover shell is provided with air holes, the air holes are located at the periphery of the micro flow channel, and the air holes are used for enabling the closed space where the bare chip is located to be communicated with the outside so as to eliminate volatile gas and the like generated by soldering flux when the bare chip is welded with the package substrate.

In a second aspect, the present application discloses a chip package structure, including the package cover shell as described in any one of the above. Because the micro-channel in the packaging cover shell can radiate the packaging cover shell and the bare chip through flowing coolant, the radiating capacity of the packaging cover shell can be improved, and the service life of the chip packaging structure is prolonged.

In a third aspect, the application discloses an electronic device comprising a chip packaging structure as described in any of the above. Because the micro-channel in the packaging cover shell in the chip packaging structure can radiate the packaging cover shell and the bare chip through flowing coolant, the radiating capacity of the packaging cover shell can be improved, and the service life of the chip packaging structure is prolonged.

The utility model discloses a encapsulation lid shell, chip package structure and electronic equipment, encapsulation lid shell are including being located its inside microchannel, because this microchannel can dispel the heat through its inside coolant that flows, to encapsulation lid shell and bare chip, consequently, can improve the heat-sinking capability of encapsulation lid shell, prolong chip package structure and electronic equipment's life.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the background art of the present application, the drawings required to be used in the embodiments or the background art of the present application will be described below.

Fig. 1 is a schematic cross-sectional view illustrating a chip package structure disclosed in the present application;

fig. 2 is a schematic top view of a package cover disclosed in an embodiment of the present application;

fig. 3 is a schematic cross-sectional view of the package cover casing shown in fig. 2 along a cutting line AA';

fig. 4 is a schematic top view of another package cover disclosed in the embodiments of the present application;

fig. 5 is a schematic cross-sectional view of the package cover case shown in fig. 4 along a cutting line BB';

FIG. 6 is a schematic structural view of a micro flow channel according to an embodiment of the present invention;

FIG. 7 is a schematic view showing the structure of another micro flow channel disclosed in the embodiment of the present application;

fig. 8 is a schematic bottom view of another package cover disclosed in the embodiments of the present application;

fig. 9 is a schematic cross-sectional view of the package cover case shown in fig. 8 along a cutting line CC;

fig. 10 is a schematic cross-sectional view of another package cover disclosed in the embodiments of the present application;

fig. 11 is a schematic bottom view of another package cover disclosed in the embodiments of the present application;

fig. 12 is a schematic cross-sectional view of the package cover case shown in fig. 11 along a cutting line DD';

fig. 13 is a schematic bottom view of another package cover disclosed in the embodiments of the present application;

fig. 14 is a schematic cross-sectional view of the package cover case shown in fig. 13 along cutting line EE';

fig. 15 is a schematic bottom view of another package cover disclosed in the embodiments of the present application;

fig. 16 is a schematic top view of another package cover disclosed in the embodiments of the present application;

fig. 17 is a schematic cross-sectional view of the package cover case shown in fig. 16 along a cutting line FF';

fig. 18 is a schematic cross-sectional view of another package cover disclosed in the embodiments of the present application;

fig. 19 is a schematic cross-sectional structure diagram of a chip package structure according to an embodiment of the disclosure;

fig. 20 is a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the disclosure;

fig. 21 is a schematic cross-sectional structure diagram of a chip package structure disclosed in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

Most of the current Chip package structures are Flip Chip (Flip Chip) structures, the Flip Chip structures are pin-less structures, as shown in fig. 1, fig. 1 is a schematic cross-sectional structure diagram of a Chip package structure disclosed in this application, solder balls 11 are deposited on input/output pads of a die 10, the solder balls 11 include tin lead balls, and the die 10 can be electrically connected to a package substrate 12 through the melted solder balls 11 by heating the die 10.

Since the package substrate 12 also has a plurality of solder balls 13 electrically connected to a PCB (Printed Circuit Board) Board or the like at the bottom thereof, and the plurality of solder balls 13 are arranged in a Grid-like pattern, the package structure is also called a BGA (Ball Grid Array) package structure.

As shown in fig. 1, the chip package structure generally includes a package cover 14, where the package cover 14 and the package substrate 12 enclose an enclosed space for accommodating the die 10, so as to provide a certain mechanical protection for the die 10. As the size of the chip package structure is larger and larger, the package cover 14 is thicker and thicker to resist the larger and larger warpage generated by the chip package structure after the chip package structure is subjected to the heating process, so as to protect the key components of the chip package structure from being damaged, but the excessively thick package cover 14 may cause the chip package structure to have poor heat dissipation capability.

Based on this, this application discloses a encapsulation lid shell structure to through set up the microchannel at encapsulation lid shell inside, dispel the heat through the coolant of microchannel inside flow, improve encapsulation lid shell and chip package structure's heat-sinking capability.

As an alternative implementation of the disclosure, an embodiment of the present application discloses a package cover shell for packaging a die. As shown in fig. 2 and fig. 3, fig. 2 is a schematic top view of a package cover case disclosed in an embodiment of the present invention, and fig. 3 is a schematic cross-sectional view of the package cover case shown in fig. 2 along a cutting line AA', the package cover case 20 includes micro channels 21, the micro channels 21 are located inside the package cover case 20, and the micro channels 21 are used for dissipating heat of the package cover case 20 and the bare chips packaged therein by a coolant flowing inside the package cover case 21. The coolant may include liquid such as water or alcohol, or gas such as ammonia gas or sulfur dioxide. Gases such as ammonia gas and sulfur dioxide are generally used as refrigerants for refrigeration equipment such as air conditioners.

In the embodiment of the present application, the inside of the package cover 20 may include one micro flow channel 21, or may include a plurality of micro flow channels 21. In the examples and drawings of the present application, only one micro flow channel 21 is described as an example, and the present invention is not limited thereto. In some embodiments, the micro flow channels 21 may be arranged in parallel or in a cross manner according to actual requirements, and will not be described herein.

As shown in fig. 3, the cover casing 20 at least comprises a plate-shaped structure, the micro flow channel 21 is at least located inside the plate-shaped structure, and the micro flow channel 21 is connected with the outside of the cover casing 20 through the inlet 210 and the outlet 211, so as to package components such as a motor and a mechanical pump outside the cover casing 20, and the coolant is injected into the micro flow channel 21 through the inlet 210, so that the coolant flows inside the micro flow channel 21 and takes away heat of the cover casing 20 and the bare chips, etc., and then flows out of the micro flow channel 21 through the outlet 211, thereby dissipating heat of the cover casing 20 and the bare chips, etc.

In some embodiments of the present application, the fluidic channels 21 at least partially cover the die to allow for efficient heat dissipation from the die that generates more heat. In some embodiments, as shown in fig. 2, the micro flow channel 21 may partially cover the die 22, and in other embodiments, as shown in fig. 4, fig. 4 is a schematic top view structure of another package cover disclosed in the embodiments of the present application, the micro flow channel 21 may not only completely cover the die 22, but also cover a region around the die 22, so as to achieve a better heat dissipation effect. It should be noted that the die 22 is a dashed box to indicate that the die is disposed in the area, and does not indicate that the area necessarily has the die.

In some embodiments of the present application, as shown in fig. 3, the package cover 20 includes a first surface S1 and a second surface S2 opposite to each other, the die is located on the first surface S1 of the package cover 20, and the inlet 210 and the outlet 211 of the micro channel 21 are located on a side surface, i.e., the second surface S2, of the package cover 20 away from the die, so as to prevent the coolant in the micro channel 21 from corroding the connection circuit and the like of the die and affecting the normal operation of the die.

Of course, the present application is not limited thereto, and in other embodiments, as shown in fig. 5, fig. 5 is a schematic cross-sectional view of the package cover case shown in fig. 4 along a cutting line BB', the inlet 210 and the outlet 211 of the micro flow channel 21 may be respectively located on the left and right sides of the package cover case 20. Of course, in other embodiments, the inlet 210 and the outlet 211 of the micro flow channel 21 may be both located on the left side or the right side of the package cover 20, and will not be described herein.

In some embodiments of the present application, the micro channels 21 are arranged in a predetermined pattern, so that the micro channels 21 uniformly cover the die, and uniform heat dissipation of the die is achieved. As shown in fig. 6, fig. 6 is a schematic structural diagram of a micro flow channel disclosed in an embodiment of the present invention, the micro flow channel 21 includes a plurality of first flow channels 212 and a plurality of second flow channels 213, the first flow channels 212 extend along a first direction Y, the second flow channels 213 extend along a second direction X, the first direction Y intersects with the second direction X, and the plurality of first flow channels 212 are sequentially arranged along the second direction X, and the second flow channels 212 are located between two adjacent first flow channels 212, such that the two adjacent first flow channels 212 are connected end to form a zigzag micro flow channel.

Of course, the present application is not limited thereto, and in other embodiments, as shown in fig. 7, fig. 7 is a schematic structural diagram of another micro flow channel disclosed in the embodiments of the present application, and the plurality of first flow channels 212 and the plurality of second flow channels 213 form a zigzag micro flow channel. In other embodiments, the micro flow channel 21 may be a micro flow channel with other shapes, which will not be described herein.

In some embodiments of the present application, in order to reduce the cost of the package cover 20 while ensuring that the package cover 20 is resistant to warpage, the thickness of the package cover 20 covering only a portion of the die area is adjusted. As shown in fig. 8 and 9, fig. 8 is a schematic bottom view of another package cover disclosed in an embodiment of the present application, and fig. 9 is a schematic cross-sectional view of the package cover shown in fig. 8 along a cutting line CC', where the package cover 20 includes a first portion 201 and a second portion 202, and the second portion 202 is located at a periphery of the first portion 201. Further, the thickness of the first portion 201 is greater than the thickness of the second portion 202, and as shown in fig. 9, the difference in thickness between the first portion 201 and the second portion 202 is D. Wherein the first portion 201 is for fixed connection with the die.

During the process of packaging the die, the die is heated to electrically connect the die to the package substrate through the melted solder balls, but the package structure is warped due to the mismatch of the thermal expansion coefficients between the package substrate and the die. By making the thickness of the first portion 201 greater than that of the second portion 202, the first portion 201 with a greater thickness and a heavier weight can resist the warpage of the die, protect the die from damage, reduce the probability of package structure failure, reduce the weight of the package cover 20 by the second portion 202 with a smaller thickness, and reduce the process risks such as solder joint collapse and bridging caused by the excessive weight of the package cover 20 during the packaging process.

In some embodiments, as shown in fig. 9, the side surfaces of the first portion 201 and the second portion 202 facing away from the die are coplanar, and the side surfaces of the first portion 201 and the second portion 202 facing toward the die are at different heights, so that the thickness of the first portion 201 is greater than that of the second portion 202. However, the present application is not limited thereto, and in other embodiments, as shown in fig. 10, fig. 10 is a schematic cross-sectional view of another package cover disclosed in the embodiments of the present application, a side surface of the first portion 201 and a side surface of the second portion 202 close to the die are coplanar, and heights of the side surfaces of the first portion 201 and the second portion 202 facing away from the die are different, so that a thickness of the first portion 201 is greater than a thickness of the second portion 202.

In some embodiments, the first portion 201 is located in a middle region of the encapsulating cover 20 and the second portion 202 is located in a peripheral edge region of the encapsulating cover 20. Of course, the present application is not limited thereto, and in other embodiments, the first portion 201 may be located at an edge region of the package cover 20, but it should be understood that the location of the first portion 201 corresponds to the location of the die, or the location of the first portion 201 is determined by the location of the die.

In some embodiments, as shown in fig. 9, the fluidic channel 21 is at least partially located inside the first portion 201. Since the thickness of the first portion 201 is large, the flow channel aperture of the micro flow channel 21 inside the first portion 201 can be large or the flow channel length can be large, and the heat dissipation capability of the micro flow channel 21 can be further improved.

In some embodiments of the present application, as shown in fig. 8 and fig. 9, the package cover 20 has a package retaining wall 203 around the package cover, and the package retaining wall 203 is used for being fixedly connected to the package substrate of the bare chip, so that the package cover 20 and the package substrate enclose an enclosed space for accommodating the bare chip. The thickness of the retaining wall 203 is greater than or equal to the thickness of the first portion 201. Of course, the present application is not limited thereto, and in other embodiments, the package cover 20 may also have a flat plate-like structure, and the space between the package cover and the package substrate 12 may be sealed by package glue to form a sealed space for accommodating the die.

In some embodiments, as shown in fig. 11 and 12, fig. 11 is a schematic bottom view of another package cover case disclosed in the embodiments of the present application, fig. 12 is a schematic cross-sectional view of the package cover case shown in fig. 11 along a cutting line DD', and a side surface of the package retaining wall 203 facing the package substrate has a stiffener 204, where the stiffener 204 may also be referred to as a rib. The stiffener 204 is fixedly connected to the package substrate to resist warpage of the package substrate due to an over-size via the stiffener 204. The stiffener 205 may be fixedly connected to the package substrate 21 by an adhesive 204.

In some embodiments, as shown in fig. 11, the stiffener 204 extends along the long side direction of the package cover 20, and two stiffeners 204 are respectively located at two sides of the first portion 201 to support the second portion 202 with smaller thickness against the warpage of the package substrate caused by over-sizing.

In some embodiments of the present application, as shown in fig. 13 and 14, fig. 13 is a schematic bottom view of another package cover shell disclosed in the embodiments of the present application, and fig. 14 is a schematic cross-sectional view of the package cover shell shown in fig. 13 along a cutting line EE', and the package cover shell 20 includes a first surface S1, where the first surface S1 is used for fixedly connecting with a die, or the first surface S1 is a surface fixedly connected with the die. The first surface S1 has a plurality of micro-grooves 205, and the micro-grooves 205 are used for accommodating a connection material between the first surface S1 and the die.

Based on this, by providing the plurality of micro grooves 205 on the first surface S1, not only the contact area of the connection material with the first surface S1 and the die can be increased, but also the connection material can be prevented from flowing excessively, so that the connection effect between the die and the package cover 20 can be enhanced.

In some embodiments, as shown in fig. 13, the micro grooves 205 are stripe grooves, and the plurality of micro grooves 205 are arranged in parallel, although the present disclosure is not limited thereto, in other embodiments, the plurality of micro grooves 205 may also be square or circular grooves arranged in an array, and the details are not repeated herein.

In some embodiments, the connection material between the first surface S1 and the die comprises a metal solder material, such as metallic indium. Based on this, by providing the plurality of micro grooves 205 on the first surface S1, the heat dissipation effect between the die and the package cover can be enhanced.

In some embodiments, as shown in fig. 15, fig. 15 is a schematic bottom view of another package cover disclosed in the embodiments of the present application, and the first surface S1 may be a surface of the first portion 201 to enhance the connection effect and the heat dissipation effect between the first portion 201 and the die while resisting the warpage of the die by the first portion 201 with a larger thickness and reducing the weight of the package cover 20 by the second portion 202 with a smaller thickness.

In some embodiments of the present application, as shown in fig. 16 and 17, fig. 16 is a schematic top view of another package cover shell disclosed in the embodiments of the present application, fig. 17 is a schematic cross-sectional view of the package cover shell shown in fig. 16 along a cutting line FF', the package cover shell 20 has a vent 206, the vent 206 is located at the periphery of the micro flow channel 21, and the vent 206 is used for communicating the enclosed space where the bare chip is located with the outside to remove volatile gases and the like generated by the flux when the bare chip is soldered to the package substrate.

In some embodiments, as shown in fig. 18, fig. 18 is a schematic cross-sectional view of another package cover disclosed in the embodiments of the present application, and the vent 206 is located on the second portion 202 so as to prevent the vent 206 from affecting the normal operation of the first portion 201 and the die.

As another optional implementation of the disclosure, an embodiment of the present application discloses a chip packaging structure, which may also be referred to as a chip, where the chip includes a processor chip, a server chip, and the like. The chip packaging structure comprises the packaging cover shell disclosed by any embodiment.

As shown in fig. 19, fig. 19 is a schematic cross-sectional structure diagram of a chip package structure disclosed in an embodiment of the present application, where the chip package structure includes a package cover 20, a die 22, and a package substrate 23. Wherein the die 22 is located between the package cover 20 and the package substrate 23, the die 22 is fixedly connected to the package cover 20 through the solder material 212, and the die 22 is electrically connected to the package substrate 23 through the solder balls 220.

And, there is the filling glue 213 between the solder ball 220 and the package substrate 23, so as to protect the solder ball 220 by the filling glue 213. In addition, the package walls around the package cover 20 are fixedly connected to the package substrate 23 by the adhesive 214, so that the package cover 20 and the package substrate 23 enclose an enclosed space for accommodating the die 22.

In some embodiments, as shown in fig. 20, fig. 20 is a schematic cross-sectional structural diagram of a chip package structure disclosed in an embodiment of the present application, and the package substrate 23 is further provided with a passive device 24, where the passive device 24 includes a decoupling capacitor, and the decoupling capacitor is used to reduce noise influence on the die 22 from other devices in the circuit.

In some embodiments, as shown in fig. 21, fig. 21 is a schematic cross-sectional view of a chip package structure disclosed in the embodiments of the present application, a die 22 is located between a first portion 201 of a package cover 20 and a package substrate 23 to protect the die from damage by the first portion 201 with a larger thickness and a heavier weight against warpage of the die, and a second portion 202 with a smaller thickness reduces the weight of the package cover 20 to reduce process risks such as solder joint collapse and bridging caused by an excessive weight of the package cover 20 during a BGA package process.

In some embodiments, the package lid 20 is a metal lid, and the package lid 20 is fixedly connected to the die 22 by a connection material 212, wherein the connection material 212 includes silicone grease or a solder material, and the solder material includes indium metal. Based on this, a heat dissipation channel between the die 22 and the package cover 20 can be established through the metal connection material 212, so that heat dissipation of the die 22 can be better achieved.

In some embodiments, the material of the package lid shell 20 includes a metal such as copper or a copper alloy to further inhibit warpage of the die 22 by the metallic package lid shell 20. Moreover, the surface of the package cover case 20 is plated with nickel or gold to achieve good infiltration of indium and reliable welding effect.

As another alternative implementation of the disclosure, an embodiment of the present application discloses an electronic device, which includes a chip package structure disclosed in any of the above embodiments. The electronic device can be a smart phone, a tablet computer, a digital camera, a server and the like.

All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above examples only express several embodiments of the present specification, and the description thereof is specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present description, which falls within the scope of protection of the present description. Therefore, the protection scope of the patent of the specification shall be subject to the appended claims.

Claims (10)

1. A package cover shell is used for packaging a bare chip and is characterized by comprising a micro-channel, wherein the micro-channel is positioned inside the package cover shell and used for cooling the package cover shell and the bare chip through a coolant flowing inside the micro-channel.

2. The package cover shell of claim 1, wherein the die is located on a side surface of the package cover shell, and the micro fluidic channel at least partially covers the die.

3. The package cover case of claim 2, wherein the inlet and outlet of the fluidic channel are located on a side of the package cover case facing away from the die.

4. The package cover case of claim 1, wherein the micro flow channels comprise a plurality of first flow channels and a plurality of second flow channels;

the first flow channel extends along a first direction, the second flow channel extends along a second direction, and the first direction and the second direction are intersected; the plurality of first flow channels are sequentially arranged along the second direction, and the second flow channels are positioned between two adjacent first flow channels, so that the two adjacent first flow channels are connected end to end.

5. The packaging cover shell of claim 1, wherein the packaging cover shell comprises a first portion and a second portion;

the second portion is located at the periphery of the first portion, the thickness of the first portion is larger than that of the second portion, the first portion is used for being fixedly connected with the bare chip, and the micro-channel is located at least partially inside the first portion.

6. The package cover shell of claim 1, wherein the package cover shell comprises a first surface for fixed connection with the die;

the first surface has a plurality of micro-grooves for receiving a connecting material between the first surface and the die.

7. The cover casing assembly as claimed in claim 1, wherein the cover casing assembly has a plurality of walls around the cover casing assembly; the packaging retaining wall is used for being fixedly connected with a packaging substrate of the bare chip, so that the packaging cover shell and the packaging substrate enclose a closed space for containing the bare chip;

and the surface of one side of the packaging retaining wall facing the packaging substrate is provided with reinforcing ribs or fins.

8. The cover packaging shell according to claim 1, wherein the cover packaging shell has vents at the periphery of the micro flow channel, the vents communicating the enclosed space where the bare chip is located with the outside.

9. A chip package structure, comprising the package cover shell according to any one of claims 1 to 8.

10. An electronic device comprising the chip packaging structure of claim 9.

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