CN219435859U - Chip packaging structure and electronic equipment - Google Patents

Abstract

The application discloses chip packaging structure and electronic equipment, chip packaging structure includes the encapsulation base plate, fix the encapsulation lid shell and a plurality of bare chip in encapsulation base plate one side, encapsulation lid shell includes the apron and be located apron peripheral lateral wall, apron and lateral wall enclose into an accommodation space with encapsulation base plate, a plurality of bare chip are located accommodation space, and a plurality of bare chip are connected with encapsulation base plate electricity respectively, the apron includes a plurality of first board areas, second board area and third board area, a plurality of first board areas and a plurality of bare chip are fixed connection respectively, the second board area is located between the adjacent first board area, first board area and second board area are surrounded to the third board area, the thickness of at least second board area is greater than the thickness of third board area, thereby can strengthen the warpage suppression effect of encapsulation lid shell through the thickness of second board area between the increase adjacent bare chip, and then can furthest restrain the warpage of chip packaging structure that has a plurality of bare chip, avoid chip packaging structure to take place solder joint and bridge scheduling problem because of warpage.

Description

Chip packaging structure and electronic equipment

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a chip packaging structure and electronic equipment.

Background

A DIE, also called a DIE or DIE, is a fully functional chip structure formed through circuit design and wafer fabrication processes. In order to prevent the die from being damaged by the outside, a packaging material or the like is generally used to package the die to form a chip packaging structure. However, the chip package structure having a plurality of dies packaged therein has a problem of warpage, which affects the performance of the chip package structure.

Disclosure of Invention

The application discloses a chip packaging structure and electronic equipment to solve the warpage problem of the chip packaging structure packaged with a plurality of bare chips.

In a first aspect, the application discloses a chip packaging structure, which comprises a packaging substrate, a packaging cover shell fixed on one side of the packaging substrate, and a plurality of bare chips; the packaging cover shell comprises a cover plate and side walls positioned on the periphery of the cover plate, an accommodating space is defined by the cover plate, the side walls and the packaging substrate, the bare chips are positioned in the accommodating space, and the bare chips are electrically connected with the packaging substrate respectively; the cover plate comprises a plurality of first plate areas, second plate areas and third plate areas, wherein the first plate areas are fixedly connected with the bare chips respectively, the second plate areas are located between the adjacent first plate areas, the third plate areas surround the first plate areas and the second plate areas, and the thickness of at least the second plate areas is larger than that of the third plate areas. Based on the above, the warping inhibition effect of the packaging cover shell can be enhanced by increasing the thickness of the second board area between the adjacent bare chips, so that the warping of the chip packaging structure with a plurality of bare chips can be inhibited to the greatest extent, and the problems of welding spot collapse, bridging and the like of the chip packaging structure caused by the warping are avoided.

In some alternative examples, a side of the second board region facing the package substrate has a first rib, and the first rib is located between any two adjacent dies. Based on this, the thickness of the second plate region may be increased by adding the first rib to the side of the second plate region facing the package substrate.

In some alternative examples, the material of the first rib is the same as the material of the cover plate; the thickness of the first rib is equal to that of the accommodating space between the cover plate and the packaging substrate, and the first rib is fixedly connected with the packaging substrate. Based on this, the warp suppressing effect of the first rib can be enhanced, and further the warp suppressing effect of the package cover case can be enhanced.

In some alternative examples, the cover plate further includes a fourth plate region located between the third plate region and the first and second plate regions, or between the third plate region and the sidewall; the thickness of the fourth plate area is greater than the thickness of the third plate area. Based on the above, the warping inhibition effect of the packaging cover shell can be further enhanced by increasing the thicknesses of the second plate area and the fourth plate area at the same time, so that the warping of the chip packaging structure with a plurality of bare chips can be inhibited to the greatest extent, and the problems of welding spot collapse, bridging and the like of the chip packaging structure due to the warping are avoided.

In some alternative examples, a side of the fourth plate region facing the package substrate has a second rib, and the second rib surrounds the first plate region and the second plate region. Based on this, the thickness of the fourth plate region may be increased by adding the second ribs on the side of the fourth plate region facing the package substrate.

In some alternative examples, the thickness of the first plate region is greater than the thickness of the third plate region. Based on the method, the warping of the chip packaging structure can be further resisted through the first plate area with larger thickness and heavier weight, the bare chip is protected from being damaged, the failure probability of the chip packaging structure is reduced, the weight of the whole packaging cover shell is reduced through the third plate area with smaller thickness and lighter weight, and the risk of welding spot collapse, bridging among welding spots and other process problems caused by overlarge weight of the packaging cover shell in the packaging process is reduced.

In some alternative examples, a side surface of the first plate region facing the package substrate protrudes from a side surface of the third plate region facing the package substrate.

In some optional examples, the chip packaging structure further includes a stiffener, where the stiffener is located around the packaging substrate, and the stiffener is at least located at a side of the packaging substrate facing away from the packaging cover shell. Based on the above, at least the package cover shells and the reinforcing ribs which are respectively positioned at the two opposite sides of the package substrate can apply stress to the package substrate from the two opposite sides, namely, the package cover shells can apply stress to the package substrate along the Z 'direction, and the reinforcing ribs can apply stress to the package substrate along the Z direction, so that the warping of the chip package structure in the Z and Z' directions can be restrained to the greatest extent, and the problems of welding spot collapse, bridging and the like of the chip package structure due to the warping are avoided.

In some alternative examples, the stiffener extends from a side of the encapsulation substrate facing away from the encapsulation cover to a side of the encapsulation substrate adjacent to the encapsulation cover. Based on the structure, the warpage of the packaging substrate can be further restrained by the reinforcing ribs respectively positioned at the three sides of the packaging substrate, so that the warpage of the chip packaging structure can be restrained to the greatest extent, and the problems of welding spot collapse, bridging and the like of the chip packaging structure due to the warpage are avoided.

In a second aspect, the present application discloses an electronic device comprising a chip package structure as defined in any one of the preceding claims. Based on the method, the warping of the chip packaging structure can be restrained to the greatest extent, the problems of welding spot collapse, bridging and the like of the chip packaging structure caused by the warping are avoided, and the using effect of the electronic equipment is ensured.

Drawings

In order to more clearly describe the technical solutions in the embodiments or the background of the present application, the following description will describe the drawings that are required to be used in the embodiments or the background of the present application.

Fig. 1 is a schematic cross-sectional structure of a chip package structure disclosed in the present application;

fig. 2 is a schematic top view of a chip package structure according to an embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional view of the chip package structure shown in fig. 2 along a cutting line AA';

FIG. 4 is a schematic top view of another chip package structure according to an embodiment of the disclosure;

fig. 5 is a schematic cross-sectional structure of the chip package structure shown in fig. 4 along a cutting line BB';

FIG. 6 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

FIG. 7 is a schematic top view of another chip package structure according to an embodiment of the disclosure;

fig. 8 is a schematic cross-sectional view of the chip package structure shown in fig. 7 along a cutting line CC';

FIG. 9 is a schematic top view of another chip package structure according to an embodiment of the disclosure;

fig. 10 is a schematic cross-sectional view of the chip package structure shown in fig. 9 along a cutting line DD';

FIG. 11 is a schematic top view of another chip package structure according to an embodiment of the disclosure;

FIG. 12 is a schematic top view of another chip package structure according to an embodiment of the disclosure;

FIG. 13 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

FIG. 14 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

FIG. 15 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

FIG. 16 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

FIG. 17 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure;

fig. 18 is a schematic cross-sectional view of another chip package structure according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Most of the current Chip package structures are Flip Chip (Flip Chip) structures, which are leadless structures, as shown in fig. 1, fig. 1 is a schematic cross-sectional structure of a Chip package structure disclosed in the present application, and the Chip package structure includes a die 10, a package substrate 11 and a package cover 12. The package cover 12 and the package substrate 11 enclose an enclosed space, and the enclosed space is used for accommodating the die 10, so as to provide a certain mechanical protection for the die 10.

As shown in fig. 1, the package cover 12 is fixedly connected with the package substrate 11 through the adhesive 13, and the bare chip 10 is fixedly connected with the package substrate 11 through the filling adhesive 14, however, because the thermal expansion coefficients of the package substrate 11, the package cover 12 and the adhesive 13 are not matched, the thermal expansion coefficients of the package substrate 11, the bare chip 10 and the filling adhesive 14 are also not matched, and therefore, when the surface mounting technology is adopted to heat the molten solder balls 110, when the chip package structure is fixedly connected with the integrated circuit board through the molten solder balls 110, the temperature change can lead to the package substrate 11 to warp, and further the chip package structure has the problems of solder joint collapse where the solder balls 110 are located, bridging between adjacent solder joints and the like. Also, the warpage problem is more serious for the chip package structure in which a plurality of dies 10 are packaged.

Based on this, this application discloses a chip packaging structure, through the thickness of increase encapsulation lid shell between a plurality of dies, increase the thickness of second board district promptly, the warpage suppression effect of reinforcing encapsulation lid shell to the furthest suppresses the warpage of chip packaging structure that has a plurality of dies, avoids chip packaging structure to appear solder joint subsidence and bridging scheduling problem because of the warpage.

As an optional implementation of the disclosure, an embodiment of the application discloses a chip packaging structure, as shown in fig. 2 and 3, the chip packaging structure includes a packaging substrate 11, a packaging cover shell 12 fixed on one side of the packaging substrate 11, and a plurality of dies 10, where the packaging cover shell 12 includes a cover plate 120 and a sidewall 121 located around the cover plate 120, the cover plate 120 and the sidewall 121 enclose an accommodating space with the packaging substrate 11, the dies 10 are located in the accommodating space, and the dies 10 are electrically connected with the packaging substrate 11 respectively.

Also, as shown in fig. 3, the cover plate 120 includes a plurality of first plate regions 120a, a second plate region 120b, and a third plate region 120c, the plurality of first plate regions 120a are fixedly connected with the plurality of dies 10, respectively, the second plate region 120b is located between adjacent first plate regions 120a, the third plate region 120c surrounds the first plate region 120a and the second plate region 120b, and at least the thickness of the second plate region 120b is greater than the thickness of the third plate region 120 c.

Based on this, the warpage-inhibiting effect of the package cover 12 can be enhanced by increasing the thickness of the second board region 120b between the adjacent dies 10, and thus the warpage of the chip package structure having a plurality of dies 10 can be inhibited to the maximum extent, avoiding the problems of solder joint collapse, bridging, and the like of the chip package structure due to warpage.

In some embodiments of the present application, as shown in fig. 4 and 5, a side of the second board area 120b facing the package substrate 11 has a first rib 13, and the first rib 13 is located between any two adjacent dies 10. That is, in some embodiments of the present application, the thickness of the second plate region 120b may be increased by adding the first ribs 13 to the side of the second plate region 120b facing the package substrate 11. Wherein the first ribs 13 may be adhered to the side of the second plate area 120b facing the package substrate 11 using an adhesive or the like.

Of course, the present application is not limited thereto, and in other embodiments, the cover plate 120 having at least the second plate region 120b with a thickness greater than that of the third plate region 120c may be formed in an integrally molded manner. In other embodiments, the thickness of the third plate region 120c may be reduced by etching, so that at least the thickness of the second plate region 120b is greater than the thickness of the third plate region 120c, which will not be described herein.

In some embodiments of the present application, the material of the encapsulation cover 12 includes a metal material including copper or copper alloy to further suppress warpage of the die 10 by the metal cover. And the surface of the metal cover shell can be plated with nickel or gold to realize good infiltration of metal welding materials such as indium and achieve reliable welding effect.

In some embodiments, the material of the first rib 13 is the same as that of the cover plate 120 or the encapsulation cover 12, so as to enhance the warpage-inhibiting effect of the first rib 13 by enhancing the connection effect of the first rib 13 and the encapsulation cover 12, thereby enhancing the warpage-inhibiting effect of the encapsulation cover 12. Of course, the present application is not limited thereto, and in other embodiments, the material of the first rib 13 and the material of the packaging cover 12 may be different, which is not described herein.

In some embodiments, the connection material between the package cover 12 and the die 10 comprises a metal solder material, wherein the metal solder material in turn comprises metallic indium. In other embodiments, the connection material may further include silicone grease material, etc., which will not be described herein. Based on this, a heat dissipation channel between the die 10 and the package cover 12 can be established by a metal solder material with good heat conduction performance, so that heat dissipation of the die 10 can be better realized.

In some embodiments of the present application, as shown in fig. 5, the thickness of the first rib 13 is equal to the thickness of the accommodating space between the cover plate 120 and the package substrate 11, and the first rib 13 is fixedly connected with the package substrate 11, so as to further enhance the buckling suppressing effect of the first rib 13 and the package cover 12. Of course, the present application is not limited thereto, and in other embodiments, as shown in fig. 6, the first rib 13 and the package substrate 11 may not be fixedly connected, and/or the thickness of the first rib 13 may be smaller than the thickness of the accommodating space between the cover plate 120 and the package substrate 11.

In some embodiments of the present application, as shown in fig. 7 and 8, the cover plate 120 further includes a fourth plate region 120d, the fourth plate region 120d is located between the third plate region 120c and the first and second plate regions 120a and 120b, and the thickness of the fourth plate region 120d is greater than the thickness of the third plate region 120 c. Alternatively, in other embodiments, as shown in fig. 9 and 10, the fourth plate region 120d may also be located between the third plate region 120c and the sidewall 121, and the thickness of the fourth plate region 120d is greater than the thickness of the third plate region 120 c.

Based on this, the warpage-inhibiting effect of the package cover 12 can be further enhanced by increasing the thicknesses of the second board region 120b and the fourth board region 120d at the same time, and thus the warpage of the chip package structure having the plurality of dies 10 can be maximally inhibited, and the problems of solder joint collapse, bridging, and the like of the chip package structure due to warpage can be avoided.

In some embodiments of the present application, as shown in fig. 11 and 12, a side of the fourth board region 120d facing the package substrate 11 has a second rib 14, and the second rib 14 surrounds the first board region 120a and the second board region 120b. Based on this, the thickness of the fourth plate region 120d may be increased by adding the second ribs 14 to the side of the fourth plate region 120d facing the package substrate 11. The second ribs 14 may be adhered to the side of the fourth plate area 120d facing the package substrate 11 using an adhesive or the like.

Of course, the present application is not limited thereto, and in other embodiments, the cover plate 120 having the fourth plate region 120d with a thickness greater than that of the third plate region 120c may be formed in an integrally molded manner. In other embodiments, the thickness of the third plate region 120c may be reduced by etching, so that the thickness of the second plate region 120b and the fourth plate region 120d is greater than the thickness of the third plate region 120c, which is not described herein.

In addition, in some embodiments, the material of the second rib 14 may be the same as that of the cover plate 120 or the encapsulation cover 12, so as to enhance the buckling suppressing effect of the second rib 14 by enhancing the connection effect of the second rib 14 and the encapsulation cover 12, and thus enhance the buckling suppressing effect of the encapsulation cover 12. Of course, the present application is not limited thereto, and in other embodiments, the material of the second rib 14 may be different from the material of the cover plate 120 or the encapsulating cover 12, which is not described herein.

It should be understood that the four dies 10 are shown in the drawings of the embodiment of the present application, but the present application is not limited thereto. The shapes of the first ribs 13 and the second ribs 14 may be determined by the number and layout of the die 10, and will not be described herein.

In other embodiments of the present application, the thickness of the first plate area 120a may be greater than the thickness of the third plate area 120 c. Based on this, the warpage of the chip package structure can be further resisted by the first plate region 120a with larger thickness and heavier weight, the bare chip 10 is protected from damage, the probability of failure of the chip package structure is reduced, the weight of the whole package cover 12 is reduced by the third plate region 120c with smaller thickness and lighter weight, and the risk of technical problems such as welding spot collapse and bridging between welding spots caused by overlarge weight of the package cover 12 in the packaging process is reduced.

As shown in fig. 13, a side surface of the first plate region 120a facing away from the package substrate 11 is coplanar with a side surface of the second plate region 120b and the third plate region 120c facing away from the package substrate 11, and a side surface of the first plate region 120a facing toward the package substrate 11 protrudes from a side surface of the third plate region 120c facing toward the package substrate 11. Of course, the present application is not limited thereto, and in other embodiments, as shown in fig. 14, a side surface of the first board 120a facing the package substrate 11 is coplanar with a side surface of the third board 120c facing the package substrate 11, and a side surface of the first board 120a facing away from the package substrate 11 protrudes from a side surface of the third board 120c facing away from the package substrate 11.

In some embodiments of the present application, as shown in fig. 15, the chip packaging structure further includes a stiffener 15, where the stiffener 15 is located around the packaging substrate 11, and the stiffener 15 is at least located on a side of the packaging substrate 11 facing away from the packaging cover 12.

In some embodiments of the present application, as shown in fig. 15, the stiffener 15 is only located on the side of the package substrate 11 facing away from the package cover 12. Since the package cover 12 and the stiffener 15 are respectively located at two opposite sides of the package substrate 11, the package cover 12 and the stiffener 15 can apply stress to the package substrate 11 from two opposite sides, that is, the package cover 12 can apply stress to the package substrate 11 along the Z ' direction, and the stiffener 15 can apply stress to the package substrate 11 along the Z ' direction, so that warpage of the chip package structure in the Z and Z ' directions can be suppressed to the greatest extent, and problems such as solder joint collapse and bridging of the chip package structure due to warpage are avoided.

However, the present application is not limited thereto, and in other embodiments, the reinforcing ribs 15 may be located on a side of the package substrate 11 facing away from the package cover 12 and a side of the package substrate 11 near the package cover 12. In some embodiments, as shown in fig. 16, the reinforcing bars 15 may include a first reinforcing bar 151 and a second reinforcing bar 152. The first reinforcing ribs 151 are located around the package substrate 11, and the first reinforcing ribs 151 are located on one side of the package substrate 11 facing away from the package cover 12. The second reinforcing ribs 152 are located around the package substrate 11, and the second reinforcing ribs 152 are located on one side of the package substrate 11 close to the package cover 12. Alternatively, in other embodiments, as shown in fig. 17, the second reinforcing ribs 152 may be further located at a side of the package substrate 11 and connected to the first reinforcing ribs 151.

Based on this, stress can be applied to the package substrate 11 from both sides by the first stiffener 151 and the second stiffener 152 respectively located at both sides of the package substrate 11, and thus warpage of the package substrate 11 can be suppressed from both sides, and warpage of the chip package structure can be suppressed to the greatest extent, and problems such as solder joint collapse and bridging due to warpage of the chip package structure can be avoided.

In other embodiments, the stiffener 15 extends from a side of the package substrate 11 facing away from the package cover 12 to a side of the package substrate 11 adjacent to the package cover 12. As shown in fig. 18, the stiffener 15 may further include a first stiffener 151, a second stiffener 152, and a third stiffener 153, where the first stiffener 151 is located around the package substrate 11, and the first stiffener 151 is located on a side surface of the package substrate 11 facing away from the package cover 12, the second stiffener 152 is located around the package substrate 11, and the second stiffener 152 is located on a side surface of the package substrate 11 near the package cover 12, the third stiffener 153 is located on a peripheral side surface of the package substrate 11, and the third stiffener 153 connects the first stiffener 151 and the second stiffener 152.

Based on this, the warpage of the package substrate 11 can be further suppressed by the first stiffener 151, the second stiffener 152, and the third stiffener 153 respectively located at the three sides of the package substrate 11, so that the warpage of the chip package structure can be suppressed to the greatest extent, and the problems of solder joint collapse, bridging, and the like of the chip package structure due to the warpage can be avoided. It is understood that the first reinforcing rib 151, the second reinforcing rib 152, and the third reinforcing rib 153 may be continuously disposed or discontinuously disposed around the package substrate 11.

In this embodiment, the side of the package substrate 11 facing away from the package cover 12 has solder balls 110, and the solder balls 110 are used to electrically connect the package substrate 11 with the integrated circuit board, so that the die 10 is electrically connected with other devices on the integrated circuit board. In some embodiments, as shown in fig. 15, a thickness D1 of the stiffener 15 on a side of the package substrate 11 facing away from the package cover 12 is smaller than a thickness D2 of the solder balls 110, and a width L1 of the stiffener 15 on a side of the package substrate 11 facing away from the package cover 12 is smaller than a distance L2 between the solder balls 110 and a side of the package substrate 11, so that the stiffener 15 does not affect the mounting of the package substrate 11 and the integrated circuit board.

Optionally, a distance L3 between the solder balls 110 and the stiffener 15 on a side of the package substrate 11 facing away from the package cover 12 is greater than 0.5mm, so as to ensure convenience in mounting the package substrate 11 and the integrated circuit board. Optionally, the thickness D1 of the reinforcing rib 15 on the side of the package substrate 11 facing away from the package cover 12 ranges from 0.2mm to 0.3mm; the width L1 of the reinforcing rib 15 on the side of the package substrate 11 facing away from the package cover 12 ranges from 0.3mm to 0.5mm.

In some embodiments of the present application, the material of the reinforcing rib 15 includes a metal material including a stainless steel material or a copper material, etc., so as to improve the buckling suppressing effect of the reinforcing rib 15 through the metal material having poor ductility. It is understood that the stiffener 15 may be directly formed on the package substrate 11, or may be bonded to the package substrate 11 by an adhesive material or the like.

As another optional implementation of the disclosure, an embodiment of the present application discloses an electronic device, which includes the chip package structure disclosed in any one of the embodiments above. The electronic device may be a smart phone, a tablet computer, a digital camera, a server, etc. Based on the method, the warping of the chip packaging structure can be restrained to the greatest extent, the problems of welding spot collapse, bridging and the like of the chip packaging structure caused by the warping are avoided, and the using effect of the electronic equipment is ensured.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present specification, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the present description, which is within the scope of the present description. Accordingly, the protection scope of the patent should be determined by the appended claims.

Claims (10)

1. The chip packaging structure is characterized by comprising a packaging substrate, a packaging cover shell and a plurality of bare chips, wherein the packaging cover shell is fixed on one side of the packaging substrate;

the packaging cover shell comprises a cover plate and side walls positioned on the periphery of the cover plate, an accommodating space is defined by the cover plate, the side walls and the packaging substrate, the bare chips are positioned in the accommodating space, and the bare chips are electrically connected with the packaging substrate respectively;

the cover plate comprises a plurality of first plate areas, second plate areas and third plate areas, wherein the first plate areas are fixedly connected with the bare chips respectively, the second plate areas are located between the adjacent first plate areas, the third plate areas surround the first plate areas and the second plate areas, and the thickness of at least the second plate areas is larger than that of the third plate areas.

2. The chip package structure of claim 1, wherein a side of the second board area facing the package substrate has a first rib, and wherein the first rib is located between any two adjacent dies.

3. The chip package structure according to claim 2, wherein a material of the first rib is the same as a material of the cover plate; the thickness of the first rib is equal to that of the accommodating space between the cover plate and the packaging substrate, and the first rib is fixedly connected with the packaging substrate.

4. The chip package structure of claim 1, wherein the cover plate further comprises a fourth plate region, the fourth plate region being located between the third plate region and the first and second plate regions, or between the third plate region and the sidewall; the thickness of the fourth plate area is greater than the thickness of the third plate area.

5. The chip package structure according to claim 4, wherein a side of the fourth board region facing the package substrate has a second rib, and the second rib surrounds the first board region and the second board region.

6. The chip package structure of claim 1, wherein a thickness of the first plate region is greater than a thickness of the third plate region.

7. The chip package structure according to claim 6, wherein a side surface of the first plate region facing the package substrate protrudes from a side surface of the third plate region facing the package substrate.

8. The chip package structure of claim 1, further comprising a stiffener, wherein the stiffener is located around the package substrate, and the stiffener is located at least on a side of the package substrate facing away from the package cover.

9. The chip package structure of claim 8, wherein the stiffener extends from a side of the package substrate facing away from the package cover to a side of the package substrate adjacent to the package cover.

10. An electronic device comprising the chip package structure of any one of claims 1 to 9.