CN219394806U

CN219394806U - Wafer level packaging structure and module, circuit board and electronic equipment thereof

Info

Publication number: CN219394806U
Application number: CN202320115067.4U
Authority: CN
Inventors: 龙建飞; 宁世朝; 刘立筠; 白云芳
Original assignee: Beijing Weijie Chuangxin Precision Measurement Technology Co ltd
Current assignee: Beijing Weijie Chuangxin Precision Measurement Technology Co ltd
Priority date: 2023-01-22
Filing date: 2023-01-22
Publication date: 2023-07-21
Anticipated expiration: 2033-01-22

Abstract

The utility model discloses a wafer level packaging structure, a wafer level packaging module, a circuit board and electronic equipment. The wafer level package structure comprises: the chip body is provided with an electrode surface and a mounting surface opposite to the electrode surface, the mounting surface is provided with solder, a connector is positioned on the electrode surface and surrounds the electrode surface to form a cavity, a plurality of electrodes are positioned on the electrode surface in the cavity, and the connector and the cavity are covered by a sealing cover, so that the sealing cover, the connector and the chip body jointly form a closed cavity, and a wire layer is arranged on the side surface of the chip body to electrically connect the electrode surface of the chip body with the mounting surface. The utility model can effectively solve the problem of air tightness caused by inconsistent heights, can avoid the problem of soldering flux residue, and greatly saves cost while simplifying the process and ensuring the quality.

Description

Wafer level packaging structure and module, circuit board and electronic equipment thereof

Technical Field

The utility model relates to a wafer level packaging structure, and also relates to a module, a circuit board and electronic equipment comprising the wafer level packaging structure, belonging to the technical field of chip packaging.

Background

Acoustic filters can be classified into surface acoustic wave filters (abbreviated as SAW filters) and surface acoustic wave filters (abbreviated as BAW filters) according to their structures, and their basic principles are substantially the same except that there is a difference in the propagation direction of acoustic signals. The basic principle of SAW filters is to convert a radio signal into an acoustic signal by the piezoelectric effect at the input end and to propagate on the surface of a medium, and to convert an acoustic signal into a radio signal by the inverse piezoelectric effect at the output end. The basic principle of BAW filters is the same as SAW filters, except that the acoustic waves of BAW filters propagate vertically. Thus, both require a cavity structure to protect the interdigital transducer (IDT).

With the continuous evolution of microelectronic technology, the demands for chip miniaturization and high integration are becoming more and more urgent, so miniaturization of acoustic filters is becoming particularly important in high-integration modules, such as radio frequency front end modules (RF FEM), circuit boards, or electronic devices.

In the Chinese utility model with the patent number ZL 201721882163.2, an airtight wafer-level packaging structure of a surface acoustic wave device is disclosed, a circle of bonding layer metal is plated on the periphery of a working surface of a functional chip, a circle of bonding layer metal is respectively plated on a position, corresponding to each chip bonding layer metal, on a sealing cover wafer, and the functional chip and the sealing cover wafer are correspondingly combined together through gold-gold bonding or eutectic bonding; an external circuit wiring structure and an external electrode are arranged on the surface of the sealing cover wafer, which faces away from the working surface of the functional chip; external solder balls are manufactured on the outer electrodes; the sealing cover wafer is provided with a via hole so as to electrically connect the working surface circuit of the functional chip with the external solder ball through the via hole, the external electrode and the external solder ball in sequence. The utility model can realize the airtight package of the Wafer Level (WLP) surface acoustic wave device with high chip shear strength, good heat dissipation and controllable internal atmosphere, and has the characteristic of high reliability.

Disclosure of Invention

The first technical problem to be solved by the present utility model is to provide a wafer level package structure.

Another technical problem to be solved by the present utility model is to provide a module including the above wafer level package structure.

Another technical problem to be solved by the present utility model is to provide a circuit board including the above wafer level package structure.

Another technical problem to be solved by the present utility model is to provide an electronic device including the above wafer level package structure.

In order to achieve the above purpose, the present utility model adopts the following technical scheme:

according to a first aspect of an embodiment of the present utility model, there is provided a wafer level package structure, including:

the chip body is provided with an electrode surface and a mounting surface opposite to the electrode surface, the mounting surface is provided with solder,

a connector which is positioned on the electrode surface and surrounds the electrode surface to form a cavity,

a plurality of electrodes located on the electrode faces within the cavity,

a cover covering the connector and the cavity so that the cover, the connector and the chip body together form a closed cavity,

and a wire layer is arranged on the side surface of the chip body, so that the electrode surface of the chip body is electrically connected with the mounting surface.

The side surface is in an inclined surface shape.

Preferably, the electrode surface is further provided with a metal conductive pad, the mounting surface is further provided with a conductive disc, and the conductive wire layer is connected with the conductive pad and the conductive disc.

Wherein preferably said connector adheres said cover and said chip body together.

According to a second aspect of the embodiments of the present utility model, a module including a wafer level package structure is provided, where the wafer level package structure is the aforementioned wafer level package structure.

According to a third aspect of the embodiments of the present utility model, there is provided a circuit board including a wafer level package structure, the wafer level package structure being the aforementioned wafer level package structure.

According to a fourth aspect of the embodiments of the present utility model, there is provided an electronic device including a wafer level package structure, where the wafer level package structure is the foregoing wafer level package structure.

Compared with the prior art, the utility model can effectively solve the problem of air tightness caused by inconsistent heights, can avoid the problem of soldering flux residue, and greatly saves cost while simplifying the process and ensuring the quality.

Drawings

Fig. 1 is a schematic diagram of a wafer level package structure according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of the structure of the conductive wire layer in FIG. 1;

FIG. 3 is a schematic view of the closure of FIG. 1;

FIG. 4 (a) is a schematic illustration of a method of forming an airtight connection of a closure through a connector;

fig. 4 (b) is a second schematic diagram of a method of forming an airtight connection of a closure through a connector.

Detailed Description

The technical contents of the present utility model will be described in detail with reference to the accompanying drawings and specific examples.

As shown in fig. 1 to 3, the wafer level package structure provided in the embodiment of the utility model at least includes a cover 1, an electrode 2 located in a cavity 3, a connector 4, and a chip body 8. The chip body 8 will be described below using a SAW filter as an example. The chip body 8 is made of a wafer material, and has an electrode surface 81, a mounting surface 82 opposed to the electrode surface, and a side surface 83 connecting the electrode surface 81 and the mounting surface 82. A plurality of electrodes (for example, electrodes of an interdigital transducer) 2 and a plurality of metal conductive pads 5 are formed on the electrode surface 81. On the mounting surface 82, a metal conductive pad 7 is formed for connecting with the solder 9.

The sides of the chip body 8 are preferably beveled for reducing thermal stress conduction after die bonding. Since the electrode surface 81 has a larger cross-sectional dimension than the mounting surface 82, the side surface 83 is inclined so as to gradually contract in the chip interior direction from the electrode surface 81 to the mounting surface 82, for example, at a 45-degree slope angle. Since the inclined shape has an angle in the stress transmission direction, the magnitude of the thermal stress generated by heating is decomposed into one component, and thus the thermal stress buffering function is exerted.

As shown in fig. 2, the side surface 83 is provided with a wiring layer 6 to electrically connect the electrode surface and the mounting surface of the chip body. The wire layers are fabricated using re-Routing (RDL) techniques. The re-wiring technology is to change the contact position of the originally designed IC circuit contact position (I/O pad) through the wafer-level metal wiring process and the bump process, so that the chip can be suitable for different packaging forms. The wire layer 6 is connected to the conductive pad 5 and to the conductive pad 7 to electrically connect the conductive pad to the conductive pad. In the subsequent packaging process, the conductive pads 7 are solder-mounted to the corresponding module substrates by a conventional SMT (surface mount) technique or FC (flip chip) process.

As shown in fig. 3, the cap 1 is fixed to the chip body 8 by the ring connector 4. The structural material of the cover 1 includes, but is not limited to, glass silicon wafer (glass wafer), silicon-based wafer (Si wafer), SOI silicon wafer (SOI wafer) or other LiTaO ₃ A substrate; or a copper-clad plate or other hard cover plate, and the purpose of the structure is mainly to form a cavity structure with good air tightness with the filter chip body 8 so as to protect the electrode 2. The cover 1 covers the connector 4 and the cavity 3 such that the cover 1, the connector 4 and the chip body 8 together form a closed cavity 3, thereby providing protection to the electrode 2.

As shown in fig. 1, the connector 4 connects the cover 1 and the chip body 8. The width of the connector 4 is at least 20um to ensure that the adhesive contact area between the connector 4 and the chip body 8 and the cover 1 reaches a predetermined value. The thickness of the connector 4 is typically 10um to 40um to ensure that the cavity 3 is large enough to meet performance requirements (e.g. to meet the cavity requirements of a filter chip).

The connector 4 may be a polymer dry film material that is subsequently heated to attach the cover 1 to the chip body 8. The connector 4 can also be made of other various materials with the function of crosslinking and bonding. The chip body 8 encloses the cavity 3 together with the cover 1 and the connector 4 to accommodate the electrode 2.

Since the ring-shaped connector 4 formed in the same process step is adopted to enclose the electrode 2 of the interdigital transducer in the embodiment of the utility model, and a two-step process is not adopted to form the electrode, the size of the ring-shaped connector 4 can be precisely controlled, the problem of inconsistent heights of connectors around the electrode is avoided, and the air tightness is improved. In addition, by using the rewiring technology, metal wires are formed on the side wall of the chip body to connect the conductive pads in the cavity and the conductive plates on the mounting surface of the chip body, so that the problem of soldering flux residue is avoided. And the side surface of the chip body is designed into an inclined surface shape, so that the thermal stress conduction after the chip is welded is reduced, and the yield and the productivity are improved.

The following describes a method for manufacturing a wafer level package structure according to an embodiment of the present utility model with reference to fig. 2, fig. 3, fig. 4 (a), and fig. 4 (b).

As shown in fig. 2, electrodes and conductive pads are formed on the electrode faces of the chip body, and conductive pads are formed on the mounting face. Meanwhile, an inclined side surface is formed on the chip body through a laser grooving process, and then a wire layer is prepared on the side surface through an electroplating process.

As shown in fig. 3, a connector made of a polymer dry film is laminated on the cover; or other cross-linking adhesive material may be applied to the cover to form the connector.

The chip body is then air-tightly connected to the cover via the connector. Optionally, as shown in fig. 4 (a), the conductive disc on the mounting surface does not need solder, and the subsequent package module integrated product preparation such as singulation, welding, plastic packaging and the like is directly performed. Alternatively, as shown in fig. 4 (b), bump preparation is performed first, and then, package module integrated product preparation such as singulation, welding, plastic packaging and the like is performed subsequently. That is, the conductive interconnection may be performed by ball mounting (solder 9 formation) or bump technology, or the subsequent mounting on the module substrate may be directly performed in the form of LGA pads.

In the plastic packaging process of packaging the wafer-level packaging structure to the substrate, the chip body and the sealing cover welded with the chip body bear main plastic packaging pressure, so that the cavity structure is greatly protected from collapse due to extrusion deformation of the plastic packaging pressure. Meanwhile, the wafer level packaging size can be small, and the thickness can be flexibly controlled, so that the wafer level packaging structure provided by the embodiment of the utility model has remarkable advantages in high-density integrated radio frequency front end module (RF FEM) products, and can be suitable for various RF FEM module products, such as radio frequency module devices of DiFEM, LPAMID and the like.

The utility model also provides a module comprising the wafer-level packaging structure. The module includes the aforementioned wafer level package structure and other chip package structures (e.g., power amplifier chip, low noise amplifier chip), and may be, for example, a radio frequency module.

The utility model also provides a circuit board comprising the wafer-level packaging structure. The circuit board comprises the wafer level packaging structure or the module, and can also comprise various discrete devices and the like.

The utility model also provides electronic equipment comprising the wafer-level packaging structure. The circuit board comprises the wafer level packaging structure or the module. The electronic device may be a wearable electronic device, a smart phone, a personal computer, or the like.

Compared with the prior art, in the wafer level packaging structure provided by the utility model, the chip body and the sealing cover are subjected to film covering and hot pressing to form a cavity, signals are led out from the conductive electrode pad positioned on the electrode surface to the conductive disc positioned on the mounting surface through the side surface wire layer, and then the signals are welded on the module substrate through the packaging process to complete the final product level interconnection. The structure can effectively avoid the problems of soldering flux residue and the like caused by welding in the closed cavity, also avoid the problem of mismatching between the welding convex points in the cavity and the height of the cavity wall, greatly simplify the process flow and improve the product quality.

The wafer level packaging structure, the module, the circuit board and the electronic equipment provided by the utility model are described in detail. Any obvious modifications to the present utility model, without departing from the spirit thereof, would constitute an infringement of the patent rights of the utility model and would take on corresponding legal liabilities.

Claims

1. The wafer level packaging structure is characterized by comprising:

the chip body is provided with an electrode surface and a mounting surface opposite to the electrode surface, the mounting surface is provided with a conductive disk,

a plurality of electrodes located on the electrode faces within the cavity,

2. The wafer level package structure of claim 1, wherein:

the side surface is in an inclined surface shape.

3. The wafer level package structure of claim 2, wherein:

and a metal conductive gasket is further arranged on the electrode surface, and the conducting wire layer is connected with the conductive gasket and the conductive disc.

4. The wafer level package structure of claim 3, wherein:

the connector adheres the cover and the chip body together.

5. The wafer level package structure of claim 3, wherein:

and the conductive disc is provided with solder.

6. A module comprising the wafer level package structure of any one of claims 1-5.

7. A circuit board comprising the wafer level package structure of any one of claims 1-5.

8. An electronic device comprising the wafer level package structure of any one of claims 1-5.