WO2022241623A1

WO2022241623A1 - Chip encapsulation structure, chip encapsulation method, and electronic device

Info

Publication number: WO2022241623A1
Application number: PCT/CN2021/094189
Authority: WO
Inventors: 陈建桦; 林来存; 张珊; 刘国文
Original assignee: 华为技术有限公司
Priority date: 2021-05-17
Filing date: 2021-05-17
Publication date: 2022-11-24
Also published as: CN116803002A

Abstract

A chip encapsulation structure, comprising a substrate, a bare chip mounted upside down on the substrate, at least one conductive bump located between the substrate and the bare chip, and a conductive sealing ring. A functional element is arranged on the surface of the bare chip that faces the substrate. The conductive bump is electrically connected to the bare chip and the substrate. The functional element and the substrate are spaced apart from each other by means of the sealing ring, and the sealing ring surrounds the functional element to form a closed ring shape, so that a closed cavity is formed between the substrate and the bare chip. Further provided in the present application are an electronic device to which the chip encapsulation structure is applied, and a preparation method for the chip encapsulation structure. According to the chip encapsulation structure of the present application, in a space where the conductive bump originally needs to be arranged between the bare chip and the substrate to realize electrical connection between the bare chip and the substrate, the sealing ring in a closed ring shape is arranged, such that the closed cavity is formed between the bare chip and the substrate to avoid damage to the functional element, thereby simplifying the chip encapsulation structure.

Description

Chip packaging structure and chip packaging method, electronic equipment

technical field

The present application relates to a chip packaging structure, a chip packaging method, and an electronic device using the chip packaging structure.

Background technique

There are usually multiple filters in the mobile phone to filter the transmission and reception paths of wireless access methods such as 2G, 3G, 4G and 5G in multiple frequency bands. At the same time, filters also include: Wi-Fi, Bluetooth and GPS reception Receiver path. Two types of filters commonly used in mobile phones include Surface Acoustic Wave Filter (SAWF) and Bulk Acoustic Wave Filter (BAWF). As shown in Figure 1A, SAWF is provided with two interdigital transducers (Interdigital Transducer, IDT) 63 at the receiving end and the sending end on the substrate 61 of piezoelectric material; the input electric signal is added on the transducer 63 at the sending end, because The piezoelectric effect of the substrate 61 converts the electrical signal into an acoustic signal propagating on the surface of the substrate 61, which is called a surface acoustic wave; the acoustic signal propagates to the receiving end transducer 63, and then is converted into an electrical signal and output to the load; in the electro-acoustic -In the process of electrical conversion and acoustic transmission, the filtering of the input signal is completed. As shown in FIG. 1B , a BAWF is provided with electrodes 73 on opposite sides of a quartz or silicon substrate 71 and a piezoelectric material (not shown) between the two electrodes 73 . Different from SAWF, the sound wave propagates vertically in the BAWF, and the electrodes 73 embedded on both sides of the substrate 71 excite the sound wave so that the sound wave bounces from the top surface to the bottom to form a standing sound wave.

For the functional components of the acoustic wave filter, such as interdigital transducers or surface electrodes, changes in surface conditions, such as damage, residues, changes in film structure, etc., will affect the characteristics of the acoustic wave filter. The existing acoustic wave filter packaging technology uses gold balls and solder balls that do not damage the functional surface, or uses wafer bonding, and then sets injection molding materials, adhesive film materials, etc. on the surface of the acoustic wave filter to form a cavity with the acoustic wave filter. To achieve the purpose of not damaging the functional surface of the component. However, the setting of injection molding material, adhesive film material, etc. will result in an increase in the package thickness of the acoustic wave filter.

Contents of the invention

In a first aspect, the present application provides a chip packaging structure, including:

Substrate;

A bare chip is flip-chip mounted on the substrate, and the surface of the bare chip facing the substrate is provided with functional elements;

at least one conductive bump, located between the substrate and the die, electrically connecting the die and the substrate;

A conductive sealing ring, located between the substrate and the die and spaced from the conductive bumps so that the functional element and the substrate are spaced apart from each other, and the sealing ring forms a closed circle around the functional element shape, so that a closed cavity is formed between the substrate and the die.

It can be seen that, in the chip packaging structure provided by the first aspect, in the space where conductive bumps need to be provided between the die and the substrate to realize the electrical connection between the die and the substrate, a closed ring-shaped sealing ring is provided to make the A closed cavity is formed between the bare chip and the substrate to avoid damage to the functional elements, so that no additional injection molding materials, adhesive film materials, etc. are required to cooperate with the bare chip to form a cavity, which simplifies The chip packaging structure effectively reduces the overall thickness of the chip packaging structure.

With reference to the first aspect, in some embodiments, the die includes an acoustic wave filter.

It can be seen that changes in the surface conditions of the functional components of the acoustic wave filter, such as damage, residues, and changes in the film structure, will affect the characteristics of the components. Therefore, it is necessary to focus on protecting the functional components of the acoustic wave filter during the packaging process. Through the setting of the sealing ring The functional components of the acoustic wave filter bare chip can be effectively protected, thereby avoiding direct processing on the surface of the acoustic wave filter functional components, and avoiding affecting filter characteristics.

With reference to the first aspect, in some embodiments, the functional element includes a resonator.

With reference to the first aspect, in some embodiments, a plurality of metal pads are provided on the surface of the die facing the substrate, and the plurality of metal pads include a closed ring-shaped metal pad and other dot-shaped metal pads. Pad, the sealing ring is connected between the closed ring-shaped metal pad and the substrate, and each conductive bump is connected between a dot-shaped metal pad and the substrate.

With reference to the first aspect, in some embodiments, both the sealing ring and the at least one conductive bump are formed by an electroplating process.

It can be seen that the sealing ring is formed at the same time as the electroplating process is used to form the conductive bumps to realize the electrical connection between the bare chip and the substrate. In this way, the manufacturing process of the chip packaging structure can be effectively simplified.

With reference to the first aspect, in some embodiments, the sealing ring and each conductive bump include a seed layer and an electroplating layer sequentially stacked on the surface of the die facing the substrate.

With reference to the first aspect, in some embodiments, the seed layer includes a Ti layer on the die and a Cu layer on the Ti layer, and the electroplating layer includes a Cu layer sequentially stacked on the seed layer, Ni layer, SnAg layer.

It can be seen that the Ti layer in the seed layer can be positioned as an adhesion layer between the metal pad of the die and the electroplating layer, and the Cu layer in the seed layer can be in contact with the Cu layer in the electroplating layer. The layers are firmly bonded. The Ni layer of the electroplated layer is arranged between the Cu layer and the SnAg layer to prevent Cu and Sn from forming a eutectic and causing an increase in brittleness; the setting of the SnAg layer is convenient for subsequent heating and melting to connect the sealing ring to the substrate and The conductive bump is electrically connected with the substrate.

With reference to the first aspect, in some embodiments, the substrate is provided with a wiring structure, and each conductive bump is electrically connected to the wiring structure, and the surface of the substrate away from the bare chip is provided with solder balls connected to the wiring structure.

In a second aspect, the present application provides a chip packaging method, including:

providing a bare chip with functional elements on its surface;

Forming a conductive sealing ring and at least one conductive bump on the surface of the bare chip with the functional element, the sealing ring forms a closed ring around the functional element;

Flip-chip the bare chip on a substrate by means of the sealing ring and the at least one conductive bump, and the at least one conductive bump is located between the bare chip and the substrate to realize the connection between the bare chip and the substrate. The electrical connection between the substrate, the sealing ring is located between the die and the substrate, so that a closed cavity is formed between the substrate and the die, and the functional element and the The substrates are spaced apart from each other.

It can be seen that in the chip packaging method provided by the second aspect, a closed cavity is formed between the bare chip and the substrate by forming a conductive bump between the bare chip and the substrate and simultaneously forming a closed ring-shaped sealing ring To avoid damage to the functional components, it is not necessary to form additional injection molding materials, adhesive film materials, etc. to cooperate with the die to form a cavity, which simplifies the chip packaging steps and effectively reduces the The overall thickness of the chip package structure.

With reference to the second aspect, in some embodiments, the step of providing a die with functional elements on its surface includes: providing an acoustic wave filter die with the functional elements.

With reference to the second aspect, in some embodiments, the step of providing a bare chip with functional elements on its surface includes: providing a bare chip with functional elements on its surface and a plurality of metal pads, the plurality of metal pads including a surrounding The functional elements are closed ring-shaped metal pads and other point-shaped metal pads.

With reference to the second aspect, in some embodiments, the step of forming the sealing ring and the at least one conductive bump includes:

forming a first photoresist layer on the surface of the die having the functional element, the first photoresist layer completely covers the functional element and each metal pad is exposed relative to the first photoresist layer;

forming a conductive seed layer on the surface of the first photoresist layer away from the die and on the plurality of metal pads;

forming a second photoresist layer on the seed layer, and forming a through hole at a position corresponding to each metal pad in the second photoresist layer so that the seed layer on each metal pad is relatively exposed;

Electroplating is used to form a conductive material in each through hole to connect the corresponding metal pad, wherein the conductive material connected to the closed ring-shaped metal pad is formed as a sealing ring, and the conductive material connected to other metal pads is formed as a conductive bump;

sequentially removing the second photoresist layer, the seed layer not covered by the sealing ring and the conductive bumps, and the first photoresist layer.

It can be seen that the functional elements are shielded and protected by the photoresist layer and the electroplating process is performed to form the conductive bumps and the sealing ring. Since the functional elements are shielded by the photoresist layer, the functional elements will not be polluted and damaged. .

In conjunction with the second aspect, in some embodiments, the step of forming the seed layer includes sequentially forming a stacked Ti layer and a Cu layer, and the step of forming a conductive material in each through hole using an electroplating process includes sequentially forming a stacked Cu layer , Ni layer, SnAg layer.

In a third aspect, the present application provides an electronic device, which includes a circuit board and the chip package structure described in the first aspect of the present application disposed on the circuit board.

Description of drawings

1A and 1B are schematic diagrams of two types of acoustic wave filters in the prior art.

FIG. 2A is a schematic cross-sectional view of a chip package structure according to an embodiment of the present application.

FIG. 2B is a schematic top view of the die of the chip packaging structure of the embodiment of the present application.

FIG. 3 is a schematic cross-sectional view of a sealing ring of a chip packaging structure according to an embodiment of the present application.

FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present application.

FIG. 5A is a first schematic diagram of the manufacturing process of the chip package structure according to the embodiment of the present application.

FIG. 5B is a second schematic diagram of the manufacturing process of the chip package structure according to the embodiment of the present application.

FIG. 5C is a third schematic diagram of the manufacturing process of the chip package structure according to the embodiment of the present application.

FIG. 5D is a schematic diagram 4 of the manufacturing process of the chip package structure according to the embodiment of the present application.

FIG. 5E is a fifth schematic diagram of the manufacturing process of the chip package structure according to the embodiment of the present application.

FIG. 5F is a sixth schematic diagram of the manufacturing process of the chip package structure according to the embodiment of the present application.

FIG. 5G is a schematic diagram 7 of the manufacturing process of the chip package structure according to the embodiment of the present application.

FIG. 5H is an eighth schematic diagram of the manufacturing process of the chip package structure according to the embodiment of the present application.

FIG. 5I is a schematic diagram 9 of the manufacturing process of the chip package structure according to the embodiment of the present application.

Detailed ways

Embodiments of the present application are described below with reference to the drawings in the embodiments of the present application.

In the existing packaging structure including the acoustic wave filter, injection molding materials, adhesive film materials, etc. are usually placed on the functional surface of the acoustic wave filter to cooperate with the acoustic wave filter to form a cavity so as not to damage the functional surface of the acoustic wave filter. However, the overall thickness of the packaging structure obtained in the above manner will be relatively large.

In view of this, please refer to FIG. 2A , a chip packaging structure 100 according to an embodiment of the present application includes a substrate 10 and a die 30 flip-chip mounted on the substrate 10 . A functional element 31 is disposed on the surface of the die 30 facing the substrate 10 . The die 30 can be an acoustic wave filter die, but not limited thereto. The chip packaging structure 100 further includes a conductive sealing ring 50 and at least one conductive bump 40 . Each conductive bump 40 is located between the substrate 10 and the die 30 for electrically connecting the die 30 and the substrate 10 . The sealing ring 50 is also located between the substrate 10 and the die 30 , that is, it is disposed on the same layer as the conductive bump 40 and is spaced apart from the conductive bump 40 . The sealing ring 50 is used to keep the functional element 31 and the substrate 10 from contacting each other. Referring to FIG. 2B , the sealing ring 50 forms a closed ring around the functional element 31 , so that a closed cavity 101 is formed between the substrate 10 and the die 30 . As shown in FIG. 2A , in this embodiment, the conductive bump 40 is located in the cavity 101 . It can be understood that the location of the conductive bumps 40 is not limited to being set in the cavity 101, and can also be set outside the cavity 101; or part of the conductive bumps 40 are set in the cavity 101, and some of the conductive bumps 40 are set in the cavity 101 outside.

The bare chip (die) in this application refers to a chip produced by a processing factory, that is, a chip that has not been packaged after the wafer has been diced and tested.

In the chip packaging structure 100 of the present application, in the space between the bare chip 30 and the substrate 10 where conductive bumps 40 need to be provided to realize the electrical connection between the bare chip 30 and the substrate 10, a closed ring-shaped sealing ring 50 is provided so that the A closed cavity 101 is formed between the bare chip 30 and the substrate 10 to avoid damage to the functional element 31, so that there is no need to additionally arrange other injection molding materials, adhesive film materials, etc. to cooperate with the bare chip 30 Forming the cavity 101 simplifies the chip packaging structure 100 and effectively reduces the overall thickness of the chip packaging structure 100 .

The die 30 may include an acoustic wave filter. When the die 30 includes an acoustic wave filter, the functional element 31 includes a resonator. The circuit (not shown) of the bare chip 30 may include the acoustic wave filter module and other functional modules, or only include the acoustic wave filter module. Changes in the surface conditions of the functional components 31 of the acoustic wave filter, such as damage, residues, and changes in the film structure, will affect the characteristics of the components. Therefore, it is necessary to focus on protecting the functional components 31 on the surface of the acoustic wave filter during the packaging process. This application adopts the sealing ring The setting of 50 can effectively protect the functional element 31 of the bare chip 30, thereby avoiding direct processing on the surface of the acoustic wave filter functional element 31 and avoiding affecting the filter characteristics.

The acoustic wave filter in the present application can be the conventional acoustic wave filter of this field, for example SAWF, it has the resonator of the interdigital transducer (Interdigital Transducer, IDT) interdigitated; A resonator with a laminated structure of materials.

As shown in FIG. 2A , a plurality of metal pads 33 are arranged on the surface of the die 30 facing the substrate 10 , and the plurality of metal pads 33 and the functional element 31 are all arranged on the same surface of the die 30 . a surface. The plurality of metal pads 33 includes one metal pad 33a in the shape of a closed ring and other metal pads 33b in the shape of points. Two point-like metal pads 33b are shown in FIG. 2A. The sealing ring 50 is connected and located between the closed ring-shaped metal pad 33 a and the substrate 10 . Each conductive bump 40 is located between a dot-shaped metal pad 33 b and the substrate 10 to electrically connect the die 30 and the substrate 10 .

As shown in FIG. 2A , the substrate 10 is also provided with a metal pad 33 at a position corresponding to the connection between the sealing ring 50 and the conductive bump 40 . The metal pads 33 on the substrate 10 also include a metal pad 33a in the shape of a closed circle and other metal pads 33b in the shape of points. The sealing ring 50 is connected and located between the closed-ring-shaped metal pad 33 a on the die 30 and the closed-ring-shaped metal pad 33 a on the substrate 10 . Each conductive bump 40 is connected to and located between a dot-like metal pad 33 b on the die 30 and a dot-like metal pad 33 b on the substrate 10 .

In this embodiment, both the sealing ring 50 and the at least one conductive bump 40 are formed by an electroplating process. The electroplating process is used to form the conductive bumps 40 to realize the electrical connection between the die 30 and the substrate 10 while forming the sealing ring 50 , so that the manufacturing process of the chip packaging structure 100 can be effectively simplified.

Since the sealing ring 50 and the conductive bump 40 are formed simultaneously by electroplating process, they have exactly the same cross-sectional structure, and only the cross-sectional structure of the sealing ring 50 is shown in FIG. 3 . As shown in FIG. 3 , the sealing ring 50 and each conductive bump 40 include a seed layer 51 and an electroplating layer 53 sequentially laminated on the surface of the die 30 facing the substrate 10 . The seed layer 51 includes a Ti layer 511 on the die 30 and a Cu layer 513 on the Ti layer 511, and the electroplating layer 53 includes a Cu layer 531 and a Ni layer stacked on the seed layer 51 in sequence. 533 . The SnAg layer 535 . The thickness of the seed layer 51 is generally lower than that of the electroplating layer 53 . Due to the particularity of the electroplating process, the layer formed by electroplating can only be deposited on the surface of the conductive material, so the electroplating process generally forms a thinner conductive seed layer 51 in advance, and then forms a layer with a relatively thicker thickness on the surface of the seed layer 51. Thick electroplating layer 53.

The Ti layer 511 in the seed layer 51 can serve as an adhesion layer between the metal pad 33 of the die 30 and the electroplating layer 53, and the Cu layer 513 in the seed layer 51 can be in contact with the electroplating layer. The Cu layer 531 in 53 is firmly bonded. The Ni layer 533 of the electroplated layer 53 is arranged between the Cu layer 531 and the SnAg layer 535 to prevent Cu and Sn from forming a eutectic and causing an increase in brittleness; the setting of the SnAg layer 535 is convenient for subsequent heating and melting to make the sealing ring 50 and The substrate 10 is connected and the conductive bump 40 is electrically connected to the substrate 10 .

It can be understood that the sealing ring 50 and the conductive bump 40 are not limited to the structure of the seed layer 51 and the electroplating layer 53 obtained by the electroplating process, and solder paste can also be directly used to form the seal. circle 50 and the conductive bump 40 .

The substrate 10 can be a substrate of organic material, a ceramic substrate, or a fan-out packaging substrate. As shown in FIG. 2A , the substrate 10 is provided with a wiring structure 11 . Each conductive bump 40 is electrically connected to the wiring structure 11 through a metal pad 33 on the substrate 10 . The surface of the substrate 10 away from the bare chip 30 is provided with solder balls 13 electrically connected to the wiring structure 11 to realize signal extraction. It can be understood that in this embodiment, the sealing ring 50 is also electrically connected to the wiring structure 11 . It can be understood that the sealing ring 50 may not be electrically connected to the wiring structure 11 .

As shown in FIG. 4 , the embodiment of the present application also provides an electronic device 300 , which includes a circuit board 310 and the chip packaging structure 100 disposed on the circuit board 310 . The substrate 10 can be located between the circuit board 310 and the die 30 , and the solder balls 13 of the substrate 10 can be electrically connected to the circuit board 310 . The electronic device 300 shown in FIG. 4 is a mobile phone, but not limited to the mobile phone.

Referring to FIG. 5A to FIG. 5I in conjunction, the present application also provides a chip packaging method, including:

providing a bare chip 30 with functional elements 31 disposed on its surface;

A conductive sealing ring 50 and at least one conductive bump 40 are formed on the surface of the bare chip 30 having the functional element 31, and the sealing ring 50 forms a closed ring around the functional element 31;

Relying on the sealing ring 50 and the at least one conductive bump 40 to flip-chip the die 30 on a substrate 10, the at least one conductive bump 40 is located between the die 30 and the substrate 10 Realize the electrical connection between the die 30 and the substrate 10, the sealing ring 50 is located between the die 30 and the substrate 10, so that the substrate 10 and the die 30 A closed cavity 101 is formed and the functional element 31 and the substrate 10 are spaced apart from each other.

In the chip packaging method of the present application, a closed cavity is formed between the bare chip 30 and the substrate 10 by forming the conductive bump 40 between the bare chip 30 and the substrate 10 and simultaneously forming the closed ring-shaped sealing ring 50 101 to avoid damage to the functional element 31, so that there is no need to additionally form other injection molding materials, adhesive film materials, etc. to cooperate with the die 30 to form a cavity 101, which simplifies the steps of chip packaging and is effective The overall thickness of the chip packaging structure 100 is reduced.

Referring to FIG. 5A , the step of providing a bare chip 30 with functional elements 31 on its surface includes: providing a bare chip 30 with functional elements 31 and a plurality of metal pads 33 on its surface, and the plurality of metal pads 33 include The above-mentioned functional element 31 is a metal pad 33a in the shape of a closed ring and other metal pads 33b in the shape of a point. The die 30 may be a die 30 including an acoustic wave filter, and the functional element 31 may include a resonator.

Referring to FIG. 5B to FIG. 5I , forming the sealing ring 50 and the at least one conductive bump 40 specifically includes the following steps.

Referring to FIG. 5B, a first photoresist layer 21 is formed on the surface of the die 30 having the functional element 31, the first photoresist layer 21 completely covers the functional element 31 and each metal pad 33 is opposite to each other. The first photoresist layer 21 is exposed. The thickness of the first photoresist layer 21 is to ensure that the functional element 31 is completely covered to prevent subsequent processing steps from affecting the functional element 31 . The first photoresist layer 21 defines an opening 211 at a position corresponding to each metal pad 33 to expose the metal pad 33 .

Referring to FIG. 5C , a conductive seed layer 51 is formed on the surface of the first photoresist layer 21 away from the die 30 and the plurality of metal pads 33 . The setting of the seed layer 51 is to obtain a thin conductive seed layer 51 in advance, and subsequently form a relatively thick electroplating layer at the corresponding position of the seed layer 51 .

Referring to FIG. 5D , the second photoresist layer 22 is formed on the seed layer 51 , and a through hole 221 is formed at the position corresponding to each metal pad 33 in the second photoresist layer 22 so that each metal pad 33 The seed layer 51 is relatively exposed. In this step, in order to define the position where the thickness plating layer 53 is formed, the plating layer will be formed on the seed layer 51 in the through hole 221 .

Please refer to FIG. 5E , an electroplating process is used to form a conductive material in each through hole 221 to connect the corresponding metal pad 33, wherein the conductive material connected to the closed ring-shaped metal pad 33a is formed as a sealing ring 50, and connected to other metal pads 33b The conductive material is formed into conductive bumps 40 .

Referring to FIG. 5F, FIG. 5G, and FIG. 5H, the second photoresist layer 22, the seed layer 51 not covered by the sealing ring 50 and the conductive bump 40, and the first photoresist layer are sequentially removed. twenty one.

The functional element 31 is shielded and protected by a photoresist layer and the electroplating process is performed to form the conductive bump 40 and the sealing ring 50, since the functional element 31 is shielded by the photoresist layer and will not pollute and damage the functional element 31.

It can be understood that the size of the opening area of the through hole 221 opened in the second photoresist layer 22 can be adjusted as required. For example, the opening area of the through hole 221 may be smaller than the area of the metal pad 33 , or equal to the area of the metal pad 33 , or smaller than the area of the metal pad 33 . Due to the difference in the opening size of the through hole 221 , the microstructures of the conductive bump 40 and the sealing ring 50 formed by electroplating will have a small difference.

The step of forming the seed layer 51 includes sequentially forming a laminated Ti layer 511 and a Cu layer 513 , and the method of forming each layer of the seed layer 51 can be a sputtering method. The step of forming conductive material in each through hole by electroplating process includes sequentially forming stacked Cu layer 513 , Ni layer 533 , and SnAg layer 535 by electroplating process.

The packaging method further includes reducing the thickness of the bare chip 30 before flip-chip mounting the bare chip 30 on the substrate 10, specifically setting the functional element 31 opposite to the bare chip 30. The thickness of the surface is reduced, as shown in Figure 5I.

The step of flipping the bare chip 30 on the substrate 10: place and align the surface of the bare chip 30 with the sealing ring 50 and the conductive bump 40 facing the substrate 10, so that the bare chip 30 The sheet 30 is stacked on the substrate 10, and then heated to melt the SnAg layer 535 or solder paste in the sealing ring 50 and the conductive bump 40, and after cooling, the sealing ring 50 and the conductive bump 40 are The substrate 10 is especially firmly combined with the metal pad 33 on the substrate 10, so that the die 30 is mounted on the substrate 10, and the chip package structure 100 shown in FIG. 2A is obtained.

It should be noted that the above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto, and any person familiar with the technical field can easily think of changes or substitutions within the scope of the technology disclosed in the application , should be covered within the protection scope of the present application; in the case of no conflict, the implementation modes and the features in the implementation modes of the application can be combined with each other. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A chip packaging structure, characterized in that, comprising:

Substrate;

A bare chip is flip-chip mounted on the substrate, and the surface of the bare chip facing the substrate is provided with functional elements;

at least one conductive bump, located between the substrate and the die, electrically connecting the die and the substrate;

A conductive sealing ring, located between the substrate and the die and spaced from the conductive bumps so that the functional element and the substrate are spaced apart from each other, and the sealing ring forms a closed circle around the functional element shape, so that a closed cavity is formed between the substrate and the die.
The chip package structure according to claim 1, wherein the die comprises an acoustic wave filter.
The chip package structure according to claim 1 or 2, wherein the functional element comprises a resonator.
The chip packaging structure according to any one of claims 1 to 3, wherein a plurality of metal pads are provided on the surface of the die facing the substrate, and the plurality of metal pads comprise a closed circle Shaped metal pads and other point-shaped metal pads, the sealing ring is connected between the closed ring-shaped metal pad and the substrate, and each conductive bump is connected to a point-shaped metal pad and the substrate. between the substrates.
The chip packaging structure according to any one of claims 1 to 4, characterized in that, both the sealing ring and the at least one conductive bump are formed by an electroplating process.
The chip packaging structure according to claim 5, wherein the sealing ring and each conductive bump include a seed layer and an electroplating layer sequentially stacked on the surface of the die facing the substrate.
The chip packaging structure according to claim 6, wherein the seed layer comprises a Ti layer on the bare chip and a Cu layer on the Ti layer, and the electroplating layer includes layers sequentially stacked on the seed layer. Cu layer, Ni layer, SnAg layer.
The chip packaging structure according to any one of claims 1 to 7, wherein a wiring structure is arranged in the substrate, each conductive bump is electrically connected to the wiring structure, and the substrate is away from the bare The surface of the sheet is provided with solder balls connecting the wiring structures.
A chip packaging method, characterized in that, comprising:

providing a bare chip with functional elements on its surface;

Forming a conductive sealing ring and at least one conductive bump on the surface of the bare chip with the functional element, the sealing ring forms a closed ring around the functional element;

Flip-chip the bare chip on a substrate by means of the sealing ring and the at least one conductive bump, and the at least one conductive bump is located between the bare chip and the substrate to realize the connection between the bare chip and the substrate. The electrical connection between the substrate, the sealing ring is located between the die and the substrate, so that a closed cavity is formed between the substrate and the die, and the functional element and the The substrates are spaced apart from each other.
The chip packaging method according to claim 9, wherein the step of providing a bare chip with functional elements on its surface comprises: providing an acoustic wave filter bare chip with the functional elements.
The chip packaging method according to claim 9 or 10, wherein the step of providing a bare chip with functional elements on its surface comprises: providing a bare chip with functional elements and a plurality of metal pads on its surface, the multiple The two metal pads include a closed ring-shaped metal pad surrounding the functional element and other dot-shaped metal pads.
The chip packaging method according to claim 11, wherein the step of forming the sealing ring and the at least one conductive bump comprises:

forming a first photoresist layer on the surface of the die having the functional element, the first photoresist layer completely covers the functional element and each metal pad is exposed relative to the first photoresist layer;

forming a conductive seed layer on the surface of the first photoresist layer away from the die and on the plurality of metal pads;

forming a second photoresist layer on the seed layer, and forming a through hole at a position corresponding to each metal pad in the second photoresist layer so that the seed layer on each metal pad is relatively exposed;

Electroplating is used to form conductive material in each through hole to connect the corresponding metal pad, wherein the conductive material connected to the closed ring-shaped metal pad is formed as a sealing ring, and the conductive material connected to other metal pads is formed as a conductive bump;

sequentially removing the second photoresist layer, the seed layer not covered by the sealing ring and the conductive bumps, and the first photoresist layer.
The chip packaging method according to claim 12, wherein the step of forming the seed layer includes sequentially forming stacked Ti layers and Cu layers, and the step of forming a conductive material in each through hole using an electroplating process includes sequentially forming Stacked Cu layer, Ni layer, SnAg layer.
An electronic device comprising a circuit board and the chip packaging structure according to any one of claims 1 to 8 arranged on the circuit board.