CN219393394U - DRAM module packaging structure based on double-bare-core stacking - Google Patents

Abstract

The utility model discloses a DRAM module packaging structure based on double bare chip stacking, which comprises a base material, a flip chip positioned at a lower layer, a forward chip positioned at an upper layer and Underfill, wherein the flip chip is flip-chip mounted on the base material, the back surface of the forward chip is interconnected with the back surface of the flip chip, the Underfill fills a gap, ball welding is performed on the front surface of the forward chip positioned at the upper layer, and a bonding wire is connected with the base material; and the plastic packaging material coats the DRAM module packaging structure based on the double-die stacking. The stacking structure is suitable for a special structure, the lower part of the stacking structure is provided with the flip chip, and the upper part of the stacking structure is provided with the forward chip; and can solve the interconnection between the stacked chips, and fill the structure with the underwill process, support steadily when making WB bonding wire. Therefore, the structure can realize the stacking of chips, reduce the packaging area, realize the interconnection of specific functional areas among the chips, shorten the interconnection length and improve the electrical performance and the reliability of products.

Description

DRAM module packaging structure based on double-bare-core stacking

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a DRAM module packaging structure based on double-die stacking.

Background

With the gradual increase of the performance of the processor, a plurality of DRAM chips are required to be matched for use as a cache. The advanced packaging technology is adopted, so that the contradiction between large capacity, small size and high performance can be relieved, and the gap of the domestic manufacturing process is made up.

Taking a dual chip stacked DRAM package as an example, the current stacked patent situation is analyzed:

such as patent application, application number: 201410199594.3, name of utility model: a DRAM double-chip stacked package structure and a packaging method; the similar DRAM adopts a back-to-back stacked structure, the lower part is inverted and bonded on the upper part, and a welding spot redistribution process is not adopted, but the processing mode is that after the pad in a Wire bond process chip is converted into a convex point, the convex point is welded on a substrate by an FC process, and strict requirements are imposed on the windowing size and pitch spacing of the DRAM bare chip.

Such as patent application, application number: 201310142301.3, name of utility model: a DRAM double-chip stacked package structure and a package process, wherein the similar DRAM adopts an intermediate substrate, so that the transmission line constraint is reduced, the electrical performance of the package is improved, but the processing mode requires the two substrate processes of the intermediate substrate and the chip substrate.

Such as patent application, application number: 202210576411.X, title of utility model: a DDR3 chip with high capacity and three-dimensional stacking is characterized in that a TSV advanced packaging structure is adopted by a similar DRAM, the problems of fan-out area and transmission performance of bonding wires caused by the increase of the stacking layers are effectively solved, but the processing mode is used for a double-chip stacking scene, and the cost is relatively high.

Therefore, a DRAM module packaging structure based on dual-die stacking needs to be developed, and has the characteristics of small size, large capacity, high performance, low cost, wide application and the like.

Disclosure of Invention

The utility model provides a DRAM module packaging structure based on double-die stacking, which adopts the following technical scheme: the utility model provides a DRAM module packaging structure based on two bare core stacks, includes first bare core, second bare core, base plate and encapsulation cavity, and first bare core openly face the base plate and flip on the base plate, interconnect with the base plate through Wire Bond bonding Wire, the second bare core back paste install in first bare core top forms openly towards the structural style of base plate, after RDL walks the line, through Wire Bond bonding Wire and base plate interconnection, both encapsulate as an organic wholely through the encapsulation cavity to form groove type step packaging structure in the routing position.

According to the technical scheme, the second bare chip is a Wire bond packaging process, and the Wire bond bonding is performed after the middle pad is led out to the two sides of the bare chip through RDL wiring in consideration of the Wire arc length.

For the preferred embodiments of the present utility model, the substrate bottom layer directly connects a portion of the finger signal to the ball terminal without a via.

In the technical scheme of the utility model, the first bare chip and the substrate, and the first bare chip and the second bare chip are all fixed through a chip mucosa DAF.

Compared with the prior art, the utility model has the beneficial effects that:

1. according to the DRAM module packaging structure based on double-bare-core stacking, a back-to-back stacking mode is adopted, and the bottom layer of the substrate can directly connect part of finger signals to the ball end without through holes, so that the substrate design difficulty and the substrate layer number are reduced, and the impedance continuity of a routing channel is improved.

2. According to the DRAM module packaging structure based on double-bare-core stacking, from the multi-chip cascading use scene of the DRAM module on the PCB, the stub length of address and control signals is effectively reduced by adopting an up-down wire bonding mode, and the signal integrity is improved.

Drawings

Fig. 1 is a schematic layout diagram of a cavity of a dual-die stacked-based DRAM module package according to the present embodiment (the dashed lines in the figure enclose a cavity of a prior art package).

Detailed Description

The technical scheme of the present utility model is described in detail below, but the scope of the present utility model is not limited to the embodiments. In order to make the contents of the present utility model more comprehensible, the present utility model is further described with reference to fig. 1 and the detailed description below.

The embodiment is a dual die stack-based DRAM module package structure, and further describes a DRAM chip formed by 2 DDR3 die, 1 substrate and 1 package cavity as an example.

In the embodiment, 2 DDR3 bare chips are all preferably DDR3 bare chips; the definition, 2 DDR3 bare chips are divided into a first DDR3 bare chip and a second DDR3 bare chip. The DDR3 die in this embodiment is preferably a domestic eastern semiconductor corporation model FM38F16SSB9MGD die, having a storage capacity of 4Gb, a bit width of 16 bits, and a supply voltage of 1.5V.

As shown in fig. 1, the first DDR3 die is flip-chip mounted on the substrate 3 with its front side facing the substrate 3, and is interconnected with the substrate 3 by a Wire Bond Wire 5, the second DDR3 die is mounted on the first DDR3 die with its back side, so as to form a structure with its front side facing the substrate 3, and after passing through the RDL wiring 6, is interconnected with the substrate 3 by a Wire Bond Wire 5, and is packaged as a whole by a package cavity 4, and forms a trench step package structure 7 at the Wire bonding position.

As shown in fig. 1, the second DDR3 die is itself a Wire bond packaging process, and the Wire bond is performed by extracting the intermediate pad to both sides of the die through RDL wiring 6 in consideration of the Wire arc length.

As shown in fig. 1, the bottom layer of the substrate 3 directly connects part of finger signals to the ball terminal without a via hole, so as to improve impedance continuity.

As shown in fig. 1, the first DDR3 die and the substrate 3, and the first DDR3 die and the second die are fixed by a die attach DAF.

As shown in fig. 1, the JEDEC standard is satisfied for both single rank and dual rank DRAM modules, and only the CS and ZQ signals have an extraction difference.

The above embodiments are only for illustrating the technical idea of the present utility model, and the protection scope of the present utility model is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present utility model falls within the protection scope of the present utility model.

Claims (4)

1. A DRAM module packaging structure based on double-bare-core stacking is characterized in that: including first naked core (1), second naked core (2), base plate (3) and encapsulation cavity (4), the front face of first naked core (1) is in towards base plate (3) flip-chip is in on base plate (3), through Wire Bond bonding line (5) with base plate (3) interconnection, the back paste of second naked core (2) in first naked core (1) top forms the structural style of front orientation base plate (3), after RDL walks line (6), through Wire Bond bonding line (5) and base plate interconnection, both encapsulate as an organic wholely through encapsulation cavity (4) to form groove step packaging structure (7) in the routing position.

2. The dual die stack based DRAM module package structure of claim 1, wherein: the second bare chip (2) is a Wire bond packaging process, and the middle pad is led out to the two sides of the bare chip through RDL wiring and then Wire bond is carried out.

3. The dual die stack based DRAM module package structure of claim 1, wherein: the substrate (3) bottom layer directly connects part of finger signals to the ball terminal without a via hole.

4. The dual die stack based DRAM module package structure of claim 1, wherein: the first bare chip (1) and the substrate (3), and the first bare chip (1) and the second bare chip (2) are all fixed through a chip adhesive film DAF.