CN219371016U - DFN1610 chip frame structure - Google Patents
DFN1610 chip frame structure Download PDFInfo
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- CN219371016U CN219371016U CN202320013726.3U CN202320013726U CN219371016U CN 219371016 U CN219371016 U CN 219371016U CN 202320013726 U CN202320013726 U CN 202320013726U CN 219371016 U CN219371016 U CN 219371016U
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Abstract
The utility model relates to a DFN1610 chip frame structure, which comprises a DFN1610 chip frame, wherein a left side island and a right side island are arranged on the DFN1610 chip frame; the left side island is provided with a first chip loading area, one side of the first chip loading area, facing to the right side island, is provided with a left side island wire bonding area, and the shape of the left side island wire bonding area is isosceles trapezoid; the right side island is provided with a second chip loading area, one side of the second chip loading area facing the left side island is provided with a right side island wire bonding area, and the shape of the right side island wire bonding area is in a groove shape which is matched with the isosceles trapezoid shape. The utility model increases the area of the chip loading area, so that the chip loading area can be assembled with a larger size chip, and the chip loading area is compatible with a double-chip opposite-punching serial structure and a double-chip opposite-punching parallel structure.
Description
Technical Field
The utility model belongs to the technical field of chip frames, and particularly relates to a DFN1610 chip frame structure.
Background
On the premise that the structural parameters of the chip are not obviously broken through, the ESD finished product has good electrical parameters, the inner sealing chip needs to keep a certain size specification, contradictions with the miniaturization of the existing finished product packaging size, and higher requirements are provided for the product assembly structure.
The conventional frame style (see fig. 1) can only be used for chip serial chip mounting, if the parallel chip mounting is forced, the negative influence on the chip size is great, and only small-size chips can be mounted, so that the electric parameters of the product cannot be dominant.
Therefore, it is necessary to design a chip frame structure that can increase the area of the mounting area and enable the mounting area to be assembled with a larger chip size on the premise of meeting the wiring requirement and ensuring the regularity of the mounting area (keeping the rectangular shape) on the frame.
Disclosure of Invention
Aiming at the defects of the prior art, the utility model provides a DFN1610 chip frame structure which increases the area of a chip loading area, enables the chip loading area to be assembled with a larger size chip, and can be compatible with a double-chip opposite-beating serial structure and a double-chip opposite-beating parallel structure.
In order to achieve the above purpose, the technical scheme of the utility model is as follows:
a DFN1610 chip frame structure comprises a DFN1610 chip frame, wherein a left side island and a right side island are arranged on the DFN1610 chip frame;
the left side island is provided with a first chip loading area, one side of the first chip loading area, facing to the right side island, is provided with a left side island wire bonding area, and the cross section of the left side island wire bonding area is in an isosceles trapezoid shape;
the right side island is provided with a second chip loading area, one side of the second chip loading area facing the left side island is provided with a right side island wire bonding area, the shape of the right side island wire bonding area is a groove shape, and the right side island wire bonding area is tightly attached to the left side island wire bonding area.
In the above-mentioned DFN1610 chip frame structure, an angle between a waist line slope of the left side island routing area and a side edge of the first die-mounting area is 45 degrees; the included angle between the groove inclined plane of the right side island routing area and the side edge of the second chip loading area is 45 degrees.
In the DFN1610 chip frame structure, the left side, the top and the bottom of the left side island are respectively provided with a first frame pin; and the right side, the top and the bottom of the right side island are respectively provided with a second frame pin.
The utility model has the technical effects and advantages that:
according to the DFN1610 chip frame structure, through the pre-separation design of the wire bonding area where the left side island is connected with the right side island, the area of the chip loading area can be increased on the premise of meeting the wire bonding requirement and guaranteeing the regularity of the chip loading area on the frame, so that a chip with a larger size can be assembled at the position, the universality of the frame is improved, meanwhile, a double-core opposite-bonding serial structure and a double-core opposite-bonding parallel structure are compatible, the operability in the subsequent product specification design stage is improved, and more advantageous packaging structures can be matched.
Drawings
FIG. 1 is a prior art DFN1610-2 chip frame structure;
fig. 2 is a DFN1610 chip frame structure of the utility model.
Reference numerals in the drawings: 1. DFN1610 chip frame; 2. left side islands; 21. a first die-loading area; 22. left side island routing area; 3. a right side island; 31. a second die-loading area; 32. a right side island routing area; 7. a first frame pin; 8. a first frame pin.
Detailed Description
The utility model is described in further detail below with reference to examples given in the accompanying drawings.
Referring to fig. 2, a DFN1610 chip frame structure includes a DFN1610 chip frame 1, where a left side island 2 and a right side island 3 are disposed on the DFN1610 chip frame 1.
In the implementation, as shown in fig. 2, a first die-bonding area 21 is disposed on the left side island 2, a left side island routing area 22 is disposed on a side of the first die-bonding area 21 facing the right side island 3, and a cross section of the left side island routing area 22 is in an isosceles trapezoid shape.
In the specific implementation, referring to fig. 2, the right side island 3 is provided with a second chip mounting area 31, one side of the second chip mounting area 31 facing the left side island 2 is provided with a right side island routing area 32, and the shape of the right side island routing area 32 is a groove shape, which is closely attached to the left side island routing area 22.
In specific implementation, the angle between the inclination of the waist line of the left side island wire bonding area 22 and the side edge of the first chip loading area 21 is 45 degrees; the included angle between the groove slope of the right side island routing region 32 and the side edge of the second die-filling region 31 is 45 degrees.
In the implementation, the left side, the top and the bottom of the left side island 2 are respectively provided with a first frame pin 7; the right side, the top and the bottom of the right side island 3 are respectively provided with a second frame pin 8.
Referring to fig. 1, the conventional frame style generally can only be used for chip serial chip mounting, if the parallel chip mounting is forcibly performed, the negative effect on the chip size is great, only small-sized chips can be mounted, and the final product often cannot take advantage of electrical parameters.
According to the utility model, the wire bonding area where the left side island 2 and the right side island 3 are connected is designed separately in advance, so that the area of the chip loading area can be increased on the premise of meeting the wiring requirement and guaranteeing the regularity of the chip loading area on the frame, the chip with larger size can be assembled at the position, the universality of the frame is improved, meanwhile, the dual-core butt-bonding serial structure and the dual-core butt-bonding parallel structure are compatible, the operability in the subsequent product specification design stage is improved, and more advantageous packaging structures can be matched.
The foregoing is merely a preferred embodiment of the present utility model, and it should be noted that modifications and improvements could be made by those skilled in the art without departing from the inventive concept, which falls within the scope of the present utility model.
Claims (3)
1. A DFN1610 chip frame structure, characterized by: the semiconductor chip comprises a DFN1610 chip frame (1), wherein a left side island (2) and a right side island (3) are arranged on the DFN1610 chip frame (1);
a first chip loading area (21) is arranged on the left side island (2), a left side island wire bonding area (22) is arranged on one side, facing the right side island (3), of the first chip loading area (21), and the cross section of the left side island wire bonding area (22) is in an isosceles trapezoid shape;
the right side island (3) is provided with a second chip loading area (31), one side of the second chip loading area (31) facing the left side island (2) is provided with a right side island routing area (32), and the shape of the right side island routing area (32) is in a groove shape, and the right side island routing area is tightly attached to the left side island routing area (22).
2. The DFN1610 chip frame structure according to claim 1, wherein: the angle between the inclination of the waist line of the left side island wire bonding area (22) and the side edge of the first chip loading area (21) is 45 degrees; the included angle between the inclined surface of the groove of the right side island routing area (32) and the side edge of the second chip loading area (31) is 45 degrees.
3. The DFN1610 chip frame structure according to claim 2, wherein: the left side, the top and the bottom of the left side base island (2) are respectively provided with a first frame pin (7); the right side, the top and the bottom of the right side base island (3) are respectively provided with a second frame pin (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320013726.3U CN219371016U (en) | 2023-01-04 | 2023-01-04 | DFN1610 chip frame structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320013726.3U CN219371016U (en) | 2023-01-04 | 2023-01-04 | DFN1610 chip frame structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219371016U true CN219371016U (en) | 2023-07-18 |
Family
ID=87147883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320013726.3U Active CN219371016U (en) | 2023-01-04 | 2023-01-04 | DFN1610 chip frame structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219371016U (en) |
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2023
- 2023-01-04 CN CN202320013726.3U patent/CN219371016U/en active Active
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