CN219351265U - Output voltage holding time extension device and server - Google Patents
Output voltage holding time extension device and server Download PDFInfo
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- CN219351265U CN219351265U CN202320235467.9U CN202320235467U CN219351265U CN 219351265 U CN219351265 U CN 219351265U CN 202320235467 U CN202320235467 U CN 202320235467U CN 219351265 U CN219351265 U CN 219351265U
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- 239000003990 capacitor Substances 0.000 claims abstract description 34
- 238000004146 energy storage Methods 0.000 claims abstract description 30
- 238000001514 detection method Methods 0.000 claims description 28
- 230000002035 prolonged effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 14
- 238000012423 maintenance Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model relates to the field of power supply output voltage holding time extension, and particularly discloses an output voltage holding time extension device and a server, wherein a first end of an energy storage capacitor is connected with a positive electrode of a power supply, a second end of the energy storage capacitor is connected with a negative electrode of the power supply, the first end of the energy storage capacitor is also connected with a first end of an inductor, a second end of the inductor is connected with a positive electrode of a diode, and the negative electrode of the diode outputs voltage; the drain electrode of the MOS tube is connected with the anode of the diode, the source electrode of the MOS tube is grounded, and the grid electrode of the MOS tube is connected with the MOS tube control circuit; when the power supply is powered off, the MOS tube control circuit obtains the voltages at two ends of the energy storage capacitor and the output voltage at the negative end of the diode, and controls the on-off of the MOS tube according to the two voltages. According to the utility model, the MOS tube is added on the power supply side to form the booster circuit, so that the holding time of the output power supply is prolonged, the power supply holding time requirement is met, and only one MOS tube is added on the power panel, so that the occupied space is small, and the requirement of miniaturization of the board card is met.
Description
Technical Field
The utility model relates to the field of power supply output voltage holding time extension, in particular to an output voltage holding time extension device and a server.
Background
The output voltage maintaining time (Hold up time) refers to the duration or the length of time that the output voltage can normally maintain when the power supply is turned off or power is turned off, and fig. 1 is a schematic diagram of the output power maintaining time, and T2 in fig. 1 refers to the maintaining time. This time period is used to maintain the output of the computer system unstable or free from the disturbance of the power system due to momentary short circuits, overload, momentary power failure, voltage sag, etc. The length of the maintaining time depends on the capacity of the primary side energy storage large capacitor (Bulk Capacitors), and the larger the capacity is, the longer the maintaining time is, and the shorter the maintaining time is otherwise.
Fig. 2 is a schematic diagram of a typical power supply secondary side output circuit, wherein the power supply internal output consists of an energy storage capacitor, an inductor and a diode, and the main board internal equivalent circuit consists of a system capacitor and a system resistor. The power output circuit has only a filtering function and does not have a great effect on the holding time, and when the Vin input voltage is powered off, the Vout output voltage drops immediately.
Currently, server power supply development is so far miniaturized as an important development point, and therefore, the energy storage capacitor cannot be placed into a larger energy storage capacitor in the existing space, so that the holding time is limited and the requirement cannot be met.
Disclosure of Invention
In order to solve the problems, the utility model provides an output voltage holding time extension device and a server, wherein an MOS tube is added on a power supply side to form a booster circuit, so that the holding time of an output power supply is prolonged, the power supply holding time requirement is met, and only one MOS tube is added on a power panel, so that the occupied space is small, and the requirement of miniaturization of a board card is met.
In a first aspect, the present utility model provides an output voltage holding time extension apparatus, including: an energy storage capacitor, an inductor and a diode; the device further comprises an MOS tube and an MOS tube control circuit, wherein the MOS tube is an N-type MOS tube;
the drain electrode of the MOS tube is connected with the anode of the diode, the source electrode of the MOS tube is grounded, and the grid electrode of the MOS tube is connected with the MOS tube control circuit;
when the power supply is powered off, the MOS tube control circuit obtains the voltages at two ends of the energy storage capacitor and the output voltage at the negative end of the diode, and controls the on-off of the MOS tube according to the two voltages.
Further, the MOS transistor control circuit includes: the power supply detection sub-circuit, the input voltage acquisition sub-circuit, the comparator, the error amplifier and the PWM generator;
the input end of the power supply detection sub-circuit is connected with a power supply, and the output end of the power supply detection sub-circuit is connected with the control end of the input voltage acquisition sub-circuit; the input end of the input voltage acquisition sub-circuit is connected with the energy storage capacitor, the output end is connected with the positive input end of the comparator, the negative input end of the comparator is connected with the output voltage of the negative end of the diode, the output end of the comparator is connected with the input end of the PWM generator through the error amplifier, and the output end of the PWM generator is connected with the grid electrode of the MOS tube.
Further, the power supply detection sub-circuit includes: the first resistor, the second resistor, the third resistor, the triode and the relay; wherein the triode is a PNP triode;
the first end of the first resistor is connected with the power supply voltage, the second end is grounded through the second resistor, the first resistor is connected with the power supply in parallel, the second end of the first resistor is connected with the base electrode of the triode through the third resistor, the collector electrode of the triode is connected with the power supply voltage through the coil of the relay, the emitter electrode is grounded, and the contact of the relay is connected with the input voltage acquisition sub-circuit.
Further, the MOS transistor control circuit includes: the power supply detection sub-circuit, the controller, the input voltage acquisition sub-circuit, the comparator, the error amplifier and the PWM generator;
the input end of the power supply detection sub-circuit is connected with a power supply, the output end of the power supply detection sub-circuit is connected with the input end of the controller, and the output end of the controller is connected with the control end of the input voltage acquisition sub-circuit; the input end of the input voltage acquisition sub-circuit is connected with the energy storage capacitor, the output end is connected with the positive input end of the comparator, the negative input end of the comparator is connected with the output voltage of the negative end of the diode, the output end of the comparator is connected with the input end of the PWM generator through the error amplifier, and the output end of the PWM generator is connected with the grid electrode of the MOS tube.
Further, the power supply detection sub-circuit comprises a first resistor and a second resistor;
the first end of the first resistor is connected to the power supply voltage, the second end of the first resistor is grounded through the second resistor, the first resistor is connected with the power supply in parallel, and the second end of the first resistor is connected with the input end of the controller.
In a second aspect, the present utility model provides a server, including a power board and a motherboard, where the power board accesses an output voltage to the motherboard; the server further comprises any one of the output voltage holding time extending devices, wherein the MOS tube is configured on the power panel.
Compared with the prior art, the output voltage holding time extension device and the server provided by the utility model have the following beneficial effects: and the MOS tube control circuit controls the on-off of the MOS tube according to the voltages at two ends of the energy storage capacitor and the output voltage at the negative end of the diode, and the output voltage maintaining time is increased by the boost circuit. According to the utility model, the MOS tube is added on the power supply side to form the booster circuit, so that the holding time of the output power supply is prolonged, the power supply holding time requirement is met, and only one MOS tube is added on the power panel, so that the occupied space is small, and the requirement of miniaturization of the board card is met.
Drawings
For a clearer description of embodiments of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some embodiments of the present application, and that other drawings may be obtained from these drawings by a person of ordinary skill in the art without inventive effort.
FIG. 1 is a schematic diagram of the output power supply hold time.
Fig. 2 is a schematic diagram of a typical power supply secondary side output circuit.
Fig. 3 is a schematic structural diagram of an output voltage retention time extension apparatus according to an embodiment of the utility model.
Fig. 4 is a schematic diagram of a MOS transistor control circuit of an output voltage holding time extension apparatus according to an embodiment of the present utility model.
Fig. 5 is a schematic diagram of a power supply detection sub-circuit of an output voltage holding time extension device according to an embodiment of the utility model.
Fig. 6 is a schematic diagram of a MOS transistor control circuit of an output voltage holding time extension apparatus according to a second embodiment of the present utility model.
Fig. 7 is a schematic diagram of a power supply detection sub-circuit of an output voltage retention time extension device according to a second embodiment of the present utility model.
In the figure, a P_C-energy storage capacitor, an L1-inductor, a D1-diode, an S_C-system capacitor, an R0-system resistor, an M1-MOS tube, an R1-first resistor, an R2-second resistor, an R3-third resistor, an N1-triode and a K1-relay.
Detailed Description
In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Example 1
Fig. 3 is a schematic structural diagram of an output voltage holding time extension apparatus according to a first embodiment of the present utility model, as shown in fig. 3, the apparatus includes: an energy storage capacitor P_C, an inductor L1 and a diode D1; the first end of the energy storage capacitor P_C is connected with the positive electrode of the power supply, the second end of the energy storage capacitor P_C is connected with the negative electrode of the power supply, the first end of the energy storage capacitor P_C is also connected with the first end of the inductor L1, the second end of the inductor L1 is connected with the positive electrode of the diode D1, and the negative electrode of the diode D1 outputs voltage. In addition, the equivalent circuit in the main board is composed of a system capacitor S_C and a system resistor R0.
In order to achieve the prolongation of the output voltage holding time, the embodiment is further configured with a MOS tube M1 and a MOS tube M1 control circuit, wherein the MOS tube M1 is an N-type MOS tube. The drain electrode of the MOS tube M1 is connected with the positive electrode of the diode D1, the source electrode is grounded, and the grid electrode is connected with a control circuit of the MOS tube M1; when the power supply is powered down, the MOS tube M1 control circuit obtains voltages at two ends of the energy storage capacitor P_C and output voltage at the negative end of the diode D1, and the on-off of the MOS tube M1 is controlled according to the two voltages.
In this embodiment, the MOS tube M1, the inductor L1 and the diode D1 form a boost circuit, when the power supply fails, the energy storage capacitor p_c maintains power supply, the voltage of the energy storage capacitor p_c slowly drops, and then the boost circuit raises the voltage to perform power supply maintenance, so as to increase the power supply maintenance time. When the MOS tube M1 control circuit detects that the power supply is powered down, the MOS tube M1 is controlled to be on or off according to the voltages at the two ends of the energy storage capacitor P_C and the output voltage at the negative end of the diode D1, so that the output voltage maintaining time is prolonged.
Fig. 4 is a schematic structural diagram of a MOS transistor M1 control circuit, and as shown in fig. 4, the MOS transistor M1 control circuit includes: the power supply detection sub-circuit, the input voltage acquisition sub-circuit, the comparator, the error amplifier and the PWM generator.
The input end of the power supply detection sub-circuit is connected with a power supply, and the output end of the power supply detection sub-circuit is connected with the control end of the input voltage acquisition sub-circuit; the input end of the input voltage acquisition subcircuit is connected with the energy storage capacitor P_C, the output end is connected with the positive input end of the comparator, the negative input end of the comparator is connected with the output voltage of the negative end of the diode D1, the output end of the comparator is connected with the input end of the PWM generator through the error amplifier, and the output end of the PWM generator is connected with the grid electrode of the MOS tube M1.
The power supply detection sub-circuit is used for detecting whether the power supply is powered down, when the power supply is powered down, the input voltage acquisition sub-circuit is triggered to start, voltages at two ends of the energy storage capacitor P_C are acquired, the voltages at two ends of the energy storage capacitor P_C and output voltages at the negative ends of the diode D1 are input to the comparator, the comparator is used for amplifying an error amplifier after comparison, the operation of the PWM generator is controlled, the PWM generator outputs PWM waveforms according to input control, and then the on-off state and the on-off state duration of the MOS tube M1 are controlled.
Fig. 5 is a schematic diagram of a power supply detection sub-circuit in the present embodiment, which includes a first resistor R1, a second resistor R2, a third resistor R3, a triode N1 and a relay K1, wherein the triode N1 is a PNP triode N1.
The first end of the first resistor R1 is connected with a power supply voltage, the second end is grounded through the second resistor R2, the first resistor R1 is connected with the power supply in parallel, the second end of the first resistor R1 is connected with the base electrode of the triode N1 through the third resistor R3, the collector electrode of the triode N1 is connected with the power supply voltage through the coil of the relay K1, the emitter electrode is grounded, and the contact of the relay K1 is connected with the input voltage acquisition subcircuit.
When the power supply is normal, the first resistor R1 is short-circuited, the triode N1 inputs high level and is not conducted; when the power supply is powered down, the triode N1 is input with low level and is conducted, the relay K1 is further turned on and off, the contact is closed, and the input voltage acquisition sub-circuit is conducted to start voltage acquisition.
Example two
Unlike the first embodiment, the MOS transistor M1 control circuit performs on-off control on the input voltage acquisition sub-circuit by the controller, and fig. 6 is a schematic block diagram of the MOS transistor M1 control circuit structure of the present embodiment, as shown in fig. 6, the MOS transistor M1 control circuit includes: the power supply detection sub-circuit, the controller, the input voltage acquisition sub-circuit, the comparator, the error amplifier and the PWM generator.
The input end of the power supply detection sub-circuit is connected with a power supply, the output end of the power supply detection sub-circuit is connected with the input end of the controller, and the output end of the controller is connected with the control end of the input voltage acquisition sub-circuit; the input end of the input voltage acquisition subcircuit is connected with the energy storage capacitor P_C, the output end is connected with the positive input end of the comparator, the negative input end of the comparator is connected with the output voltage of the negative end of the diode D1, the output end of the comparator is connected with the input end of the PWM generator through the error amplifier, and the output end of the PWM generator is connected with the grid electrode of the MOS tube M1.
Fig. 7 is a schematic diagram of a power supply detection sub-circuit in the present embodiment, as shown in fig. 7, the power supply detection sub-circuit includes a first resistor R1 and a second resistor R2, a first end of the first resistor R1 is connected to a power supply voltage, a second end is grounded through the second resistor R2, the first resistor R1 is connected in parallel with a power supply, and a second end of the first resistor R1 is connected to an input end of a controller.
When the power supply is normal, the first resistor R1 is short-circuited, and outputs a high level to the controller, and the controller controls the input voltage acquisition sub-circuit to be disconnected and not to operate; when the power supply is powered off, a low level is output to the controller, and the controller controls the input voltage acquisition subcircuit to conduct and run, so that voltage acquisition is started.
Example III
The embodiment provides a server, and the power panel connects the output voltage to the motherboard, and the server further includes the output voltage holding time extension device described in the first embodiment or the second embodiment, where the MOS transistor M1 is configured on the power panel.
The foregoing disclosure is merely illustrative of the preferred embodiments of the utility model and the utility model is not limited thereto, since modifications and variations may be made by those skilled in the art without departing from the principles of the utility model.
Claims (6)
1. An output voltage holding time extension apparatus comprising: an energy storage capacitor, an inductor and a diode; the device is characterized by further comprising an MOS tube and an MOS tube control circuit, wherein the MOS tube is an N-type MOS tube;
the drain electrode of the MOS tube is connected with the anode of the diode, the source electrode of the MOS tube is grounded, and the grid electrode of the MOS tube is connected with the MOS tube control circuit;
when the power supply is powered off, the MOS tube control circuit obtains the voltages at two ends of the energy storage capacitor and the output voltage at the negative end of the diode, and controls the on-off of the MOS tube according to the two voltages.
2. The output voltage holding time extension apparatus according to claim 1, wherein the MOS transistor control circuit comprises: the power supply detection sub-circuit, the input voltage acquisition sub-circuit, the comparator, the error amplifier and the PWM generator;
the input end of the power supply detection sub-circuit is connected with a power supply, and the output end of the power supply detection sub-circuit is connected with the control end of the input voltage acquisition sub-circuit; the input end of the input voltage acquisition sub-circuit is connected with the energy storage capacitor, the output end is connected with the positive input end of the comparator, the negative input end of the comparator is connected with the output voltage of the negative end of the diode, the output end of the comparator is connected with the input end of the PWM generator through the error amplifier, and the output end of the PWM generator is connected with the grid electrode of the MOS tube.
3. The output voltage holding time extension apparatus as claimed in claim 2, wherein the power supply detection sub-circuit comprises: the first resistor, the second resistor, the third resistor, the triode and the relay; wherein the triode is a PNP triode;
the first end of the first resistor is connected with the power supply voltage, the second end is grounded through the second resistor, the first resistor is connected with the power supply in parallel, the second end of the first resistor is connected with the base electrode of the triode through the third resistor, the collector electrode of the triode is connected with the power supply voltage through the coil of the relay, the emitter electrode is grounded, and the contact of the relay is connected with the input voltage acquisition sub-circuit.
4. The output voltage holding time extension apparatus according to claim 2, wherein the MOS transistor control circuit includes: the power supply detection sub-circuit, the controller, the input voltage acquisition sub-circuit, the comparator, the error amplifier and the PWM generator;
the input end of the power supply detection sub-circuit is connected with a power supply, the output end of the power supply detection sub-circuit is connected with the input end of the controller, and the output end of the controller is connected with the control end of the input voltage acquisition sub-circuit; the input end of the input voltage acquisition sub-circuit is connected with the energy storage capacitor, the output end is connected with the positive input end of the comparator, the negative input end of the comparator is connected with the output voltage of the diode negative end, the output end of the comparator is connected with the input end of the PWM generator through the error amplifier,
the output end of the PWM generator is connected with the grid electrode of the MOS tube.
5. The output voltage holding time extension apparatus according to claim 4, wherein the power supply detection sub-circuit includes a first resistor and a second resistor;
the first end of the first resistor is connected to the power supply voltage, the second end of the first resistor is grounded through the second resistor, the first resistor is connected with the power supply in parallel, and the second end of the first resistor is connected with the input end of the controller.
6. A server comprises a power panel and a main board, wherein the power panel is used for connecting output voltage to the main board; the server is characterized by further comprising the output voltage holding time prolonging device according to any one of claims 1 to 5, wherein the MOS tube is configured on the power panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320235467.9U CN219351265U (en) | 2023-02-16 | 2023-02-16 | Output voltage holding time extension device and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320235467.9U CN219351265U (en) | 2023-02-16 | 2023-02-16 | Output voltage holding time extension device and server |
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| Publication Number | Publication Date |
|---|---|
| CN219351265U true CN219351265U (en) | 2023-07-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320235467.9U Active CN219351265U (en) | 2023-02-16 | 2023-02-16 | Output voltage holding time extension device and server |
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| CN (1) | CN219351265U (en) |
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- 2023-02-16 CN CN202320235467.9U patent/CN219351265U/en active Active
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