CN219321349U

CN219321349U - MOS tube and electronic equipment

Info

Publication number: CN219321349U
Application number: CN202223613352.3U
Authority: CN
Inventors: 刘国福
Original assignee: Shenzhen Xinwangda Intelligent Technology Co ltd
Current assignee: Shenzhen Xinwangda Intelligent Technology Co ltd
Priority date: 2022-12-30
Filing date: 2022-12-30
Publication date: 2023-07-07
Anticipated expiration: 2032-12-30

Abstract

The utility model relates to the technical field of electronics, and discloses a MOS tube and electronic equipment, wherein the MOS tube comprises a MOS chip, and is provided with a first grid electrode, a second grid electrode, a first source electrode, a second source electrode, a first detection electrode and a second detection electrode; the first detection electrode is electrically connected with the first source electrode, the second detection electrode is electrically connected with the second source electrode, current flows through the first source electrode and the second source electrode, and the first detection electrode and the second detection electrode are used for detecting the internal resistance value of the MOS tube. The MOS tube is provided with the independent internal resistance signal detection end for sampling and detecting the internal resistance value of the MOS tube, so that the influence of the thickness of the copper foil of the PCB, layout wiring and production welding on the detection precision can be reduced, the detection precision is improved, and the requirements of the board factory process, design and circuit board production process are reduced.

Description

MOS tube and electronic equipment

Technical Field

The utility model relates to the technical field of electronics, in particular to a MOS tube and electronic equipment.

Background

In the field of electronic technology, the MOS transistor is generally called MOSFET (Metal Oxide Semiconductor Field EffectTransistor), i.e., a mosfet.

According to ohm's law (r=Δv/I), the current value can be calculated by detecting the voltage value and the resistance value. At present, along with the increasing of current to be detected, cost is controlled, and a low-resistance MOS tube is required to be selected in production to reduce loss. At present, the internal resistance of the ultra-low resistance MOS tube mostly reaches the level of several milliohms, and the lead resistance which is discussed less in the past becomes a factor which easily influences the sampling accuracy.

Aiming at the situation, the method generally adopted at present is to directly connect a detection line for sampling the internal resistance of the MOS tube into a source circuit of the MOS tube, so that the influence of the resistance of a lead of a PCB circuit can be eliminated, but the accuracy of the internal resistance value of the MOS tube measured by the method is not high.

Specifically, referring to fig. 1 and 2, fig. 1 is a schematic circuit connection diagram of a PCB board 200 and a MOS transistor 100 in the prior art, and fig. 2 is a schematic current flow diagram when the MOS transistor 100 is assembled on the PCB board 200. In fig. 1, a first gate line A1, a second gate line A2, a first source line B1 and a second source line B2 are disposed on a PCB 200. The first gate pad G01 of the MOS transistor 100 is electrically connected to the first gate line A1, the second gate pad G02 is electrically connected to the second gate line A2, the first source pad S01 is electrically connected to the first source line B1 through the first solder paste F1, and the second source pad S02 is electrically connected to the second source line B2 through the second solder paste F2. A detect one circuit C1 for sampling detect MOS pipe internal resistance value inserts source one circuit B1, detects two circuit C2 and inserts source two circuit B2. In operation of the device, current passes from the source (the dashed arrow in FIG. 2 indicates current), as shown in FIG. 2, and thus the total resistance R is measured _{Total (S)} ＝R _B1 +R _F1 +R _{MOS tube} +R _F2 +R _B2 。

From the above, the height of solder paste, the height of the solder joint climbing and the thickness of the copper foil of the PCB can affect the measured total resistance, i.e. the method can not accurately measure the internal resistance of the MOS tube.

Disclosure of Invention

The utility model mainly aims to provide a MOS tube and electronic equipment, and aims to solve the technical problem that the internal resistance value of the MOS tube cannot be accurately measured in the prior art.

In order to achieve the above object, the present utility model provides a MOS transistor, including:

a MOS chip provided with a first gate, a second gate, a first source, a second source, a first detection electrode, and a second detection electrode;

the first detection electrode is electrically connected with the first source electrode, the second detection electrode is electrically connected with the second source electrode, current flows through the first source electrode and the second source electrode, and the first detection electrode and the second detection electrode are used for detecting the internal resistance value of the MOS tube.

In some embodiments of the present application, the surface of the MOS chip is provided with a first pad, a second pad, a third pad, a fourth pad, a fifth pad, and a sixth pad;

the first bonding pad is correspondingly conducted with the first grid electrode, the second bonding pad is correspondingly conducted with the second grid electrode, the third bonding pad is correspondingly conducted with the first source electrode, the fourth bonding pad is correspondingly conducted with the second source electrode, the fifth bonding pad is correspondingly conducted with the first detection electrode, and the sixth bonding pad is correspondingly conducted with the second detection electrode.

In some embodiments of the present application, the fifth pad and the sixth pad are disposed on the MOS chip along a first axis, and the first axis is parallel to the current direction and coincides with a middle line of the length direction of the MOS chip.

In some embodiments of the present application, when the third pad and the fourth pad are both provided with one;

the MOS chip is divided into a first side and a second side by the first axis, the first bonding pad and the second bonding pad are arranged on the first side, and the third bonding pad and the fourth bonding pad are arranged on the second side.

In some embodiments of the present application, the first pad and the second pad are symmetrically arranged with a second axis as a symmetry axis, the third pad and the fourth pad are symmetrically arranged with the second axis as a symmetry axis, and the second axis is perpendicular to the current direction and coincides with a middle line of the MOS chip in the width direction.

In some embodiments of the present application, when the third pads and the fourth pads are equal in number and are each provided with at least two;

dividing the MOS chip into a third side and a fourth side with the second axis;

the first bonding pad and the second bonding pad are arranged on the MOS chip along the second axis;

the third bonding pad and the fifth bonding pad are arranged on the third side, and the fourth bonding pad and the sixth bonding pad are arranged on the fourth side.

In some embodiments of the present application, at least one set of the third pad and the fourth pad are disposed along the first axis and are located between the fifth pad and the sixth pad or at both ends of the fifth pad and the sixth pad along the first axis.

In some embodiments of the present application, the area of the first pad is consistent with the area of the second pad, the area of the third pad is consistent with the area of the fourth pad, the area of the fifth pad is consistent with the area of the sixth pad, and the area of the third pad is greater than the first pad, and the area of the fifth pad is equal to or less than the first pad.

In some embodiments of the present application, further comprising:

an insulating housing, in which a housing cavity is formed, in which the MOS chip is disposed;

the connecting pin penetrates through the insulating shell; the connecting pins comprise a first pin, a second pin, a third pin, a fourth pin, a fifth pin and a sixth pin;

the first pin is correspondingly conducted with the first grid electrode, the second pin is correspondingly conducted with the second grid electrode, the third pin is correspondingly conducted with the first source electrode, the fourth pin is correspondingly conducted with the second source electrode, the fifth pin is correspondingly conducted with the first detection electrode, and the sixth pin is correspondingly conducted with the second detection electrode.

In addition, in order to achieve the above purpose, the utility model also provides an electronic device, which comprises the MOS tube according to any embodiment.

According to the MOS tube and the electronic equipment provided by the utility model, the MOS tube is provided with the independent internal resistance signal detection end for sampling and detecting the internal resistance value of the MOS tube, so that the influence of the thickness of the copper foil of the PCB, layout wiring and production welding on the detection precision can be reduced, the detection precision is improved, and the requirements of the board factory process, design and circuit board production process are reduced.

Drawings

Fig. 1 is a schematic diagram of a circuit connection between a MOS transistor and a PCB in the prior art;

fig. 2 is a schematic diagram of current flow when a MOS transistor in the prior art is assembled on a PCB board;

FIG. 3 is a schematic diagram of a MOS chip of the MOS transistor of the present utility model;

fig. 4 is a schematic diagram of circuit connection between a MOS transistor and a PCB board according to the present utility model;

fig. 5 is a schematic diagram of the current flow when the MOS tube of the present utility model is assembled on a PCB board;

fig. 6 is a schematic structural diagram of a MOS transistor in embodiment 1;

fig. 7 is a schematic structural diagram of a MOS transistor in embodiment 2;

FIG. 8 is a cross-sectional view of FIG. 7 along a first axis;

fig. 9 is a schematic structural diagram of a MOS transistor in embodiment 3;

FIG. 10 is a cross-sectional view of FIG. 9 along a first axis;

fig. 11 is a schematic diagram of the internal structure of the MOS transistor of embodiment 4.

The achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

It should be noted that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance, order, or number of such features, i.e., a "first" feature may be referred to as a "second" feature, a "second" feature may also be referred to as a "first" feature, and a feature defining "first," "second" may explicitly or implicitly include one or more such features. In addition, unless otherwise indicated, the meaning of "a plurality" is two or more.

It is emphasized that in the description of this application, unless clearly indicated and defined otherwise, the term "connected" is to be interpreted broadly, e.g. as either a fixed connection, a removable connection, or a unitary connection; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

Referring to fig. 3, the present utility model provides a MOS transistor 10, which mainly includes a MOS chip 1, and is provided with a first gate G1, a second gate G2, a first source S1, a second source S2, a first detection electrode T1, and a second detection electrode T2.

The first detection electrode T1 is electrically connected with the first source electrode S1, the second detection electrode T2 is electrically connected with the second source electrode S2, current flows through the first source electrode S1 and the second source electrode S2, and the first detection electrode T1 and the second detection electrode T2 are used for detecting an internal resistance value of the MOS transistor.

That is, the MOS tube provided by the application is provided with an independent detection access end for detecting the internal resistance value of the MOS tube.

Referring to fig. 4, fig. 4 is a schematic circuit connection diagram of a MOS transistor 10 and a PCB board 20 of the present application, the PCB board 20 is provided with a first gate line a10, a second gate line a20, a first source line B10, a second source line B20, a first detection line C10 and a second detection line C20, the first gate line a10 is electrically connected with a first gate G1, the second gate line a20 is electrically connected with a second gate G2, the first source line B10 is electrically connected with a first source S1, the second source line B20 is electrically connected with a second source S2, the first detection line C10 is electrically connected with a first detection electrode T1, and the second detection line C20 is electrically connected with a second detection electrode T2.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating a current flow direction when the MOS transistor 10 of the present utility model is assembled on the PCB 20, and the current flows through the first source S1 and the second source S2, and does not flow through the first detection electrode T1 and the second detection electrode T2, so that a total resistance R is measured _{Total =} R _{MOS tube} 。

The application provides a MOS pipe is provided with independent internal resistance signal detection end for the internal resistance value of sampling detection MOS pipe can reduce PCB board copper foil thickness, layout wiring, production welding to the influence of detection precision, has improved detection precision, and has reduced the requirement to board factory technology, design, circuit board production process.

In the technical scheme of the application, each electrode can be electrically connected with the PCB board through a bonding pad or a pin or other electrical connection structures, and the number of the electrical connection structures corresponding to the first source S1 and the second source S2 can be more than one, which is described in detail below through specific embodiments.

Example 1

Referring to fig. 6, the MOS transistor of the present embodiment mainly includes a MOS chip 1, which is provided with a first gate G1, a second gate G2, a first source S1, a second source S2, a first detection electrode T1, and a second detection electrode T2; the first detection electrode T1 is electrically connected to the first source electrode S1, and the second detection electrode T2 is electrically connected to the second source electrode S2.

The surface of the MOS chip 1 is provided with a first pad G10, a second pad G20, a third pad S10, a fourth pad S20, a fifth pad T10 and a sixth pad T20, and both the third pad and the fourth pad S20 are provided with one.

The first bonding pad G10 is correspondingly conducted with the first gate G1, the second bonding pad G20 is correspondingly conducted with the second gate G2, the third bonding pad S10 is correspondingly conducted with the first source S1, the fourth bonding pad S20 is correspondingly conducted with the second source S2, the fifth bonding pad T10 is correspondingly conducted with the first detecting electrode T1, and the sixth bonding pad T20 is correspondingly conducted with the second detecting electrode T2.

For the sake of clarity of the description, fig. 6 shows a first axis X and a second axis Y on the MOS chip 1, where the first axis X and the second axis Y are virtual auxiliary lines for describing the orientation, and are not line structures actually existing on the MOS chip 1. The first axis X is parallel to the current direction and coincides with a middle line of the MOS chip 1 in the length direction (i.e., a dotted line denoted by X in the figure), and the second axis Y is perpendicular to the current direction and coincides with a middle line of the MOS chip 1 in the width direction (i.e., a dotted line denoted by Y in the figure).

The MOS chip 1 is divided into a first side and a second side with the first axis X.

The fifth pad T10 and the sixth pad T20 are disposed on the MOS chip 1 along the first axis X, which is advantageous for further improving the detection accuracy.

The first bonding pad G10 and the second bonding pad G20 are both disposed on the first side, and the first bonding pad G10 and the second bonding pad G20 are symmetrically disposed with the second axis Y as a symmetry axis.

The third pad S10 and the fourth pad S20 are both disposed on the second side, and the third pad S10 and the fourth pad S20 are symmetrically disposed with the second axis Y as a symmetry axis.

The positioning of the bonding pads is beneficial to simplifying the wiring requirement of the circuit board while ensuring the detection precision.

The area of the first pad G10 is consistent with the area of the second pad G20, the area of the third pad S10 is consistent with the area of the fourth pad S20, the area of the fifth pad T10 is consistent with the area of the sixth pad T20, and the area of the third pad S10 is greater than the first pad G10, and the area of the fifth pad T10 is equal to or less than the first pad G10.

The first pad G10 and the second pad G20 may have a circular shape, and the first pad G10 may have a diameter of about 0.3mm to ensure a stable electrical connection with the PCB panel by soldering. The third pad S10 and the fourth pad S20 may have a strip shape with an area greater than 0.3mm, so as to ensure the passage of a large current. Since no current passes, only for sampling and detecting the internal resistance value, the area of the fifth pad T10 may be small, and in order to ensure that a stable electrical connection with the PCB panel is formed by soldering, a value close to the area of the first pad G10 may be taken.

Example 2

This embodiment differs from embodiment 1 in that: the number of the third pads S10 and the fourth pads S20, and the positional arrangement of the respective pads.

Referring to fig. 7, the MOS transistor of the present embodiment mainly includes a MOS chip 1 provided with a first gate G1, a second gate G2, a first source S1, a second source S2, a first detection electrode T1, and a second detection electrode T2; the first detection electrode T1 is electrically connected to the first source electrode S1, and the second detection electrode T2 is electrically connected to the second source electrode S2.

The surface of the MOS chip 1 is provided with a first bonding pad G10, a second bonding pad G20, a third bonding pad S10, a fourth bonding pad S20, a fifth bonding pad T10 and a sixth bonding pad T20, and the number of the third bonding pads S10 is equal to that of the fourth bonding pads S20 and at least two bonding pads are arranged.

In this embodiment, three third pads S10 and three fourth pads S20 are respectively provided, and in fig. 7, three third pads S10 are respectively denoted by reference numerals S10-1, S10-2 and S10-3, and three fourth pads S20 are respectively denoted by reference numerals S20-1, S20-2 and S20-3.

For the sake of clarity of the description, fig. 7 shows a first axis X and a second axis Y on the MOS chip 1, where the first axis X and the second axis Y are virtual auxiliary lines for describing the orientation, and are not line structures actually existing on the MOS chip 1. The first axis X is parallel to the current direction and coincides with a middle line of the MOS chip 1 in the length direction (i.e., a dotted line denoted by X in the figure), and the second axis Y is perpendicular to the current direction and coincides with a middle line of the MOS chip 1 in the width direction (i.e., a dotted line denoted by Y in the figure).

The MOS chip 1 is divided into a third side and a fourth side with the second axis Y.

The first bonding pad G10 and the second bonding pad G20 are both disposed on the MOS chip 1 along the second axis Y, and are symmetrically disposed with the first axis X as a symmetry axis.

The third bonding pad S10 is disposed on the third side, the fourth bonding pad S20 is disposed on the fourth side, the second axis Y is symmetrically disposed with respect to the symmetry axis, and at least one group of the third bonding pad S10 and the fourth bonding pad S20 are disposed on the MOS chip 1 along the first axis X. In this embodiment, the third pad S10-2 and the fourth pad S20-2 are disposed on the MOS chip 1 along the first axis X.

The fifth pad T10 and the sixth pad T20 are disposed on the MOS chip 1 along the first axis X, which is advantageous for further improving the detection accuracy. And, the fifth pad T10 is disposed on the third side, and the sixth pads T20 are disposed on the fourth side and are symmetrically disposed with the first axis X as a symmetry axis.

The third pad S10-2 and the fourth pad S20-2 are located between the fifth pad T10 and the sixth pad T20.

The limitation of the shape and area of each pad in this embodiment may be the same as that in embodiment 1.

Referring to fig. 8, fig. 8 is a cross-sectional view of the first axis X in fig. 7, the MOS chip 1 is sequentially provided with a back gold layer 101, a silicon layer 102, a passivation layer 103 and an insulating layer 104 from bottom to top along the axial direction thereof, and the structure and materials used are consistent with those of the MOS chip in the prior art.

Example 3

This embodiment differs from embodiment 2 in that: the positions of the third pad S10-2, the fourth pad S20-2, the fifth pad T10 and the sixth pad T20 are arranged.

Referring to fig. 9, in the MOS transistor of the present embodiment, the third pad S10-2 and the fourth pad S20-2 are located at two ends of the fifth pad T10 and the sixth pad T20 along the first axis X, that is, the fifth pad T10 and the sixth pad T20 are located between the third pad S10-2 and the fourth pad S20-2.

Fig. 10 is a cross-sectional view of the first axis X of fig. 9.

Example 4

Referring to fig. 11, the MOS transistor of the present embodiment mainly includes a MOS chip 1, an insulating housing 2, and connection pins.

The inside of the insulating housing 2 forms a housing cavity in which the MOS chip 1 is disposed.

The MOS chip 1 is provided with a first grid G1, a second grid G2, a first source S1, a second source S2, a first detection electrode T1 and a second detection electrode T2; the first detection electrode T1 is electrically connected to the first source electrode S1, and the second detection electrode T2 is electrically connected to the second source electrode S2.

The connecting pins penetrate through the insulating shell 2. The connection pins include a first pin G11, a second pin G21, a third pin S11, a fourth pin S21, a fifth pin T11, and a sixth pin T21.

The first pin G11 is correspondingly conducted with the first gate G1, the second pin G21 is correspondingly conducted with the second gate G2, the third pin S11 is correspondingly conducted with the first source S1, the fourth pin S21 is correspondingly conducted with the second source S2, the fifth pin T11 is correspondingly conducted with the first detecting electrode T1, and the sixth pin T21 is correspondingly conducted with the second detecting electrode T2.

In this embodiment, two third pins S11 and two fourth pins S21 are respectively provided, two third pins S11 are respectively denoted by reference numerals S11-1 and S11-2, and two fourth pins S21 are respectively denoted by reference numerals S21-1 and S21-2.

With the view angle shown in fig. 11, the first pin G11, the fifth pin T11, the third pin S11-1 and the third pin S11-2 are all disposed on the left side of the insulating housing 2 and are sequentially arranged at equal intervals from top to bottom. The second pin G21, the sixth pin T21, the fourth pin S21-1 and the fourth pin S21-2 are all disposed on the right side of the insulating housing 2, and are sequentially arranged at equal intervals from top to bottom.

The positioning of the pins is beneficial to simplifying the wiring requirement of the circuit board while ensuring the detection precision.

In summary, compared with the prior art, the MOS tube and the electronic device provided by the utility model have the advantages that the independent internal resistance signal detection end is arranged for sampling and detecting the internal resistance value of the MOS tube, so that the influence of the thickness of the copper foil of the PCB, layout wiring and production welding on the detection precision can be reduced, the detection precision is improved, and the requirements of the board factory process, design and circuit board production process are reduced.

The foregoing description is only of the preferred embodiments of the present utility model, and is not intended to limit the scope of the utility model, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims

1. A MOS transistor, comprising:

a MOS chip (1) provided with a first gate (G1), a second gate (G2), a first source (S1), a second source (S2), a first detection electrode (T1), and a second detection electrode (T2);

the first detection electrode (T1) is electrically connected with the first source electrode (S1), the second detection electrode (T2) is electrically connected with the second source electrode (S2), current flows through the first source electrode (S1) and the second source electrode (S2), and the first detection electrode (T1) and the second detection electrode (T2) are used for detecting the internal resistance value of the MOS tube.

2. The MOS transistor of claim 1, wherein:

the surface of the MOS chip (1) is provided with a first bonding pad (G10), a second bonding pad (G20), a third bonding pad (S10), a fourth bonding pad (S20), a fifth bonding pad (T10) and a sixth bonding pad (T20);

the first bonding pad (G10) is correspondingly conducted with the first grid electrode (G1), the second bonding pad (G20) is correspondingly conducted with the second grid electrode (G2), the third bonding pad (S10) is correspondingly conducted with the first source electrode (S1), the fourth bonding pad (S20) is correspondingly conducted with the second source electrode (S2), the fifth bonding pad (T10) is correspondingly conducted with the first detection electrode (T1), and the sixth bonding pad (T20) is correspondingly conducted with the second detection electrode (T2).

3. The MOS transistor of claim 2, wherein:

the fifth bonding pad (T10) and the sixth bonding pad (T20) are arranged on the MOS chip (1) along a first axis (X), and the first axis (X) is parallel to the current direction and coincides with the central line of the length direction of the MOS chip (1).

4. A MOS transistor according to claim 3, characterized in that:

when the third pad (S10) and the fourth pad (S20) are provided with one;

the MOS chip (1) is divided into a first side and a second side by the first axis (X), the first bonding pad (G10) and the second bonding pad (G20) are arranged on the first side, and the third bonding pad (S10) and the fourth bonding pad (S20) are arranged on the second side.

5. The MOS transistor of claim 4, wherein:

the first bonding pads (G10) and the second bonding pads (G20) are symmetrically arranged by taking a second axis (Y) as a symmetry axis, the third bonding pads (S10) and the fourth bonding pads (S20) are symmetrically arranged by taking the second axis (Y) as a symmetry axis, and the second axis (Y) is perpendicular to the current direction and coincides with a central line of the MOS chip (1) in the width direction.

6. The MOS transistor of claim 5, wherein:

when the number of the third bonding pads (S10) and the fourth bonding pads (S20) are equal and at least two bonding pads are arranged;

dividing the MOS chip (1) into a third side and a fourth side with the second axis (Y);

the first bonding pad (G10) and the second bonding pad (G20) are arranged on the MOS chip (1) along the second axis (Y);

the third bonding pad (S10) and the fifth bonding pad (T10) are both disposed on the third side, and the fourth bonding pad (S20) and the sixth bonding pad (T20) are both disposed on the fourth side.

7. The MOS transistor of claim 6, wherein:

at least one set of the third pad (S10) and the fourth pad (S20) is disposed along the first axis (X) and is located between the fifth pad (T10) and the sixth pad (T20) or at both ends of the fifth pad (T10) and the sixth pad (T20) along the first axis (X).

8. A MOS transistor according to claim 3, characterized in that:

the area of the first bonding pad (G10) is consistent with the area of the second bonding pad (G20), the area of the third bonding pad (S10) is consistent with the area of the fourth bonding pad (S20), the area of the fifth bonding pad (T10) is consistent with the area of the sixth bonding pad (T20), the area of the third bonding pad (S10) is larger than the area of the first bonding pad (G10), and the area of the fifth bonding pad (T10) is equal to or smaller than the area of the first bonding pad (G10).

9. The MOS transistor of claim 1, further comprising:

an insulating housing (2) having a housing cavity formed therein, the MOS chip (1) being disposed in the housing cavity;

the connecting pin penetrates through the insulating shell (2); the connection pins comprise a first pin (G11), a second pin (G21), a third pin (S11), a fourth pin (S21), a fifth pin (T11) and a sixth pin (T21);

the first pin (G11) is correspondingly conducted with the first grid electrode (G1), the second pin (G21) is correspondingly conducted with the second grid electrode (G2), the third pin (S11) is correspondingly conducted with the first source electrode (S1), the fourth pin (S21) is correspondingly conducted with the second source electrode (S2), the fifth pin (T11) is correspondingly conducted with the first detection electrode (T1), and the sixth pin (T21) is correspondingly conducted with the second detection electrode (T2).

10. An electronic device comprising the MOS transistor according to any one of claims 1 to 9.