CN219107425U - Bootstrap switch sampling circuit, bootstrap switch and data conversion system - Google Patents
Bootstrap switch sampling circuit, bootstrap switch and data conversion system Download PDFInfo
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- CN219107425U CN219107425U CN202223582197.3U CN202223582197U CN219107425U CN 219107425 U CN219107425 U CN 219107425U CN 202223582197 U CN202223582197 U CN 202223582197U CN 219107425 U CN219107425 U CN 219107425U
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
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Abstract
The utility model discloses a bootstrap switch sampling circuit, a bootstrap switch and a data conversion system, wherein the bootstrap switch sampling circuit comprises: the first P-type MOS tube PM1, the second P-type MOS tube PM2, the third P-type MOS tube PM3, the fourth P-type MOS tube PM4, the fifth P-type MOS tube PM5, the first N-type MOS tube NM1, the second N-type MOS tube NM2, the third N-type MOS tube NM3, the fourth N-type MOS tube NM4, the fifth N-type MOS tube NM5, the sixth N-type MOS tube NM6, the seventh N-type MOS tube NM7, the eighth N-type MOS tube NM8 and the capacitor Cs. The bootstrap switch sampling circuit, the bootstrap switch and the data conversion system provided by the utility model can realize that the sampling resistor is set with a constant value, and meanwhile, the charge fed to the sampling capacitor from the positive end and the negative end is ensured to be equivalent; the utility model can improve the accuracy of data conversion.
Description
Technical Field
The utility model belongs to the technical field of electronic circuits, and relates to a sampling circuit, in particular to a bootstrap switch sampling circuit, a bootstrap switch and a data conversion system.
Background
The speed and precision of the analog signal sampling part in the data conversion system (AD/DA) determine the overall speed and precision of the system, however, the on-resistance of the sampling switch realized by the MOS tube changes along with the change of the amplitude of the input signal, and in order to realize constant on-resistance, a sampling circuit named a bootstrap switch has been developed, and the basic principle is that a constant voltage drop is applied between the grid electrode and the source electrode of the switching MOS tube during sampling.
A conventional bootstrap switch sampling circuit is shown in fig. 1; referring to fig. 1, the conventional bootstrap switch sampling circuit operates as follows: when clk is at a low level and clkb is at a high level, the second P-type MOS tube PM2 and the sixth N-type MOS tube NM6 are conducted, the third P-type MOS tube PM3 and the fourth N-type MOS tube NM4 are turned off, and VDD charges the capacitor Cs to VDD; meanwhile, the first N-type MOS transistor NM1 and the fourth P-type MOS transistor PM4 are turned on, and the clk_h level is pulled to the ground.
When clk is high level and clkb is low level, the second P-type MOS tube PM2 and the sixth N-type MOS tube NM6 are turned off, the third P-type MOS tube PM3 and the fourth N-type MOS tube NM4 are conducted, and an input signal is superimposed on the capacitor Cs through the fourth N-type MOS tube NM4, so that the voltage value of the positive end of the capacitor Cs reaches VDD+vsig (Vsig is the signal amplitude); and then the Clk_h is pulled up to VDD+vsig through the third P-type MOS transistor PM 3. Therefore, when the signal passes through the fifth N-type MOS tube NM5 of the sampling switch, the gate-source voltage of the sampling tube is always kept at VDD, so that the constant value of the sampling resistor is realized.
However, this circuit configuration implements a bootstrap sampling clock because the clock peak to peak value applied to the sampling switch MOS transistor varies with the amplitude of the input signal, which results in the charge being fed through to the sampling capacitor also varying with the signal amplitude. In differential applications, the difference in charge fed to the positive and negative sampling capacitors is not a fixed value, but a value that varies with the signal; therefore, signal harmonics are superimposed on the sampling capacitance, resulting in a decrease in the accuracy of data conversion.
In view of this, there is an urgent need to design a new bootstrap switch sampling circuit to overcome at least some of the above-mentioned drawbacks of the existing bootstrap switch sampling circuits.
Disclosure of Invention
The utility model provides a bootstrap switch sampling circuit, a bootstrap switch and a data conversion system, which can realize that the sampling resistor is set with a constant value, ensure that the charge fed to a sampling capacitor from the positive end and the negative end is equivalent, and improve the accuracy of data conversion.
In order to solve the technical problems, according to one aspect of the present utility model, the following technical scheme is adopted:
a bootstrapped switch sampling circuit, the bootstrapped switch sampling circuit comprising: the first P-type MOS tube PM1, the second P-type MOS tube PM2, the third P-type MOS tube PM3, the fourth P-type MOS tube PM4, the fifth P-type MOS tube PM5, the first N-type MOS tube NM1, the second N-type MOS tube NM2, the third N-type MOS tube NM3, the fourth N-type MOS tube NM4, the fifth N-type MOS tube NM5, the sixth N-type MOS tube NM6, the seventh N-type MOS tube NM7, the eighth N-type MOS tube NM8 and the capacitor Cs;
the grid electrode of the first P-type MOS tube PM1 is respectively connected with the grid electrode of the Clk signal and the grid electrode of the second N-type MOS tube NM2, and the source electrode of the first P-type MOS tube PM1 is respectively connected with the source electrode of the VDD signal and the source electrode of the second P-type MOS tube PM 2; the drain electrode of the first P-type MOS tube PM1 is respectively connected with the drain electrode of the second N-type MOS tube NM2, the grid electrode of the third P-type MOS tube PM3, the drain electrode of the third N-type MOS tube NM3 and the grid electrode of the fifth P-type MOS tube PM 5;
the drain electrode of the second P-type MOS tube PM2 is respectively connected with the drain electrode of the third P-type MOS tube PM3 and the first end of the capacitor Cs; the grid electrode of the second P-type MOS tube PM2 is respectively connected with the grid electrode of the third N-type MOS tube NM3, the grid electrode of the fourth P-type MOS tube PM4, the drain electrode of the fifth P-type MOS tube PM5, the grid electrode of the fourth N-type MOS tube NM4 and the drain electrode of the seventh N-type MOS tube NM 7;
the source electrode of the third P-type MOS tube PM3 is respectively connected with the source electrode of the first N-type MOS tube NM1, the drain electrode of the fourth P-type MOS tube PM4, the source electrode of the fifth P-type MOS tube PM5 and the grid electrode of the fifth N-type MOS tube NM 5;
the source electrode of the fourth P-type MOS tube PM4 is respectively connected with a Sig_in signal and the drain electrode of the first N-type MOS tube NM 1; the grid electrode of the first N-type MOS tube NM1 is connected with a Clkb signal;
the source electrode of the second N-type MOS tube NM2 is respectively connected with the second end of the capacitor Cs, the source electrode of the third N-type MOS tube NM3, the source electrode of the fourth N-type MOS tube NM4 and the drain electrode of the sixth N-type MOS tube NM 6;
the drain electrode of the fourth N-type MOS tube NM4 is respectively connected with a Sig_in signal and the source electrode of the fifth N-type MOS tube NM 5; the drain electrode of the fifth N-type MOS tube NM5 is connected with a Sig_out signal;
the grid electrode of the sixth N-type MOS tube NM6 is connected with a Clkb signal, and the emitter electrode of the sixth N-type MOS tube NM6 is grounded;
the grid electrode of the seventh N-type MOS tube NM7 is connected with a VDD signal, and the emitter electrode of the seventh N-type MOS tube NM7 is connected with the drain electrode of the eighth N-type MOS tube NM 8; and the grid electrode of the eighth N-type MOS tube NM8 is connected with a Clkb signal, and the emitter electrode of the eighth N-type MOS tube NM8 is grounded.
As one embodiment of the present utility model, VDD is a high voltage signal, clk is a normal clock signal, clkb is an inversion signal of clk, clk_h and clk_h_o are boosted clock signals, sig_in is an input signal, and sig_out is an output signal sampled by a bootstrap switch sampling circuit.
According to another aspect of the utility model, the following technical scheme is adopted: a bootstrap switch comprising the bootstrap switch sampling circuit described above.
According to another aspect of the utility model, the following technical scheme is adopted: a data conversion system comprising the bootstrap switch sampling circuit described above.
The utility model has the beneficial effects that: the bootstrap switch sampling circuit, the bootstrap switch and the data conversion system provided by the utility model can realize that the sampling resistor is set with a constant value, and meanwhile, the charge fed to the sampling capacitor from the positive end and the negative end is ensured to be equivalent; the utility model can improve the accuracy of data conversion.
Drawings
Fig. 1 is a circuit schematic diagram of a conventional bootstrap switch sampling circuit.
Fig. 2 is a schematic circuit diagram of a bootstrap switch sampling circuit in accordance with an embodiment of the present utility model.
Fig. 3 is a schematic diagram of a conventional bootstrap control clock signal.
Fig. 4 is an enlarged detail view of the clock signal shown in fig. 3.
FIG. 5 is a diagram of a bootstrap control clock signal in accordance with an embodiment of the present utility model.
Fig. 6 is an enlarged detail view of the clock signal shown in fig. 5.
Detailed Description
Preferred embodiments of the present utility model will be described in detail below with reference to the accompanying drawings.
For a further understanding of the present utility model, preferred embodiments of the utility model are described below in conjunction with the examples, but it should be understood that these descriptions are merely intended to illustrate further features and advantages of the utility model, and are not limiting of the claims of the utility model.
The description of this section is intended to be illustrative of only a few exemplary embodiments and the utility model is not to be limited in scope by the description of the embodiments. It is also within the scope of the description and claims of the utility model to interchange some of the technical features of the embodiments with other technical features of the same or similar prior art.
The description of the steps in the various embodiments in the specification is merely for convenience of description, and the implementation of the present application is not limited by the order in which the steps are implemented.
"connected" in the specification includes both direct and indirect connections, such as through some active, passive, or electrically conductive medium; connections through other active or passive devices, such as through switches, follower circuits, etc. circuits or components, may be included as known to those skilled in the art, on the basis of achieving the same or similar functional objectives.
The utility model discloses a bootstrap switch sampling circuit, and FIG. 2 is a schematic diagram of a bootstrap switch sampling circuit in an embodiment of the utility model; referring to fig. 2, the bootstrap switch sampling circuit includes: the first P-type MOS tube PM1, the second P-type MOS tube PM2, the third P-type MOS tube PM3, the fourth P-type MOS tube PM4, the fifth P-type MOS tube PM5, the first N-type MOS tube NM1, the second N-type MOS tube NM2, the third N-type MOS tube NM3, the fourth N-type MOS tube NM4, the fifth N-type MOS tube NM5, the sixth N-type MOS tube NM6, the seventh N-type MOS tube NM7, the eighth N-type MOS tube NM8 and the capacitor Cs.
The grid electrode of the first P-type MOS tube PM1 is respectively connected with the grid electrode of the Clk signal and the grid electrode of the second N-type MOS tube NM2, and the source electrode of the first P-type MOS tube PM1 is respectively connected with the source electrode of the VDD signal and the source electrode of the second P-type MOS tube PM 2; the drain electrode of the first P-type MOS tube PM1 is respectively connected with the drain electrode of the second N-type MOS tube NM2, the grid electrode of the third P-type MOS tube PM3, the drain electrode of the third N-type MOS tube NM3 and the grid electrode of the fifth P-type MOS tube PM 5.
The drain electrode of the second P-type MOS tube PM2 is respectively connected with the drain electrode of the third P-type MOS tube PM3 and the first end of the capacitor Cs; the grid electrode of the second P-type MOS tube PM2 is respectively connected with the grid electrode of the third N-type MOS tube NM3, the grid electrode of the fourth P-type MOS tube PM4, the drain electrode of the fifth P-type MOS tube PM5, the grid electrode of the fourth N-type MOS tube NM4 and the drain electrode of the seventh N-type MOS tube NM 7.
The source electrode of the third P-type MOS tube PM3 is respectively connected with the source electrode of the first N-type MOS tube NM1, the drain electrode of the fourth P-type MOS tube PM4, the source electrode of the fifth P-type MOS tube PM5 and the grid electrode of the fifth N-type MOS tube NM 5. The source electrode of the fourth P-type MOS tube PM4 is respectively connected with a Sig_in signal and the drain electrode of the first N-type MOS tube NM 1; the grid electrode of the first N-type MOS tube NM1 is connected with a Clkb signal. The source electrode of the second N-type MOS transistor NM2 is connected to the second end of the capacitor Cs, the source electrode of the third N-type MOS transistor NM3, the source electrode of the fourth N-type MOS transistor NM4, and the drain electrode of the sixth N-type MOS transistor NM6, respectively.
The drain electrode of the fourth N-type MOS tube NM4 is respectively connected with a Sig_in signal and the source electrode of the fifth N-type MOS tube NM 5; and the drain electrode of the fifth N-type MOS tube NM5 is connected with a Sig_out signal. The grid electrode of the sixth N-type MOS tube NM6 is connected with a Clkb signal, and the emitter electrode of the sixth N-type MOS tube NM6 is grounded.
The grid electrode of the seventh N-type MOS tube NM7 is connected with a VDD signal, and the emitter electrode of the seventh N-type MOS tube NM7 is connected with the drain electrode of the eighth N-type MOS tube NM 8; and the grid electrode of the eighth N-type MOS tube NM8 is connected with a Clkb signal, and the emitter electrode of the eighth N-type MOS tube NM8 is grounded.
In one embodiment of the utility model, VDD is a high voltage, clk is a normal clock signal, clkb is an inverted signal of clk, clk_h and clk_h_o are boosted clock signals, sig_in is an input signal, and sig_out is an output signal sampled by a bootstrap switch sampling circuit.
In an embodiment of the present utility model, unlike the conventional bootstrap switch sampling circuit, the MOS transistor M8 is replaced by a P transistor by N transistors, when clk_h is pulled down, it is not pulled to ground any more, but is pulled to be consistent with the signal level, and the added MOS transistors (seventh N-type MOS transistor NM7, eighth N-type MOS transistor NM 8) complete the functions of the original first N-type MOS transistors NM1 and M8, and the added fifth P-type MOS transistor PM5 realizes the isolation of the new bootstrap control clock from the original bootstrap control clock.
The utility model also discloses a sampling control method of the bootstrap switch sampling circuit, which comprises the following steps:
in the state that the Clk signal is low level and the Clkb signal is high level, the second P-type MOS tube PM2 and the sixth N-type MOS tube NM6 are conducted, the third P-type MOS tube PM3 and the fourth N-type MOS tube NM4 are turned off, and the capacitor Cs is charged by the power supply voltage VDD until the corresponding value of the power supply voltage VDD is reached; meanwhile, the first N-type MOS tube NM1 and the fourth P-type MOS tube PM4 are conducted, the level of the Clk_h signal is pulled to the input level of the Sig_in signal, the seventh N-type MOS tube NM7 and the eighth N-type MOS tube NM8 are conducted, the Clk_h_o signal is pulled down to the ground, at the moment, the fifth P-type MOS tube PM5 is turned off, and the Clk_h signal and the Clk_h_o signal are isolated;
in the state that the Clk signal is high level and the Clkb signal is low level, the second P-type MOS tube PM2 and the sixth N-type MOS tube NM6 are turned off, and the third P-type MOS tube PM3 and the fourth N-type MOS tube NM4 are turned on; the input signal Sig_in signal is superimposed on the capacitor Cs through the fourth N-type MOS tube NM4, so that the voltage value of the positive end on the capacitor Cs reaches the sum of the voltage value of the power supply voltage VDD and the signal amplitude of the input signal Sig_in; then the Clk_h signal is pulled up to the sum of the voltage value of the power supply voltage VDD and the signal amplitude of the input signal Sig_in through a third P-type MOS tube PM 3; meanwhile, the fifth P-type MOS tube PM5 is conducted, and the Clk_h_o signal is also pulled to the level corresponding to the sum of the voltage value of the power supply voltage VDD and the signal amplitude of the input signal Sig_in;
when a signal passes through the fifth N-type MOS tube NM5 of the sampling switch, the gate-source voltage of the fifth N-type MOS tube NM5 is always kept at a voltage value corresponding to the power supply voltage VDD, and meanwhile, the amplitude change of the control clock is also always kept at the voltage value corresponding to the power supply voltage VDD; the constant value of the sampling resistor is realized, and the charge fed to the sampling capacitor from the positive end and the negative end is ensured to be equivalent.
FIG. 3 is a schematic diagram of a conventional bootstrap control clock signal, and FIG. 4 is an enlarged detail view of the clock signal shown in FIG. 3; fig. 5 is a schematic diagram of a bootstrap control clock signal in an embodiment of the utility model, and fig. 6 is an enlarged detail view of the clock signal shown in fig. 5. As can be seen from a comparison of fig. 3 to 6, the present utility model can eliminate the prior bootstrap switch sampling circuit
The defect that the charge on the sampling capacitor changes along with the amplitude of the signal (because the charge difference value fed to the sampling capacitor at the positive and negative ends is not a fixed value but a value which changes along with the signal) avoids the superposition of signal harmonic waves on the sampling capacitor, thereby improving the accuracy of data conversion.
The utility model further discloses a bootstrap switch, which comprises the bootstrap switch sampling circuit.
The utility model also discloses a data conversion system which comprises the bootstrap switch sampling circuit.
In summary, the bootstrap switch sampling circuit, the bootstrap switch and the data conversion system provided by the utility model can realize that the sampling resistor sets a constant value and simultaneously ensure that the charge fed to the sampling capacitor from the positive end and the negative end is equivalent; the utility model can improve the accuracy of data conversion.
It should be noted that the present application may be implemented in software and/or a combination of software and hardware; for example, an Application Specific Integrated Circuit (ASIC), a general purpose computer, or any other similar hardware device may be employed. In some embodiments, the software programs of the present application may be executed by a processor to implement the above steps or functions. Likewise, the software programs of the present application (including related data structures) may be stored in a computer-readable recording medium; such as RAM memory, magnetic or optical drives or diskettes, and the like. In addition, some steps or functions of the present application may be implemented in hardware; for example, as circuitry that cooperates with the processor to perform various steps or functions.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The description and applications of the present utility model herein are illustrative and are not intended to limit the scope of the utility model to the embodiments described above. Effects or advantages referred to in the embodiments may not be embodied in the embodiments due to interference of various factors, and description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternatives and equivalents of the various components of the embodiments are known to those of ordinary skill in the art. It will be clear to those skilled in the art that the present utility model may be embodied in other forms, structures, arrangements, proportions, and with other assemblies, materials, and components, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the utility model.
Claims (3)
1. A bootstrap switch sampling circuit, said bootstrap switch sampling circuit comprising: the first P-type MOS tube PM1, the second P-type MOS tube PM2, the third P-type MOS tube PM3, the fourth P-type MOS tube PM4, the fifth P-type MOS tube PM5, the first N-type MOS tube NM1, the second N-type MOS tube NM2, the third N-type MOS tube NM3, the fourth N-type MOS tube NM4, the fifth N-type MOS tube NM5, the sixth N-type MOS tube NM6, the seventh N-type MOS tube NM7, the eighth N-type MOS tube NM8 and the capacitor Cs;
the grid electrode of the first P-type MOS tube PM1 is respectively connected with the grid electrode of the Clk signal and the grid electrode of the second N-type MOS tube NM2, and the source electrode of the first P-type MOS tube PM1 is respectively connected with the source electrode of the VDD signal and the source electrode of the second P-type MOS tube PM 2; the drain electrode of the first P-type MOS tube PM1 is respectively connected with the drain electrode of the second N-type MOS tube NM2, the grid electrode of the third P-type MOS tube PM3, the drain electrode of the third N-type MOS tube NM3 and the grid electrode of the fifth P-type MOS tube PM 5;
the drain electrode of the second P-type MOS tube PM2 is respectively connected with the drain electrode of the third P-type MOS tube PM3 and the first end of the capacitor Cs; the grid electrode of the second P-type MOS tube PM2 is respectively connected with the grid electrode of the third N-type MOS tube NM3, the grid electrode of the fourth P-type MOS tube PM4, the drain electrode of the fifth P-type MOS tube PM5, the grid electrode of the fourth N-type MOS tube NM4 and the drain electrode of the seventh N-type MOS tube NM 7;
the source electrode of the third P-type MOS tube PM3 is respectively connected with the source electrode of the first N-type MOS tube NM1, the drain electrode of the fourth P-type MOS tube PM4, the source electrode of the fifth P-type MOS tube PM5 and the grid electrode of the fifth N-type MOS tube NM 5;
the source electrode of the fourth P-type MOS tube PM4 is respectively connected with a Sig_in signal and the drain electrode of the first N-type MOS tube NM 1; the grid electrode of the first N-type MOS tube NM1 is connected with a Clkb signal;
the source electrode of the second N-type MOS tube NM2 is respectively connected with the second end of the capacitor Cs, the source electrode of the third N-type MOS tube NM3, the source electrode of the fourth N-type MOS tube NM4 and the drain electrode of the sixth N-type MOS tube NM 6;
the drain electrode of the fourth N-type MOS tube NM4 is respectively connected with a Sig_in signal and the source electrode of the fifth N-type MOS tube NM 5; the drain electrode of the fifth N-type MOS tube NM5 is connected with a Sig_out signal;
the grid electrode of the sixth N-type MOS tube NM6 is connected with a Clkb signal, and the emitter electrode of the sixth N-type MOS tube NM6 is grounded;
the grid electrode of the seventh N-type MOS tube NM7 is connected with the power supply voltage VDD, and the emitter electrode of the seventh N-type MOS tube NM7 is connected with the drain electrode of the eighth N-type MOS tube NM 8; and the grid electrode of the eighth N-type MOS tube NM8 is connected with a Clkb signal, and the emitter electrode of the eighth N-type MOS tube NM8 is grounded.
2. A bootstrap switch, characterized by: the bootstrap switch comprising the bootstrap switch sampling circuit of claim 1.
3. A data conversion system, characterized by: the data conversion system comprising the bootstrapped switch sampling circuit of claim 1.
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| CN202223582197.3U CN219107425U (en) | 2022-12-31 | 2022-12-31 | Bootstrap switch sampling circuit, bootstrap switch and data conversion system |
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| CN202223582197.3U CN219107425U (en) | 2022-12-31 | 2022-12-31 | Bootstrap switch sampling circuit, bootstrap switch and data conversion system |
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| CN219107425U true CN219107425U (en) | 2023-05-30 |
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