CN219087104U - Power amplifying circuit and radio frequency front end module - Google Patents
Power amplifying circuit and radio frequency front end module Download PDFInfo
- Publication number
- CN219087104U CN219087104U CN202222968569.XU CN202222968569U CN219087104U CN 219087104 U CN219087104 U CN 219087104U CN 202222968569 U CN202222968569 U CN 202222968569U CN 219087104 U CN219087104 U CN 219087104U
- Authority
- CN
- China
- Prior art keywords
- circuit
- coupled
- capacitor
- amplifying circuit
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Amplifiers (AREA)
Abstract
The application provides a power amplifying circuit, comprising: a primary amplifying circuit, a secondary amplifying circuit and an inter-stage matching circuit; an input end of the primary amplifying circuit is coupled to an input end of the power amplifying circuit, and an output end of the primary amplifying circuit is coupled to an input end of the inter-stage matching circuit; the input end of the secondary amplifying circuit is coupled to the output end of the interstage matching circuit, the output end of the secondary amplifying circuit is coupled to the interstage matching circuit of the output end of the power amplifying circuit, and the interstage matching circuit is coupled between the output end of the primary amplifying circuit and the input end of the secondary amplifying circuit, wherein the interstage matching circuit comprises a first inductor, a first capacitor, a second capacitor and a first balun. In the application, the first inductor, the first capacitor, the second capacitor and the balun are used as the inter-stage matching circuit in the power amplification circuit, so that the inter-stage matching circuit has better matching performance, the occupied area of the inter-stage matching circuit can be reduced, and the integration level of the power amplification circuit can be improved.
Description
Technical Field
The application relates to the technical field of radio frequency, in particular to a power amplifying circuit and a radio frequency front end module.
Background
The main function of the rf power amplifier is to convert a lower power rf signal into a higher power rf signal, and typically, the rf power amplifier is used to drive an antenna in a transmitter, amplify the modulated rf signal to a desired power value, and transmit the modulated rf signal through the antenna.
In general, a radio frequency power amplifier may include a multi-stage amplifying circuit, and an impedance matching circuit needs to be provided between the amplifying circuits of different stages so that an output impedance of an amplifying circuit of a previous stage and an impedance of an output of an amplifying circuit of a next stage are impedance-matched.
At present, the size of the rf power amplifier is smaller and smaller, and the existing impedance matching circuit needs to occupy more circuit area, which makes the design of the rf power amplifier difficult.
Disclosure of Invention
The purpose of the present application is: a power amplifying circuit and a radio frequency front end module are provided to solve the problem that an impedance matching circuit occupies too large circuit area in the power amplifying circuit.
In order to achieve the above object, the present application provides a power amplifying circuit including: a primary amplifying circuit, a secondary amplifying circuit and an inter-stage matching circuit, wherein;
an input of the primary amplifying circuit is coupled to an input of the power amplifying circuit, and an output of the primary amplifying circuit is coupled to an input of the inter-stage matching circuit;
an input end of the secondary amplifying circuit is coupled to an output end of the interstage matching circuit, and an output end of the secondary amplifying circuit is coupled to an output end of the power amplifying circuit;
the interstage matching circuit is coupled between the output end of the primary amplifying circuit and the input end of the secondary amplifying circuit, and comprises a first inductor, a first capacitor, a second capacitor and a first balun, wherein the first balun comprises a first winding and a second winding, a first end of the first inductor is coupled to a power supply end, and a second end of the first inductor is coupled to a first end of the first capacitor; a first end of the first capacitor is coupled to a second end of the first inductor, and a second end of the first capacitor is coupled to a ground terminal; a first end of the second capacitor is coupled to a second end of the first inductor, and a second end of the second capacitor is coupled to a first end of the first winding; a first end of the first winding is coupled to a second end of the first capacitor, and a second end of the first winding is coupled to a ground terminal; the first and second ends of the second winding are coupled to the output ends of the inter-stage matching circuit, respectively.
Further, preferably, the balun is made by a two-layer thick metal or a three-layer thick metal process.
Further, preferably, the first capacitance is a variable capacitance or a fixed capacitance.
Further, preferably, the primary amplifying circuit is a single-ended amplifying circuit, and the secondary amplifying circuit is a differential amplifying circuit.
Further, preferably, the value of the first inductor ranges from 0.5nH to 1.0 nH.
Further, preferably, the working frequency of the power amplifying circuit is 1200MHz-2300MHz, and the value ranges of the first capacitor and the second capacitor are all between [1pF-3pF ].
Further, preferably, the working frequency of the power amplifying circuit is 2300MHz-2700MHz, and the value ranges of the first capacitor and the second capacitor are both between [1.3pF-4.5pF ].
Further, preferably, the primary amplifying circuit includes a first primary amplifying transistor, and the secondary amplifying circuit includes a first secondary amplifying transistor and a second secondary amplifying transistor, an output terminal of the first primary amplifying transistor is coupled to an input terminal of the inter-stage matching circuit, and output terminals of the inter-stage matching circuit are coupled to input terminals of the first secondary amplifying transistor and the second secondary amplifying transistor, respectively.
Further preferably, the first primary amplifying transistor is a bipolar junction transistor, including a base, a collector and an emitter, the base of the first primary amplifying transistor receiving a radio frequency input signal, the collector of the first primary amplifying transistor being coupled to a first end of the inter-stage matching network, the emitter of the first primary amplifying transistor being grounded; the first secondary amplifying transistor is a bipolar junction transistor and comprises a base electrode, a collector electrode and an emitter electrode, wherein the base electrode of the first secondary amplifying transistor receives a radio frequency input signal, the collector electrode of the first secondary amplifying transistor is coupled to the output end of the power amplifying circuit, and the emitter electrode of the first secondary amplifying transistor is grounded; the second secondary amplifying transistor is a bipolar junction transistor and comprises a base electrode, a collector electrode and an emitter electrode, the base electrode of the second secondary amplifying transistor receives a radio frequency input signal, the collector electrode of the first secondary amplifying transistor is coupled to the output end of the power amplifying circuit, and the emitter electrode of the second secondary amplifying transistor is grounded.
The application also provides a radio frequency front end module, which comprises the power amplifying circuit.
Compared with the related art, the power amplification circuit has the beneficial effects that:
the power amplifying circuit provided in the embodiment of the application includes: a primary amplifying circuit, a secondary amplifying circuit and an inter-stage matching circuit, wherein; an input of the primary amplifying circuit is coupled to an input of the power amplifying circuit, and an output of the primary amplifying circuit is coupled to an input of the inter-stage matching circuit; an input end of the secondary amplifying circuit is coupled to an output end of the interstage matching circuit, and an output end of the secondary amplifying circuit is coupled to an output end of the power amplifying circuit; the interstage matching circuit is coupled between the output end of the primary amplifying circuit and the input end of the secondary amplifying circuit, and comprises a first inductor, a first capacitor and a second capacitor, wherein the first end of the first inductor is coupled to the power supply end, and the second end of the first inductor is coupled to the first end of the first capacitor; a first end of the first capacitor is coupled to a second end of the first inductor, and a second end of the first capacitor is coupled to a ground terminal; the first end of the second capacitor is coupled to the second end of the first inductor, and the second end of the second capacitor is coupled to the output end of the interstage matching circuit. In the application, the first inductor, the first capacitor, the second capacitor and the first balun are used as the inter-stage matching circuit in the power amplifying circuit, so that the inter-stage matching circuit has better matching performance, the occupied area of the inter-stage matching circuit can be reduced, and the integration level of the power amplifying circuit can be improved.
Drawings
Fig. 1 is a schematic diagram of an overall architecture of a power amplifying circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an inter-stage matching circuit according to an embodiment of the present application;
fig. 3 is a schematic diagram of a configuration of an inter-stage matching circuit in the related art;
fig. 4 is a schematic structural diagram of another power amplifying circuit according to an embodiment of the present application.
In the figure: 1. a power amplifying circuit; 10. a primary amplifying circuit; 11. the interstage matching circuit of the application; 12. a secondary amplifying circuit; 13. an inter-stage matching circuit in the related art; c1, a first capacitor; c2, a second capacitor; c3, a third capacitor; c4, a fourth capacitor; c5, a fifth capacitor; l1, a first inductor; l2, a second inductor; t1, a first balun; t2, second balun.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for the same elements throughout for clarity.
It will be understood that when an element or layer is referred to as being "on" …, "" adjacent to "…," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" …, "" directly adjacent to "…," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under …," "under …," "below," "under …," "above …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under …" and "under …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For a thorough understanding of the present application, detailed structures and steps are set forth in the following description in order to illustrate the technical solutions set forth herein. Preferred embodiments of the present application are described in detail below, however, the present application may have other implementations in addition to these detailed descriptions.
The power amplifying circuit 1 provided in the embodiment of the present application, as shown in fig. 1, includes: a primary amplifying circuit 10, a secondary amplifying circuit 11, and an inter-stage matching circuit 11, wherein;
an input of the primary amplifying circuit is coupled to an input of the power amplifying circuit, and an output of the primary amplifying circuit is coupled to an input of the inter-stage matching circuit;
specifically, it is understood that the primary amplifying circuit 10 may be a single-ended power amplifying circuit 10 or a differential power amplifying circuit 10.
In one embodiment, the single-ended power amplifying circuit 10 may be a power amplifying circuit 10 including one power amplifier, or may include a plurality of power amplifiers, and the plurality of power amplifiers may be the power amplifying circuit 10 having a cascade (serial) structure. The single-ended power amplifying circuit 10 may be a power amplifying circuit 10 including one power amplifier.
In a specific embodiment, the differential power amplifying circuit 10 may be a push-pull power amplifying circuit 10 or a doherty power amplifying circuit 10. As an example, the push-pull power amplification circuit 10 or the doherty power amplification circuit 10 includes a first differential amplification branch and a second differential amplification branch. The first differential amplifying branch and the second differential amplifying branch may each include one power amplifier, or may include a plurality of power amplifiers in a cascade structure.
Optionally, the power amplifier in the above embodiment includes one or more power amplifying transistors. Alternatively, the power amplifying transistor may be a BJT transistor or a field effect transistor.
An input end of the secondary amplifying circuit is coupled to an output end of the interstage matching circuit, and an output end of the secondary amplifying circuit is coupled to an output end of the power amplifier;
specifically, it is understood that the secondary amplifying circuit 12 may be a single-ended amplifying circuit 11 or a differential amplifying circuit 12.
In one embodiment, the single-ended amplifying circuit 12 may be the power amplifying circuit 11 including one power amplifier, or may include a plurality of power amplifiers, and the plurality of power amplifiers may be the power amplifying circuit 12 having a cascade (serial) structure. The single-ended power amplifying circuit 12 may be a power amplifying circuit comprising one power amplifier.
In a specific embodiment, the differential power amplifying circuit 12 may be a push-pull power amplifying circuit 11 or a doherty power amplifying circuit 12. As an example, the push-pull power amplification circuit 12 or the doherty power amplification circuit 12 includes a first differential amplification branch and a second differential amplification branch. The first differential amplifying branch and the second differential amplifying branch may each include one power amplifier, or may include a plurality of power amplifiers in a cascade structure.
Optionally, the power amplifier in the above embodiment includes one or more power amplifying transistors. Alternatively, the power amplifying transistor may be a BJT transistor or a field effect transistor.
In the present application, the primary amplifying circuit is a single-ended amplifying circuit, and the secondary circuit is a differential amplifying circuit.
The inter-stage matching circuit 11 is coupled between the output end of the primary amplifying circuit 10 and the input end of the secondary amplifying circuit 11, the inter-stage matching circuit 11 comprises a first inductor L1, a first capacitor C1, a second capacitor C2 and a first balun T1, wherein the first balun T1 comprises a first winding and a second winding, a first end of the first inductor L1 is coupled to a power supply end, and a second end of the first inductor L1 is coupled to a first end of the first capacitor C1; a first end of the first capacitor C1 is coupled to a second end of the first inductor L1, and a second end of the first capacitor C1 is coupled to a ground terminal; a first end of the second capacitor C2 is coupled to a second end of the first inductor L1, and a second end of the second capacitor C2 is coupled to a first end of the first winding; a first end of the first winding is coupled to a second end of the first capacitor C1, and a second end of the first winding is coupled to a ground terminal; the first and second ends of the second winding are coupled to the output of the inter-stage matching circuit 11, respectively.
Specifically, it will be appreciated that in this embodiment, the inter-stage matching circuit 11 is coupled between the output of the primary amplifying circuit 10 and the input of the secondary amplifying circuit 11 for providing impedance matching for the power amplifying circuit 100.
In a specific embodiment, as shown in fig. 2, the inter-stage matching circuit 11 includes a first inductor L1, a first capacitor C1, a second capacitor C2, and a first balun T1, where a first end of the first inductor L1 is coupled to a power supply terminal, and a second end of the first inductor L1 is coupled to a first end of the first capacitor C1; a first end of the first capacitor C1 is coupled to a second end of the first inductor L1, and a second end of the first capacitor C1 is coupled to a ground terminal; a first end of the second capacitor C2 is coupled to a second end of the first inductor L1, and a second end of the second capacitor C2 is coupled to a first end of the first winding; a first end of the first winding is coupled to a second end of the first capacitor C1, and a second end of the first winding is coupled to a ground terminal; the first and second ends of the second winding are coupled to the output of the inter-stage matching circuit 11, respectively.
It should be noted that, in general, the inductance is realized by providing a metal winding on a substrate, and the length of the metal winding increases as the inductance required increases, that is, the greater the inductance, the longer the length of the metal winding is required, so that the occupied area of the metal winding on the substrate is also the greater the inductance, that is, the greater the substrate area occupied on the substrate is for the inductance made by winding of the same specification.
As shown in fig. 3, the circuit is an inter-stage matching circuit 13 in the related art, in the inter-stage matching circuit 13, the impedance matching function of the inter-stage matching circuit 13 is completed by the second inductor L2, the fifth capacitor C5 and the balun, while in the present embodiment, the impedance matching function of the inter-stage matching circuit 11 is completed by the capacitor C1, the second capacitor C2, the first inductor L1 and the first balun T1, and the inter-stage matching circuit 13 is completed by one capacitor C1, the second capacitor C2, the first inductor L1 and the first balun T1, so that the inductance of the first inductor L1 is generally smaller than the inductance of the second inductor L2 on the premise of realizing the same impedance matching function, that is, the occupied area of the substrate of the first inductor L1 is necessarily smaller than the occupied area of the substrate of the second inductor L2, therefore, the inter-stage matching circuit 11 is necessarily smaller than the power matching circuit 11 by the other amplifier modules, and the power modules are necessarily designed to have smaller power amplifier areas than the other power modules.
Although the inter-stage matching circuit 11 provided in the present application has one capacitor more than the inter-stage matching circuit 13 in the related art, the area of the inter-stage matching circuit 11 is smaller than the inter-stage matching circuit 13 in terms of the overall area, because the occupied area of the capacitor on the substrate is much smaller than that of the inductor, and therefore, even if one capacitor is added more, the overall area is still smaller.
The power amplifying circuit provided in this embodiment includes: a primary amplifying circuit, a secondary amplifying circuit and an inter-stage matching circuit, wherein; an input of the primary amplifying circuit is coupled to an input of the power amplifying circuit, and an output of the primary amplifying circuit is coupled to an input of the inter-stage matching circuit; an input end of the secondary amplifying circuit is coupled to an output end of the interstage matching circuit, and an output end of the secondary amplifying circuit is coupled to an output end of the power amplifying circuit; the interstage matching circuit is coupled between the output end of the primary amplifying circuit and the input end of the secondary amplifying circuit, and comprises a first inductor, a first capacitor, a second capacitor and a balun, wherein the balun comprises a first winding and a second winding, a first end of the first inductor is coupled to a power supply end, and a second end of the first inductor is coupled to a first end of the first capacitor; a first end of the first capacitor is coupled to a second end of the first inductor, and a second end of the first capacitor is coupled to a ground terminal; a first end of the second capacitor is coupled to a second end of the first inductor, and a second end of the second capacitor is coupled to a first end of the first winding; a first end of the first winding is coupled to a second end of the first capacitor, and a second end of the first winding is coupled to a ground terminal; the first and second ends of the second winding are coupled to the output ends of the inter-stage matching circuit, respectively. In this embodiment, by using the first inductor, the first capacitor, the second capacitor and the first balun as the inter-stage matching circuit in the power amplifying circuit, not only can the matching performance of the inter-stage matching circuit be better, but also the occupied area of the inter-stage matching circuit can be reduced, so that the design difficulty of the power amplifying circuit can be reduced to a certain extent, and the integration level of the power amplifying circuit can be further provided.
In one embodiment of the present application, the first balun T1 is made by a two-layer thick metal or a three-layer thick metal process.
Specifically, it will be appreciated that the first balun T1 may be manufactured by selecting a suitable manufacturing process according to actual requirements, and, for example, when it is required to provide the integration level of the first balun T1, two layers of thick metal may be selected to manufacture the first balun T1; when it is desired to improve the performance of the first balun T1, a third layer thickness metal may be selected to make the first balun T1.
In one embodiment of the present application, the first capacitor is a variable capacitor or a fixed capacitor.
Specifically, it is understood that in the present embodiment, the first capacitance C1 may be a variable capacitance or a fixed capacitance.
In a specific embodiment, when the power amplification circuit needs to be used in different frequency bands, the inter-stage matching circuit 11 needs to provide different impedances to perform impedance matching, but because components in the inter-stage matching circuit are all fixed parameters and are difficult to adjust, in this embodiment, the first capacitor C1 is a variable capacitor component, so that the inter-stage matching circuit 11 can provide different impedances to perform impedance matching, and further the power amplification circuit is used in different frequency bands.
In one embodiment of the present application, the primary amplifying circuit 10 is a single-ended amplifying circuit, and the secondary amplifying circuit 12 is a differential amplifying circuit.
In one embodiment of the present application, the value of the first inductor L1 ranges from 0.5nH to 1.0 nH.
Specifically, it can be understood that in this embodiment, the value of the first inductor may be 0.5nH, 0.7nH, 0.8nH, 0.9nH, 1.0nH, etc.; for example, in fig. 2, the inter-stage matching circuit 11 includes a first inductor L1, a first capacitor C1, a second capacitor C2 and a first balun T1, where the value of the first inductor may be 0.8nH, and in order to achieve the impedance matching effect of the inter-stage matching 11, since only the fifth capacitor C5 is present in the inter-stage matching 12 in the related art, the value of the second inductor of the inter-stage matching circuit 11 needs to be at least 1.0nH or more, that is, the first inductor C1 in the inter-stage matching circuit 11 in the related art may be at least 0.2nH or more less than the inter-stage matching circuit 13 in the related art. Because the larger the value of the inductor is, the larger the occupied area on the substrate is, therefore, the occupied area of the first inductor in the application is necessarily smaller than the occupied area of the second inductor in the related art, and further, the occupied area of the inter-stage matching circuit 11 provided by the application is also necessarily smaller than the inter-stage matching circuit 13 in the related art, so that the integration level of the power amplifying circuit can be provided.
In an embodiment of the present application, the working frequency of the power amplifying circuit is 1700MHz-2100MHz, and the value ranges of the first capacitor and the second capacitor are both between [1pF-3pF ].
Specifically, it is understood that the corresponding operating frequency band of 1700MHz-2100MHz may be n1 band/n 2 band/n 3 band. When the power amplification circuit supports radio frequency signal transmission with the working frequency band of 1700MHz-2100MHz, the capacitance values of the first capacitor C1 and the second capacitor C2 are both between [1pF-3pF ]. For example: the capacitance values of the first capacitor C1 and the second capacitor C2 may be 1pF, 1.2pF, 1.5pF, 1.8pF, 2pF, 2.5pF, 3pF, etc.
In an embodiment of the present application, the working frequency of the power amplifying circuit is 2300MHz-2700MHz, and the value ranges of the first capacitor and the second capacitor are both between [1.3pF-4.5pF ].
Specifically, it is understood that the working frequency band corresponding to 2300MHz-2700MHz may be N41 frequency band/N40 frequency band/N7 frequency band, etc. When the power amplification circuit supports radio frequency signal transmission with the working frequency band of 2300MHz-2700MHz, the capacitance values of the first capacitor C1 and the second capacitor C2 are both between [1.3pF-4.5pF ]. For example: the capacitance values of the first capacitor C1 and the second capacitor C2 may be 1.3pF, 2pF, 2.1pF, 3pF, 3.5pF, 4.5pF, etc.
In an embodiment of the present application, as shown in fig. 4, the primary amplifying circuit 10 includes a first primary amplifying transistor M1, the secondary amplifying circuit 11 includes a first secondary amplifying transistor M2 and a second secondary amplifying transistor M3, an output terminal of the first primary amplifying transistor 101 is coupled to an input terminal of the inter-stage matching circuit 11, and output terminals of the inter-stage matching circuit 11 are respectively coupled to input terminals of the first secondary amplifying transistor M2 and the second secondary amplifying transistor M3.
In particular, it is understood that the first primary amplifying transistor, the first secondary amplifying transistor and the second secondary amplifying transistor may be BJT transistors or Field Effect Transistors (FETs). Optionally, the first primary amplifying transistor 101 comprises at least one BJT transistor (e.g. HBT transistor) or at least one field effect transistor. The first differential amplifying transistor M1 may be formed by connecting a plurality of BJT transistors in parallel, for example.
The first secondary amplifying transistor M2 includes at least one BJT transistor (e.g., HBT transistor) or at least one field effect transistor. For example, the first secondary amplifying transistor 111 may be formed by connecting a plurality of BJT transistors in parallel. The second secondary amplifying transistor M3 includes at least one BJT transistor (e.g., HBT transistor) or at least one field effect transistor. The second secondary amplifying transistor M3 may be formed by connecting a plurality of BJT transistors in parallel, for example. It will be appreciated that the first secondary amplifying transistor M2 and the second secondary amplifying transistor M3 may be a first differential amplifying transistor and a second differential amplifying transistor in a differential amplifying circuit, and any one of the above differential power amplifying circuits may be, for example, any one of a driving stage, an intermediate stage, or an output stage.
In an embodiment, the first secondary amplifying transistor 111 is configured to amplify a first rf input signal and output a first rf amplified signal (amplified first rf input signal), the second secondary amplifying transistor M3 is configured to amplify a second rf input signal and output a second rf amplified signal (amplified second rf input signal), and the first balun converts and synthesizes the first rf amplified signal and the second rf amplified signal and outputs an rf output signal. The fifth capacitor C5 may block the dc signal in the first rf amplified signal, and the sixth capacitor C6 may block the dc signal in the second rf amplified signal, so as to avoid the influence of the dc signal. The first rf input signal may be an rf signal output after being amplified by a corresponding pre-amplifying circuit, or may be one of balanced rf signals obtained by converting an unbalanced input rf signal. Similarly, the second rf input signal may be an rf signal output after being amplified by the corresponding pre-amplifying circuit, or may be one of balanced rf signals obtained by converting an unbalanced input rf signal.
In one embodiment of the present application, the first primary amplifying transistor is a bipolar junction transistor, including a base, a collector and an emitter, the base of the first primary amplifying transistor receiving a radio frequency input signal, the collector of the first primary amplifying transistor being coupled to a first end of the inter-stage matching network, the emitter of the first primary amplifying transistor being grounded; the first secondary amplifying transistor is a bipolar junction transistor and comprises a base electrode, a collector electrode and an emitter electrode, wherein the base electrode of the first secondary amplifying transistor receives a radio frequency input signal, the collector electrode of the first secondary amplifying transistor is coupled to the output end of the power amplifying circuit, and the emitter electrode of the first secondary amplifying transistor is grounded; the second secondary amplifying transistor is a bipolar junction transistor and comprises a base electrode, a collector electrode and an emitter electrode, the base electrode of the second secondary amplifying transistor receives a radio frequency input signal, the collector electrode of the first secondary amplifying transistor is coupled to the output end of the power amplifier, and the emitter electrode of the second secondary amplifying transistor is grounded.
The application also provides a radio frequency front end module, which comprises the power amplifying circuit.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. A power amplification circuit, comprising: a primary amplifying circuit, a secondary amplifying circuit and an inter-stage matching circuit, wherein;
an input of the primary amplifying circuit is coupled to an input of the power amplifying circuit, and an output of the primary amplifying circuit is coupled to an input of the inter-stage matching circuit;
an input end of the secondary amplifying circuit is coupled to an output end of the interstage matching circuit, and an output end of the secondary amplifying circuit is coupled to an output end of the power amplifying circuit;
the interstage matching circuit is coupled between the output end of the primary amplifying circuit and the input end of the secondary amplifying circuit, and comprises a first inductor, a first capacitor, a second capacitor and a first balun, wherein the first balun comprises a first winding and a second winding, a first end of the first inductor is coupled to a power supply end, and a second end of the first inductor is coupled to a first end of the first capacitor; a first end of the first capacitor is coupled to a second end of the first inductor, and a second end of the first capacitor is coupled to a ground terminal; a first end of the second capacitor is coupled to a second end of the first inductor, and a second end of the second capacitor is coupled to a first end of the first winding; a first end of the first winding is coupled to a second end of the first capacitor, and a second end of the first winding is coupled to a ground terminal; the first and second ends of the second winding are coupled to the output ends of the inter-stage matching circuit, respectively.
2. The power amplifying circuit according to claim 1, wherein the balun is made using a two-layer thick metal or a three-layer thick metal process.
3. The power amplification circuit of claim 1, wherein the first capacitance is a variable capacitance or a fixed capacitance.
4. The power amplification circuit of claim 1, wherein the primary amplification circuit is a single-ended amplification circuit and the secondary amplification circuit is a differential amplification circuit.
5. The power amplification circuit of claim 1, wherein the first inductance has a value in a range of [0.5nH-1.0nH ].
6. The power amplification circuit of claim 1, wherein the power amplification circuit has an operating frequency of 1200MHz-2300MHz, and the first capacitor and the second capacitor each have a value in a range of [1pF-3pF ].
7. The power amplification circuit of claim 1, wherein the power amplification circuit has an operating frequency of 2300MHz-2700MHz, and the first capacitor and the second capacitor each have a value in the range of [1.3pF-4.5pF ].
8. The power amplifying circuit according to claim 1, wherein the primary amplifying circuit comprises a first primary amplifying transistor, the secondary amplifying circuit comprises a first secondary amplifying transistor and a second secondary amplifying transistor, an output of the first primary amplifying transistor is coupled to an input of the inter-stage matching circuit, and an output of the inter-stage matching circuit is coupled to an input of the first secondary amplifying transistor and an input of the second secondary amplifying transistor, respectively.
9. The power amplification circuit of claim 8, wherein the first primary amplification transistor is a bipolar junction transistor comprising a base, a collector, and an emitter, the base of the first primary amplification transistor receiving a radio frequency input signal, the collector of the first primary amplification transistor being coupled to a first end of the inter-stage matching network, the emitter of the first primary amplification transistor being grounded; the first secondary amplifying transistor is a bipolar junction transistor and comprises a base electrode, a collector electrode and an emitter electrode, wherein the base electrode of the first secondary amplifying transistor receives a radio frequency input signal, the collector electrode of the first secondary amplifying transistor is coupled to the output end of the power amplifying circuit, and the emitter electrode of the first secondary amplifying transistor is grounded; the second secondary amplifying transistor is a bipolar junction transistor and comprises a base electrode, a collector electrode and an emitter electrode, the base electrode of the second secondary amplifying transistor receives a radio frequency input signal, the collector electrode of the first secondary amplifying transistor is coupled to the output end of the power amplifying circuit, and the emitter electrode of the second secondary amplifying transistor is grounded.
10. A radio frequency front end module comprising a power amplifying circuit according to any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222968569.XU CN219087104U (en) | 2022-11-08 | 2022-11-08 | Power amplifying circuit and radio frequency front end module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222968569.XU CN219087104U (en) | 2022-11-08 | 2022-11-08 | Power amplifying circuit and radio frequency front end module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219087104U true CN219087104U (en) | 2023-05-26 |
Family
ID=86403239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222968569.XU Active CN219087104U (en) | 2022-11-08 | 2022-11-08 | Power amplifying circuit and radio frequency front end module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219087104U (en) |
-
2022
- 2022-11-08 CN CN202222968569.XU patent/CN219087104U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101282110B (en) | Low-power consumption single-ended input difference output low-noise amplifier | |
| CN112187194B (en) | Push-pull power amplifier, radio frequency front-end circuit and wireless device | |
| CN101764581B (en) | Integrated power amplifier for use in wireless communication devices | |
| JP5512731B2 (en) | Two-stage microwave class E power amplifier | |
| CN216390932U (en) | MMIC radio frequency power amplifier | |
| CN112583369B (en) | Dual-frequency millimeter wave low-noise amplifier | |
| CN114024512B (en) | Ultra-wideband low noise amplifier of frequency division duplex | |
| CN215990714U (en) | Radio frequency power amplifier and radio frequency front end architecture applied to 5G communication system | |
| CN110034738B (en) | Ultra-wideband low-noise amplifier based on improved impedance matching network | |
| CN101478290A (en) | Method for improving linearity of multi-stage power amplifier circuit and circuit therefor | |
| CN112202408A (en) | Cascode radio frequency amplifier of GaN technology | |
| CN113541615B (en) | Multistage low noise amplifier capable of reducing cost | |
| CN111628737A (en) | Improved ultra-wideband high-efficiency power amplifier | |
| CN213243932U (en) | Radio frequency power amplification system and radio frequency front end module | |
| US20130293295A1 (en) | Compact rf power amplifier | |
| CN219087104U (en) | Power amplifying circuit and radio frequency front end module | |
| CN107809220B (en) | Low noise amplifier, radio frequency integrated circuit, signal receiving module and radio frequency transceiver chip | |
| CN216056945U (en) | Three-path power synthesis radio frequency power amplifier based on transformer matching | |
| CN115913151A (en) | Radio frequency push-pull power amplification circuit and radio frequency push-pull power amplifier | |
| CN112511114B (en) | Low-noise amplifier with power distribution function | |
| CN112003574A (en) | K-waveband CMOS high-efficiency radio frequency power amplifier circuit | |
| CN117674736A (en) | Push-pull power amplifying circuit and radio frequency front end module | |
| CN100596017C (en) | Step travel wave amplifier circuit | |
| CN221058266U (en) | Radio frequency power amplifier and radio frequency front end module | |
| CN115913152B (en) | Push-pull power amplifying circuit and radio frequency front end module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |